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timing hack removed, seems to be no longer needed

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@242 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2007-09-08 20:28:09 +00:00
parent e28a980fb7
commit d5715559cf
6 changed files with 5 additions and 17 deletions
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12
cpu/Cyclone/OpLogic.cpp
View file

@ -143,16 +143,8 @@ int OpNeg(int op)
use=OpBase(op,size);
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
OpStart(op,ea); Cycles=size<2?4:6;
if(ea >= 0x10) {
Cycles*=2;
#if CYCLONE_FOR_GENESIS
// This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
// May be this is similar case as with TAS opcode, but this time the dummy
// read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
if(type==1&&size<2) Cycles-=2;
#endif
}
OpStart(op,ea); Cycles=size<2?4:6;
if(ea >= 0x10) Cycles*=2;
EaCalc (10,0x003f,ea,size,0,0);

1
cpu/Cyclone/config.h
View file

@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
* This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0

1
cpu/Cyclone/config_mamegp2x.h
View file

@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
* This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0

3
cpu/Cyclone/config_pico.h
View file

@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
* This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 2
@ -58,7 +57,7 @@
* MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle
* count and this will screw timing (if not cause a deadlock).
*/
#define MEMHANDLERS_NEED_PC 1
#define MEMHANDLERS_NEED_PC 0
#define MEMHANDLERS_NEED_PREV_PC 0
#define MEMHANDLERS_NEED_FLAGS 0
#define MEMHANDLERS_NEED_CYCLES 1

1
cpu/Cyclone/config_uae4all.h
View file

@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
* This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0