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pollux overclocking with dividers

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@724 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2009-08-01 14:33:09 +00:00
parent 4b973b8919
commit d737d9e3f5
1 changed files with 12 additions and 4 deletions
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16
platform/gp2x/pollux_set.c
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@ -196,8 +196,8 @@ static int apply_cpuclk(volatile unsigned short *memregs, void *data)
{ {
volatile unsigned int *memregl = (volatile void *)memregs; volatile unsigned int *memregl = (volatile void *)memregs;
int mhz = *(int *)data; int mhz = *(int *)data;
int mdiv, pdiv, sdiv = 0; int adiv, mdiv, pdiv, sdiv = 0;
int i, v; int i, vf000, vf004;
// m = MDIV, p = PDIV, s = SDIV // m = MDIV, p = PDIV, s = SDIV
#define SYS_CLK_FREQ 27 #define SYS_CLK_FREQ 27
@ -205,13 +205,21 @@ static int apply_cpuclk(volatile unsigned short *memregs, void *data)
mdiv = (mhz * pdiv) / SYS_CLK_FREQ; mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
if (mdiv & ~0x3ff) if (mdiv & ~0x3ff)
return -1; return -1;
v = (pdiv<<18) | (mdiv<<8) | sdiv; vf004 = (pdiv<<18) | (mdiv<<8) | sdiv;
memregl[0xf004>>2] = v; // attempt to keep AHB the divider close to 250, but not higher
for (adiv = 1; mhz / adiv > 250; adiv++)
;
vf000 = memregl[0xf000>>2];
vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6);
memregl[0xf000>>2] = vf000;
memregl[0xf004>>2] = vf004;
memregl[0xf07c>>2] |= 0x8000; memregl[0xf07c>>2] |= 0x8000;
for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
; ;
printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);
return 0; return 0;
} }