mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
sh2 drc: add mipsel backend for MIPS32 Release 1 (for JZ47xx)
This commit is contained in:
kub
parent
1747b6712d
commit
d80a5fd2ab
13 changed files with 1922 additions and 23 deletions
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@ -169,7 +169,7 @@ DEFINES += DRC_DEBUG=$(drc_debug)
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SRCS_COMMON += $(R)cpu/sh2/mame/sh2dasm.c
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DASM = $(R)platform/libpicofe/linux/host_dasm.c
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DASMLIBS = -lbfd -lopcodes -liberty
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ifeq "$(ARCH)" "arm"
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ifeq ("$(ARCH)",$(filter "$(ARCH)","arm" "mipsel"))
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ifeq ($(filter_out $(shell $(CC) --print-file-name=libbfd.so),"/"),)
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DASM = $(R)platform/common/host_dasm.c
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DASMLIBS =
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@ -435,7 +435,7 @@ static int software_interrupt(unsigned int pc, unsigned int insn, char *buf, siz
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return 1;
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}
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int disarm(unsigned int pc, unsigned int insn, char *buf, size_t buf_len)
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int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len)
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{
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if ((insn & 0x0fffffd0) == 0x012fff10)
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return branch_and_exchange(pc, insn, buf, buf_len);
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@ -23,6 +23,6 @@
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#ifndef DISARM_H
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#define DISARM_H
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int disarm(unsigned int pc, unsigned int insn, char *buf, unsigned int buf_len);
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int disarm(uintptr_t long pc, uint32_t, char *buf, unsigned int buf_len);
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#endif /* DISARM_H */
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346
platform/common/dismips.c
Normal file
346
platform/common/dismips.c
Normal file
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@ -0,0 +1,346 @@
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/*
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* very basic mips disassembler for MIPS32/MIPS64 Release 1, only for picodrive
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* Copyright (C) 2019 kub
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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// XXX unimplemented: SYSCALL, BREAK, SYNC, SDBBP, T*, CACHE, PREF,
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// MOVF/MOVT, LWC*/LDC*, SWC*/SDC*, COP*.
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// however, it's certainly good enough for anything picodrive DRC throws at it.
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "dismips.h"
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static char *const register_names[32] = {
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"$zero",
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"$at",
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"$v0",
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"$v1",
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"$a0",
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"$a1",
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"$a2",
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"$a3",
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"$t0",
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"$t1",
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"$t2",
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"$t3",
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"$t4",
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"$t5",
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"$t6",
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"$t7",
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"$s0",
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"$s1",
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"$s2",
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"$s3",
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"$s4",
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"$s5",
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"$s6",
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"$s7",
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"$t8",
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"$t9",
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"$k0",
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"$k1",
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"$gp",
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"$sp",
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"$fp",
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"$ra"
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};
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enum insn_type {
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REG_DTS, REG_TS, // 3, 2, or 1 regs
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REG_DS, REG_D, REG_S,
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S_IMM_DT, // 2 regs with shift amount
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B_IMM_S, B_IMM_TS, // pc-relative branches with 1 or 2 regs
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J_IMM, // region-relative jump
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A_IMM_TS, // arithmetic immediate with 1 or 2 regs
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L_IMM_T, L_IMM_TS, // logical immediate with 2 regs
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M_IMM_TS, // memory indexed with 2 regs
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};
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struct insn {
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unsigned char op;
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enum insn_type type;
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char *name;
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};
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// ATTN: these array MUST be sorted by op (decode relies on it)
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// instructions with opcode SPECIAL (R-type)
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#define OP_SPECIAL 0x00
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static const struct insn special_insns[] = {
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{0x00, S_IMM_DT, "sll"},
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{0x02, S_IMM_DT, "srl"},
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{0x03, S_IMM_DT, "sra"},
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{0x04, REG_DTS, "sllv"},
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{0x06, REG_DTS, "srlv"},
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{0x07, REG_DTS, "srav"},
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{0x08, REG_S, "jr"},
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{0x09, REG_DS, "jalr"},
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{0x0a, REG_DTS, "movz"},
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{0x0b, REG_DTS, "movn"},
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// {0x0c, , "syscall"},
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// {0x0d, , "break"},
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// {0x0f, , "sync"},
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{0x10, REG_D, "mfhi"},
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{0x11, REG_S, "mthi"},
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{0x12, REG_D, "mflo"},
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{0x13, REG_S, "mtlo"},
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{0x14, REG_DTS, "dsllv"},
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{0x16, REG_DTS, "dslrv"},
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{0x17, REG_DTS, "dsrav"},
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{0x18, REG_TS, "mult"},
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{0x19, REG_TS, "multu"},
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{0x1A, REG_TS, "div"},
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{0x1B, REG_TS, "divu"},
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{0x1C, REG_TS, "dmult"},
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{0x1D, REG_TS, "dmultu"},
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{0x1E, REG_TS, "ddiv"},
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{0x1F, REG_TS, "ddivu"},
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{0x20, REG_DTS, "add"},
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{0x21, REG_DTS, "addu"},
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{0x22, REG_DTS, "sub"},
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{0x23, REG_DTS, "subu"},
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{0x24, REG_DTS, "and"},
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{0x25, REG_DTS, "or"},
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{0x26, REG_DTS, "xor"},
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{0x27, REG_DTS, "nor"},
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{0x2A, REG_DTS, "slt"},
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{0x2B, REG_DTS, "sltu"},
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{0x2C, REG_DTS, "dadd"},
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{0x2D, REG_DTS, "daddu"},
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{0x2E, REG_DTS, "dsub"},
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{0x2F, REG_DTS, "dsubu"},
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// {0x30, REG_TS, "tge" },
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// {0x31, REG_TS, "tgeu" },
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// {0x32, REG_TS, "tlt" },
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// {0x33, REG_TS, "tltu" },
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// {0x34, REG_TS, "teq" },
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// {0x36, REG_TS, "tne" },
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{0x38, S_IMM_DT, "dsll"},
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{0x3A, S_IMM_DT, "dsrl"},
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{0x3B, S_IMM_DT, "dsra"},
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{0x3D, S_IMM_DT, "dsll32"},
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{0x3E, S_IMM_DT, "dsrl32"},
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{0x3F, S_IMM_DT, "dsra32"},
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};
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// instructions with opcode SPECIAL2 (R-type)
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#define OP_SPECIAL2 0x1C
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static const struct insn special2_insns[] = {
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{0x00, REG_TS, "madd" },
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{0x01, REG_TS, "maddu" },
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{0x02, REG_TS, "mul" },
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{0x04, REG_TS, "msub" },
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{0x05, REG_TS, "msubu" },
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{0x20, REG_DS, "clz" },
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{0x21, REG_DS, "clo" },
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{0x24, REG_DS, "dclz" },
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{0x25, REG_DS, "dclo" },
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};
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// instructions with opcode REGIMM (I-type)
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#define OP_REGIMM 0x01
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static const struct insn regimm_insns[] = {
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{0x00, B_IMM_S, "bltz"},
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{0x01, B_IMM_S, "bgez"},
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{0x02, B_IMM_S, "bltzl"},
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{0x03, B_IMM_S, "bgezl"},
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// {0x08, , "tgei"},
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// {0x09, , "tgeiu"},
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// {0x0a, , "tlti"},
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// {0x0b, , "tltiu"},
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// {0x0c, , "teqi"},
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// {0x0e, , "tnei"},
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{0x10, B_IMM_S, "bltzal"},
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{0x11, B_IMM_S, "bgezal"},
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{0x12, B_IMM_S, "bltzall"},
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{0x13, B_IMM_S, "bgezall"},
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{0x13, B_IMM_S, "bgezall"},
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};
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// instructions with other opcodes (I-type)
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static const struct insn immediate_insns[] = {
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{0x02, J_IMM, "j"},
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{0x03, J_IMM, "jal"},
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{0x04, B_IMM_TS, "beq"},
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{0x05, B_IMM_TS, "bne"},
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{0x06, B_IMM_S, "blez"},
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{0x07, B_IMM_S, "bgtz"},
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{0x08, A_IMM_TS, "addi"},
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{0x09, A_IMM_TS, "addiu"},
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{0x0A, A_IMM_TS, "slti"},
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{0x0B, A_IMM_TS, "sltiu"},
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{0x0C, L_IMM_TS, "andi"},
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{0x0D, L_IMM_TS, "ori"},
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{0x0E, L_IMM_TS, "xori"},
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{0x0F, L_IMM_T, "lui"},
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{0x14, B_IMM_TS, "beql"},
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{0x15, B_IMM_TS, "bnel"},
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{0x16, B_IMM_S, "blezl"},
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{0x17, B_IMM_S, "bgtzl"},
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{0x18, A_IMM_TS, "daddi"},
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{0x19, A_IMM_TS, "daddiu"},
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{0x1A, M_IMM_TS, "ldl"},
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{0x1B, M_IMM_TS, "ldr"},
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{0x20, M_IMM_TS, "lb"},
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{0x21, M_IMM_TS, "lh"},
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{0x22, M_IMM_TS, "lwl"},
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{0x23, M_IMM_TS, "lw"},
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{0x24, M_IMM_TS, "lbu"},
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{0x25, M_IMM_TS, "lhu"},
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{0x26, M_IMM_TS, "lwr"},
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{0x27, M_IMM_TS, "lwu"},
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{0x28, M_IMM_TS, "sb"},
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{0x29, M_IMM_TS, "sh"},
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{0x2A, M_IMM_TS, "swl"},
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{0x2B, M_IMM_TS, "sw"},
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{0x2C, M_IMM_TS, "sdl"},
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{0x2D, M_IMM_TS, "sdr"},
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{0x2E, M_IMM_TS, "swr"},
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// {0x2F, , "cache"},
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{0x30, M_IMM_TS, "ll"},
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// {0x31, , "lwc1"},
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// {0x32, , "lwc2"},
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// {0x33, , "pref"},
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{0x34, M_IMM_TS, "lld"},
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// {0x35, , "ldc1"},
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// {0x36, , "ldc2"},
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{0x37, M_IMM_TS, "ld"},
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{0x38, M_IMM_TS, "sc"},
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// {0x39, , "swc1"},
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// {0x3A, , "swc2"},
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{0x3C, M_IMM_TS, "scd"},
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// {0x3D, , "sdc1"},
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// {0x3E, , "sdc2"},
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{0x3F, M_IMM_TS, "sd"},
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};
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#define ARRAY_SIZE(a) (sizeof(a)/sizeof(*a))
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// find instruction description for insn
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static const struct insn *decode_insn(uint32_t insn)
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{
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uint32_t op = insn >> 26;
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const struct insn *pi;
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int l = 0, r = 0;
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if (op == OP_SPECIAL) {
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op = insn & 0x3f;
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pi = special_insns;
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r = ARRAY_SIZE(special_insns)-1;
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} else if (op == OP_SPECIAL2) {
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op = insn & 0x3f;
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pi = special2_insns;
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r = ARRAY_SIZE(special2_insns)-1;
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} else if (op == OP_REGIMM) {
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op = (insn>>16) & 0x1f;
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pi = regimm_insns;
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r = ARRAY_SIZE(regimm_insns)-1;
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} else {
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pi = immediate_insns;
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r = ARRAY_SIZE(immediate_insns)-1;
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}
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while (l <= r) {
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int m = (l+r) / 2;
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if (pi[m].op == op)
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return pi+m;
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else if (pi[m].op < op)
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l = m+1;
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else
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r = m-1;
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}
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return NULL;
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}
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// calculate target for pc-relative branches
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static unsigned long b_target(unsigned long pc, uint32_t insn)
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{
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return pc + 4 + (int16_t)insn * 4;
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}
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// calculate target for region-relative branches
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static unsigned long j_target(unsigned long pc, uint32_t insn)
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{
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return (pc & ~0x0fffffffL) | ((insn & 0x03ffffff) << 2);
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}
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// main disassembler function
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int dismips(uintptr_t pc, uint32_t insn, char *buf, unsigned int buflen)
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{
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const struct insn *pi = decode_insn(insn);
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char *rs = register_names[(insn >> 21) & 0x1f];
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char *rt = register_names[(insn >> 16) & 0x1f];
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char *rd = register_names[(insn >> 11) & 0x1f];
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int sa = (insn >> 6) & 0x1f;
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int imm = (int16_t) insn;
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if (pi == NULL) {
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snprintf(buf, buflen, "0x%x", insn);
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return 0;
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}
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switch (pi->type) {
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case REG_DTS:
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if ((insn & 0x3f) == 0x25 /*OR*/ && (insn & 0x1f0000) == 0 /*zero*/)
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snprintf(buf, buflen, "move %s, %s", rd, rs);
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else
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snprintf(buf, buflen, "%s %s, %s, %s", pi->name, rd, rs, rt);
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break;
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case REG_TS:
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snprintf(buf, buflen, "%s %s, %s", pi->name, rs, rt);
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break;
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case REG_DS:
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snprintf(buf, buflen, "%s %s, %s", pi->name, rd, rs);
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break;
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case REG_D:
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snprintf(buf, buflen, "%s %s", pi->name, rd);
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break;
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case REG_S:
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snprintf(buf, buflen, "%s %s", pi->name, rs);
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break;
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case S_IMM_DT:
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if (insn == 0x00000000)
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snprintf(buf, buflen, "nop");
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else
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snprintf(buf, buflen, "%s %s, %s, %d", pi->name, rd, rt, sa);
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break;
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case B_IMM_S:
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snprintf(buf, buflen, "%s %s, 0x%lx", pi->name, rs, b_target(pc, insn));
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break;
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case B_IMM_TS:
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snprintf(buf, buflen, "%s %s, %s, 0x%lx", pi->name, rs, rt, b_target(pc, insn));
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break;
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case J_IMM:
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snprintf(buf, buflen, "%s 0x%lx", pi->name, j_target(pc, insn));
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break;
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case A_IMM_TS:
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if (abs(imm) < 1000)
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snprintf(buf, buflen, "%s %s, %s, %d", pi->name, rt, rs, imm);
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else
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snprintf(buf, buflen, "%s %s, %s, 0x%x", pi->name, rt, rs, imm);
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break;
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case L_IMM_T:
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snprintf(buf, buflen, "%s %s, 0x%x", pi->name, rt, (uint16_t)imm);
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break;
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case L_IMM_TS:
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if ((insn >> 26) == 0x34 /*ORI*/ && (insn & 0x03e00000) == 0 /*zero*/)
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snprintf(buf, buflen, "li %s, 0x%x", rt, (uint16_t)imm);
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else
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snprintf(buf, buflen, "%s %s, %s, 0x%x", pi->name, rt, rs, (uint16_t)imm);
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break;
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case M_IMM_TS:
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snprintf(buf, buflen, "%s %s, %d(%s)", pi->name, rt, imm, rs);
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break;
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}
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return 1;
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}
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6
platform/common/dismips.h
Normal file
6
platform/common/dismips.h
Normal file
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@ -0,0 +1,6 @@
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#ifndef DISMIPS_H
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#define DISMIPS_H
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int dismips(uintptr_t pc, uint32_t insn, char *buf, unsigned int buf_len);
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#endif /* DISMIPS_H */
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@ -29,7 +29,7 @@ void pemu_prep_defconfig(void)
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void pemu_validate_config(void)
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{
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#if !defined(__arm__) && !defined(__i386__) && !defined(__x86_64__)
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#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__i386__) && !defined(__x86_64__)
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PicoIn.opt &= ~POPT_EN_DRC;
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#endif
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}
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