mirror of
https://github.com/RaySollium99/picodrive.git
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sh2 drc: add mipsel backend for MIPS32 Release 1 (for JZ47xx)
This commit is contained in:
kub
parent
1747b6712d
commit
d80a5fd2ab
13 changed files with 1922 additions and 23 deletions
5
Makefile
5
Makefile
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@ -55,6 +55,9 @@ use_cz80 ?= 1
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ifneq (,$(findstring 86,$(ARCH)))
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use_sh2drc ?= 1
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endif
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ifneq (,$(findstring mips,$(ARCH)))
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use_sh2drc ?= 1
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endif
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endif
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-include Makefile.local
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@ -245,7 +248,7 @@ pico/carthw_cfg.c: pico/carthw.cfg
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# random deps
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pico/carthw/svp/compiler.o : cpu/drc/emit_arm.c
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cpu/sh2/compiler.o : cpu/drc/emit_arm.c
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cpu/sh2/compiler.o : cpu/drc/emit_x86.c
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cpu/sh2/compiler.o : cpu/drc/emit_x86.c cpu/drc/emit_mips.c
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cpu/sh2/mame/sh2pico.o : cpu/sh2/mame/sh2.c
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pico/pico.o pico/cd/mcd.o pico/32x/32x.o : pico/pico_cmn.c pico/pico_int.h
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pico/memory.o pico/cd/memory.o pico/32x/memory.o : pico/pico_int.h pico/memory.h
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16
config.gcw0
Normal file
16
config.gcw0
Normal file
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@ -0,0 +1,16 @@
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# Automatically generated by configure
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# Configured with: './configure' '--platform=generic'
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CC = mipsel-gcw0-linux-uclibc-gcc
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CXX = mipsel-gcw0-linux-uclibc-g++
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AS = mipsel-gcw0-linux-uclibc-as
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STRIP = mipsel-gcw0-linux-uclibc-strip
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CFLAGS += -I${HOME}/opt/gcw0-toolchain/usr/mipsel-gcw0-linux-uclibc/sysroot/usr/include/
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CFLAGS += -I${HOME}/opt/gcw0-toolchain/usr/mipsel-gcw0-linux-uclibc/sysroot/usr/include/SDL
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CFLAGS += -D_GNU_SOURCE=1 -D_REENTRANT -Wno-unused-result -fno-stack-protector
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ASFLAGS +=
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LDFLAGS +=
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LDLIBS += -B${HOME}/opt/gcw0-toolchain/usr/lib -Wl,-rpath-link=${HOME}/opt/gcw0-toolchain/usr/mipsel-gcw0-linux-uclibc/sysroot/usr/lib -Wl,-rpath-link=${HOME}/opt/gcw0-toolchain/usr/mipsel-gcw0-linux-uclibc/sysroot/lib -lSDL -lasound -lpng -lz -lm -lstdc++ -ldl
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ARCH = mipsel
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PLATFORM = opendingux
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SOUND_DRIVERS = sdl
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@ -1098,11 +1098,14 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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#define emith_jump_cond_patchable(cond, target) \
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emith_jump_cond(cond, target)
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#define emith_jump_patch(ptr, target) do { \
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#define emith_jump_patch(ptr, target) ({ \
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u32 *ptr_ = ptr; \
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u32 val_ = (u32 *)(target) - ptr_ - 2; \
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*ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
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} while (0)
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(u8 *)ptr; \
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})
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#define emith_jump_patch_size() 4
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#define emith_jump_at(ptr, target) do { \
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u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
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1464
cpu/drc/emit_mips.c
Normal file
1464
cpu/drc/emit_mips.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -869,11 +869,14 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#define emith_jump_cond_patchable(cond, target) \
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emith_jump_cond(cond, target)
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#define emith_jump_patch(ptr, target) do { \
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#define emith_jump_patch(ptr, target) ({ \
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u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 4); \
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u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
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EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
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} while (0)
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ptr; \
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})
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#define emith_jump_patch_size() 6
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#define emith_jump_at(ptr, target) do { \
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u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 5); \
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@ -466,6 +466,47 @@ static cache_reg_t cache_regs[] = {
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{ 7, HRF_REG },
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};
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#elif defined(__mips__)
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#include "../drc/emit_mips.c"
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static guest_reg_t guest_regs[] = {
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// SHR_R0 .. SHR_SP
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{GRF_STATIC, 20} , {GRF_STATIC, 21} , { 0 } , { 0 } ,
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{ 0 } , { 0 } , { 0 } , { 0 } ,
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{ 0 } , { 0 } , { 0 } , { 0 } ,
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{ 0 } , { 0 } , { 0 } , { 0 } ,
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// SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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// SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
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{ 0 } , { 0 } , { 0 } , {GRF_STATIC, 22} ,
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{ 0 } , { 0 } , { 0 } , { 0 } ,
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};
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// MIPS ABI: params: r4-r7, return: r2-r3, temp: r1(at),r8-r15,r24-r25,r31(ra),
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// saved: r16-r23,r30, reserved: r0(zero), r26-r27(irq), r28(gp), r29(sp)
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// r1,r15,r24,r25 are used internally by the code emitter
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static cache_reg_t cache_regs[] = {
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{ 14, HRF_TEMP }, // temps
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{ 13, HRF_TEMP },
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{ 12, HRF_TEMP },
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{ 11, HRF_TEMP },
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{ 10, HRF_TEMP },
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{ 9, HRF_TEMP },
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{ 8, HRF_TEMP },
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{ 7, HRF_TEMP }, // params
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{ 6, HRF_TEMP },
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{ 5, HRF_TEMP },
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{ 4, HRF_TEMP },
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{ 3, HRF_TEMP }, // RET_REG
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{ 2, HRF_TEMP },
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{ 22, HRF_LOCKED }, // statics
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{ 21, HRF_LOCKED },
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{ 20, HRF_LOCKED },
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{ 19, HRF_REG }, // other regs
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{ 18, HRF_REG },
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{ 17, HRF_REG },
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{ 16, HRF_REG },
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};
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#elif defined(__i386__)
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#include "../drc/emit_x86.c"
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@ -1050,9 +1091,12 @@ static void dr_block_link(struct block_entry *be, struct block_link *bl, int emi
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dbg(2, "- %slink from %p to pc %08x entry %p", emit_jump ? "":"early ",
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bl->jump, bl->target_pc, be->tcache_ptr);
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if (emit_jump)
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emith_jump_patch(bl->jump, be->tcache_ptr);
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// could sync arm caches here, but that's unnecessary
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if (emit_jump) {
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u8 *jump = emith_jump_patch(bl->jump, be->tcache_ptr);
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// only needs sync if patch is possibly crossing cacheline (assume 16 byte)
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if ((uintptr_t)jump >>4 != ((uintptr_t)jump+emith_jump_patch_size()-1) >>4)
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host_instructions_updated(jump, jump+emith_jump_patch_size());
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}
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// move bl to block_entry
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bl->target = be;
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@ -1069,9 +1113,9 @@ static void dr_block_unlink(struct block_link *bl, int emit_jump)
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if (bl->target) {
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if (emit_jump) {
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emith_jump_patch(bl->jump, sh2_drc_dispatcher);
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u8 *jump = emith_jump_patch(bl->jump, sh2_drc_dispatcher);
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// update cpu caches since the previous jump target doesn't exist anymore
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host_instructions_updated(bl->jump, bl->jump+4);
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host_instructions_updated(jump, jump+emith_jump_patch_size());
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}
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if (bl->prev)
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@ -4128,8 +4172,9 @@ end_op:
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struct op_data *opd_b = (op_flags[i] & OF_DELAY_OP) ? opd-1 : opd;
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u32 target_pc = opd_b->imm;
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int cond = -1;
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void *target = NULL;
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int ctaken = 0;
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void *target = NULL;
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int patchable = 0;
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if (OP_ISBRACND(opd_b->op))
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ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
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@ -4182,11 +4227,12 @@ end_op:
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branch_patch_pc[branch_patch_count] = target_pc;
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branch_patch_ptr[branch_patch_count] = target;
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branch_patch_count++;
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}
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else
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patchable = 1;
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} else
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dbg(1, "warning: too many local branches");
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}
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#endif
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if (target == NULL)
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{
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// can't resolve branch locally, make a block exit
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@ -4204,15 +4250,25 @@ end_op:
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} else
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#endif
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target = dr_prepare_ext_branch(block->entryp, target_pc, sh2->is_slave, tcache_id);
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patchable = 1;
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}
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if (cond != -1) {
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// create branch
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if (patchable) {
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if (cond != -1)
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emith_jump_cond_patchable(cond, target);
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}
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else if (target != NULL) {
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rcache_invalidate();
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emith_jump_patchable(target);
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}
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} else {
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if (cond != -1)
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emith_jump_cond(cond, target);
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else if (target != NULL) {
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rcache_invalidate();
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emith_jump(target);
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}
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}
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// branch not taken, correct cycle count
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if (ctaken)
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@ -36,6 +36,8 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
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// XXX MUST match definitions in cpu/sh2/compiler.c
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#if defined(__arm__)
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#define DRC_SR_REG r10
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#elif defined(__mips__)
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#define DRC_SR_REG s6
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#elif defined(__i386__)
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#define DRC_SR_REG edi
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#elif defined(__x86_64__)
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@ -169,7 +169,7 @@ DEFINES += DRC_DEBUG=$(drc_debug)
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SRCS_COMMON += $(R)cpu/sh2/mame/sh2dasm.c
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DASM = $(R)platform/libpicofe/linux/host_dasm.c
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DASMLIBS = -lbfd -lopcodes -liberty
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ifeq "$(ARCH)" "arm"
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ifeq ("$(ARCH)",$(filter "$(ARCH)","arm" "mipsel"))
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ifeq ($(filter_out $(shell $(CC) --print-file-name=libbfd.so),"/"),)
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DASM = $(R)platform/common/host_dasm.c
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DASMLIBS =
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@ -435,7 +435,7 @@ static int software_interrupt(unsigned int pc, unsigned int insn, char *buf, siz
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return 1;
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}
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int disarm(unsigned int pc, unsigned int insn, char *buf, size_t buf_len)
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int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len)
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{
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if ((insn & 0x0fffffd0) == 0x012fff10)
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return branch_and_exchange(pc, insn, buf, buf_len);
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@ -23,6 +23,6 @@
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#ifndef DISARM_H
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#define DISARM_H
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int disarm(unsigned int pc, unsigned int insn, char *buf, unsigned int buf_len);
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int disarm(uintptr_t long pc, uint32_t, char *buf, unsigned int buf_len);
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#endif /* DISARM_H */
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346
platform/common/dismips.c
Normal file
346
platform/common/dismips.c
Normal file
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@ -0,0 +1,346 @@
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/*
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* very basic mips disassembler for MIPS32/MIPS64 Release 1, only for picodrive
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* Copyright (C) 2019 kub
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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// XXX unimplemented: SYSCALL, BREAK, SYNC, SDBBP, T*, CACHE, PREF,
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// MOVF/MOVT, LWC*/LDC*, SWC*/SDC*, COP*.
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// however, it's certainly good enough for anything picodrive DRC throws at it.
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "dismips.h"
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static char *const register_names[32] = {
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"$zero",
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"$at",
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"$v0",
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"$v1",
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"$a0",
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"$a1",
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"$a2",
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"$a3",
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"$t0",
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"$t1",
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"$t2",
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"$t3",
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"$t4",
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"$t5",
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"$t6",
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"$t7",
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"$s0",
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"$s1",
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"$s2",
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"$s3",
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"$s4",
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"$s5",
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"$s6",
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"$s7",
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"$t8",
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"$t9",
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"$k0",
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"$k1",
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"$gp",
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"$sp",
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"$fp",
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"$ra"
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};
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enum insn_type {
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REG_DTS, REG_TS, // 3, 2, or 1 regs
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REG_DS, REG_D, REG_S,
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S_IMM_DT, // 2 regs with shift amount
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B_IMM_S, B_IMM_TS, // pc-relative branches with 1 or 2 regs
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J_IMM, // region-relative jump
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A_IMM_TS, // arithmetic immediate with 1 or 2 regs
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L_IMM_T, L_IMM_TS, // logical immediate with 2 regs
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M_IMM_TS, // memory indexed with 2 regs
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};
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struct insn {
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unsigned char op;
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enum insn_type type;
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char *name;
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};
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// ATTN: these array MUST be sorted by op (decode relies on it)
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// instructions with opcode SPECIAL (R-type)
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#define OP_SPECIAL 0x00
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static const struct insn special_insns[] = {
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{0x00, S_IMM_DT, "sll"},
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{0x02, S_IMM_DT, "srl"},
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{0x03, S_IMM_DT, "sra"},
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{0x04, REG_DTS, "sllv"},
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{0x06, REG_DTS, "srlv"},
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{0x07, REG_DTS, "srav"},
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{0x08, REG_S, "jr"},
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{0x09, REG_DS, "jalr"},
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{0x0a, REG_DTS, "movz"},
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{0x0b, REG_DTS, "movn"},
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// {0x0c, , "syscall"},
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// {0x0d, , "break"},
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// {0x0f, , "sync"},
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{0x10, REG_D, "mfhi"},
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{0x11, REG_S, "mthi"},
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{0x12, REG_D, "mflo"},
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{0x13, REG_S, "mtlo"},
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{0x14, REG_DTS, "dsllv"},
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{0x16, REG_DTS, "dslrv"},
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{0x17, REG_DTS, "dsrav"},
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{0x18, REG_TS, "mult"},
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{0x19, REG_TS, "multu"},
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{0x1A, REG_TS, "div"},
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{0x1B, REG_TS, "divu"},
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{0x1C, REG_TS, "dmult"},
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{0x1D, REG_TS, "dmultu"},
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{0x1E, REG_TS, "ddiv"},
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{0x1F, REG_TS, "ddivu"},
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{0x20, REG_DTS, "add"},
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{0x21, REG_DTS, "addu"},
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{0x22, REG_DTS, "sub"},
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{0x23, REG_DTS, "subu"},
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{0x24, REG_DTS, "and"},
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{0x25, REG_DTS, "or"},
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{0x26, REG_DTS, "xor"},
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{0x27, REG_DTS, "nor"},
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{0x2A, REG_DTS, "slt"},
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{0x2B, REG_DTS, "sltu"},
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{0x2C, REG_DTS, "dadd"},
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{0x2D, REG_DTS, "daddu"},
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{0x2E, REG_DTS, "dsub"},
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{0x2F, REG_DTS, "dsubu"},
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// {0x30, REG_TS, "tge" },
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// {0x31, REG_TS, "tgeu" },
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// {0x32, REG_TS, "tlt" },
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// {0x33, REG_TS, "tltu" },
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// {0x34, REG_TS, "teq" },
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// {0x36, REG_TS, "tne" },
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{0x38, S_IMM_DT, "dsll"},
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{0x3A, S_IMM_DT, "dsrl"},
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{0x3B, S_IMM_DT, "dsra"},
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{0x3D, S_IMM_DT, "dsll32"},
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{0x3E, S_IMM_DT, "dsrl32"},
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{0x3F, S_IMM_DT, "dsra32"},
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};
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// instructions with opcode SPECIAL2 (R-type)
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#define OP_SPECIAL2 0x1C
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static const struct insn special2_insns[] = {
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{0x00, REG_TS, "madd" },
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{0x01, REG_TS, "maddu" },
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{0x02, REG_TS, "mul" },
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{0x04, REG_TS, "msub" },
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{0x05, REG_TS, "msubu" },
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{0x20, REG_DS, "clz" },
|
||||
{0x21, REG_DS, "clo" },
|
||||
{0x24, REG_DS, "dclz" },
|
||||
{0x25, REG_DS, "dclo" },
|
||||
};
|
||||
|
||||
// instructions with opcode REGIMM (I-type)
|
||||
#define OP_REGIMM 0x01
|
||||
static const struct insn regimm_insns[] = {
|
||||
{0x00, B_IMM_S, "bltz"},
|
||||
{0x01, B_IMM_S, "bgez"},
|
||||
{0x02, B_IMM_S, "bltzl"},
|
||||
{0x03, B_IMM_S, "bgezl"},
|
||||
// {0x08, , "tgei"},
|
||||
// {0x09, , "tgeiu"},
|
||||
// {0x0a, , "tlti"},
|
||||
// {0x0b, , "tltiu"},
|
||||
// {0x0c, , "teqi"},
|
||||
// {0x0e, , "tnei"},
|
||||
{0x10, B_IMM_S, "bltzal"},
|
||||
{0x11, B_IMM_S, "bgezal"},
|
||||
{0x12, B_IMM_S, "bltzall"},
|
||||
{0x13, B_IMM_S, "bgezall"},
|
||||
{0x13, B_IMM_S, "bgezall"},
|
||||
};
|
||||
|
||||
// instructions with other opcodes (I-type)
|
||||
static const struct insn immediate_insns[] = {
|
||||
{0x02, J_IMM, "j"},
|
||||
{0x03, J_IMM, "jal"},
|
||||
{0x04, B_IMM_TS, "beq"},
|
||||
{0x05, B_IMM_TS, "bne"},
|
||||
{0x06, B_IMM_S, "blez"},
|
||||
{0x07, B_IMM_S, "bgtz"},
|
||||
{0x08, A_IMM_TS, "addi"},
|
||||
{0x09, A_IMM_TS, "addiu"},
|
||||
{0x0A, A_IMM_TS, "slti"},
|
||||
{0x0B, A_IMM_TS, "sltiu"},
|
||||
{0x0C, L_IMM_TS, "andi"},
|
||||
{0x0D, L_IMM_TS, "ori"},
|
||||
{0x0E, L_IMM_TS, "xori"},
|
||||
{0x0F, L_IMM_T, "lui"},
|
||||
{0x14, B_IMM_TS, "beql"},
|
||||
{0x15, B_IMM_TS, "bnel"},
|
||||
{0x16, B_IMM_S, "blezl"},
|
||||
{0x17, B_IMM_S, "bgtzl"},
|
||||
{0x18, A_IMM_TS, "daddi"},
|
||||
{0x19, A_IMM_TS, "daddiu"},
|
||||
{0x1A, M_IMM_TS, "ldl"},
|
||||
{0x1B, M_IMM_TS, "ldr"},
|
||||
{0x20, M_IMM_TS, "lb"},
|
||||
{0x21, M_IMM_TS, "lh"},
|
||||
{0x22, M_IMM_TS, "lwl"},
|
||||
{0x23, M_IMM_TS, "lw"},
|
||||
{0x24, M_IMM_TS, "lbu"},
|
||||
{0x25, M_IMM_TS, "lhu"},
|
||||
{0x26, M_IMM_TS, "lwr"},
|
||||
{0x27, M_IMM_TS, "lwu"},
|
||||
{0x28, M_IMM_TS, "sb"},
|
||||
{0x29, M_IMM_TS, "sh"},
|
||||
{0x2A, M_IMM_TS, "swl"},
|
||||
{0x2B, M_IMM_TS, "sw"},
|
||||
{0x2C, M_IMM_TS, "sdl"},
|
||||
{0x2D, M_IMM_TS, "sdr"},
|
||||
{0x2E, M_IMM_TS, "swr"},
|
||||
// {0x2F, , "cache"},
|
||||
{0x30, M_IMM_TS, "ll"},
|
||||
// {0x31, , "lwc1"},
|
||||
// {0x32, , "lwc2"},
|
||||
// {0x33, , "pref"},
|
||||
{0x34, M_IMM_TS, "lld"},
|
||||
// {0x35, , "ldc1"},
|
||||
// {0x36, , "ldc2"},
|
||||
{0x37, M_IMM_TS, "ld"},
|
||||
{0x38, M_IMM_TS, "sc"},
|
||||
// {0x39, , "swc1"},
|
||||
// {0x3A, , "swc2"},
|
||||
{0x3C, M_IMM_TS, "scd"},
|
||||
// {0x3D, , "sdc1"},
|
||||
// {0x3E, , "sdc2"},
|
||||
{0x3F, M_IMM_TS, "sd"},
|
||||
};
|
||||
|
||||
#define ARRAY_SIZE(a) (sizeof(a)/sizeof(*a))
|
||||
|
||||
// find instruction description for insn
|
||||
static const struct insn *decode_insn(uint32_t insn)
|
||||
{
|
||||
uint32_t op = insn >> 26;
|
||||
const struct insn *pi;
|
||||
int l = 0, r = 0;
|
||||
|
||||
if (op == OP_SPECIAL) {
|
||||
op = insn & 0x3f;
|
||||
pi = special_insns;
|
||||
r = ARRAY_SIZE(special_insns)-1;
|
||||
} else if (op == OP_SPECIAL2) {
|
||||
op = insn & 0x3f;
|
||||
pi = special2_insns;
|
||||
r = ARRAY_SIZE(special2_insns)-1;
|
||||
} else if (op == OP_REGIMM) {
|
||||
op = (insn>>16) & 0x1f;
|
||||
pi = regimm_insns;
|
||||
r = ARRAY_SIZE(regimm_insns)-1;
|
||||
} else {
|
||||
pi = immediate_insns;
|
||||
r = ARRAY_SIZE(immediate_insns)-1;
|
||||
}
|
||||
|
||||
while (l <= r) {
|
||||
int m = (l+r) / 2;
|
||||
if (pi[m].op == op)
|
||||
return pi+m;
|
||||
else if (pi[m].op < op)
|
||||
l = m+1;
|
||||
else
|
||||
r = m-1;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
// calculate target for pc-relative branches
|
||||
static unsigned long b_target(unsigned long pc, uint32_t insn)
|
||||
{
|
||||
return pc + 4 + (int16_t)insn * 4;
|
||||
}
|
||||
|
||||
// calculate target for region-relative branches
|
||||
static unsigned long j_target(unsigned long pc, uint32_t insn)
|
||||
{
|
||||
return (pc & ~0x0fffffffL) | ((insn & 0x03ffffff) << 2);
|
||||
}
|
||||
|
||||
// main disassembler function
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, unsigned int buflen)
|
||||
{
|
||||
const struct insn *pi = decode_insn(insn);
|
||||
char *rs = register_names[(insn >> 21) & 0x1f];
|
||||
char *rt = register_names[(insn >> 16) & 0x1f];
|
||||
char *rd = register_names[(insn >> 11) & 0x1f];
|
||||
int sa = (insn >> 6) & 0x1f;
|
||||
int imm = (int16_t) insn;
|
||||
|
||||
if (pi == NULL) {
|
||||
snprintf(buf, buflen, "0x%x", insn);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (pi->type) {
|
||||
case REG_DTS:
|
||||
if ((insn & 0x3f) == 0x25 /*OR*/ && (insn & 0x1f0000) == 0 /*zero*/)
|
||||
snprintf(buf, buflen, "move %s, %s", rd, rs);
|
||||
else
|
||||
snprintf(buf, buflen, "%s %s, %s, %s", pi->name, rd, rs, rt);
|
||||
break;
|
||||
case REG_TS:
|
||||
snprintf(buf, buflen, "%s %s, %s", pi->name, rs, rt);
|
||||
break;
|
||||
case REG_DS:
|
||||
snprintf(buf, buflen, "%s %s, %s", pi->name, rd, rs);
|
||||
break;
|
||||
case REG_D:
|
||||
snprintf(buf, buflen, "%s %s", pi->name, rd);
|
||||
break;
|
||||
case REG_S:
|
||||
snprintf(buf, buflen, "%s %s", pi->name, rs);
|
||||
break;
|
||||
case S_IMM_DT:
|
||||
if (insn == 0x00000000)
|
||||
snprintf(buf, buflen, "nop");
|
||||
else
|
||||
snprintf(buf, buflen, "%s %s, %s, %d", pi->name, rd, rt, sa);
|
||||
break;
|
||||
case B_IMM_S:
|
||||
snprintf(buf, buflen, "%s %s, 0x%lx", pi->name, rs, b_target(pc, insn));
|
||||
break;
|
||||
case B_IMM_TS:
|
||||
snprintf(buf, buflen, "%s %s, %s, 0x%lx", pi->name, rs, rt, b_target(pc, insn));
|
||||
break;
|
||||
case J_IMM:
|
||||
snprintf(buf, buflen, "%s 0x%lx", pi->name, j_target(pc, insn));
|
||||
break;
|
||||
case A_IMM_TS:
|
||||
if (abs(imm) < 1000)
|
||||
snprintf(buf, buflen, "%s %s, %s, %d", pi->name, rt, rs, imm);
|
||||
else
|
||||
snprintf(buf, buflen, "%s %s, %s, 0x%x", pi->name, rt, rs, imm);
|
||||
break;
|
||||
case L_IMM_T:
|
||||
snprintf(buf, buflen, "%s %s, 0x%x", pi->name, rt, (uint16_t)imm);
|
||||
break;
|
||||
case L_IMM_TS:
|
||||
if ((insn >> 26) == 0x34 /*ORI*/ && (insn & 0x03e00000) == 0 /*zero*/)
|
||||
snprintf(buf, buflen, "li %s, 0x%x", rt, (uint16_t)imm);
|
||||
else
|
||||
snprintf(buf, buflen, "%s %s, %s, 0x%x", pi->name, rt, rs, (uint16_t)imm);
|
||||
break;
|
||||
case M_IMM_TS:
|
||||
snprintf(buf, buflen, "%s %s, %d(%s)", pi->name, rt, imm, rs);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
6
platform/common/dismips.h
Normal file
6
platform/common/dismips.h
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef DISMIPS_H
|
||||
#define DISMIPS_H
|
||||
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, unsigned int buf_len);
|
||||
|
||||
#endif /* DISMIPS_H */
|
||||
|
|
@ -29,7 +29,7 @@ void pemu_prep_defconfig(void)
|
|||
|
||||
void pemu_validate_config(void)
|
||||
{
|
||||
#if !defined(__arm__) && !defined(__i386__) && !defined(__x86_64__)
|
||||
#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__i386__) && !defined(__x86_64__)
|
||||
PicoIn.opt &= ~POPT_EN_DRC;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue