vdp, fix for 68k access timing

This commit is contained in:
kub 2020-12-12 17:29:31 +01:00
parent 1613ec6c30
commit dda72beae4
3 changed files with 47 additions and 35 deletions

View file

@ -54,6 +54,10 @@ const unsigned char hcounts_32[] = {
// In blanked display, all slots but 5(h32) / 6(h40) are usable for transfers,
// in active display only 16(h32) / 18(h40) slots can be used.
// NB the cyc2sl tables should cover 2 slot into the next scanline, in case the
// last insn in the old scanline is a 32 bit VDP access. That is currently not
// the case for active display.
// XXX inactive tables by slot#=cycles*maxslot#/488. should be through hv tables
// VDP transfer slots in inactive (blanked) display 32col mode.
// refresh slots: 250, 26, 58, 90, 122 -> 32, 64, 96, 128, 160
@ -140,42 +144,45 @@ const unsigned char vdpcyc2sl_40[] = { // 68k cycles/2 to slot #
18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, // 480
};
// NB the sl2cyc tables must cover all slots present in the cyc2sl tables.
// XXX inactive tables by cyc=slot#*488/maxslot#. should be through hv tables
const unsigned short vdpsl2cyc_32_bl[] = { // slot # to 68k cycles/2
0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23,
24, 25, 27, 28, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 45, 46,
48, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70,
71, 73, 74, 75, 77, 78, 80, 81, 83, 84, 86, 87, 89, 90, 92, 93,
95, 96, 98, 99,100,102,103,105,106,108,109,111,112,114,115,117,
118,120,121,122,124,125,127,128,130,131,133,134,136,137,139,140,
142,143,145,146,147,149,150,152,153,155,156,158,159,161,162,164,
165,167,168,170,171,172,174,175,177,178,180,181,183,184,186,187,
189,190,192,193,195,196,197,199,200,202,203,205,206,208,209,211,
212,214,215,217,218,220,221,222,224,225,227,228,230,231,233,234,
236,237,239,240,242,243,244,246,
0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23,
24, 25, 27, 28, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 45, 46,
48, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70,
71, 73, 74, 75, 77, 78, 80, 81, 83, 84, 86, 87, 89, 90, 92, 93,
95, 96, 98, 99,100,102,103,105,106,108,109,111,112,114,115,117,
118,120,121,122,124,125,127,128,130,131,133,134,136,137,139,140,
142,143,145,146,147,149,150,152,153,155,156,158,159,161,162,164,
165,167,168,170,171,172,174,175,177,178,180,181,183,184,186,187,
189,190,192,193,195,196,197,199,200,202,203,205,206,208,209,211,
212,214,215,217,218,220,221,222,224,225,227,228,230,231,233,234,
236,237,239,240,242,243,244,246,247,249,250,252,253,255,256
};
const unsigned short vdpsl2cyc_40_bl[] = { // slot # to 68k cycles/2
0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18,
20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 38,
39, 40, 41, 42, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 56, 57,
58, 59, 60, 61, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76,
77, 78, 79, 81, 82, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95,
96, 97, 99,100,101,102,103,105,106,107,108,109,111,112,113,114,
115,117,118,119,120,121,122,124,125,126,127,128,130,131,132,133,
134,136,137,138,139,140,142,143,144,145,146,148,149,150,151,152,
154,155,156,157,158,160,161,162,163,164,166,167,168,169,170,172,
173,174,175,176,178,179,180,181,182,183,185,186,187,188,189,191,
192,193,194,195,197,198,199,200,201,203,204,205,206,207,209,210,
211,212,213,215,216,217,218,219,221,222,223,224,225,227,228,229,
230,231,233,234,235,236,237,239,240,241,242,243,244,246,
0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18,
20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 38,
39, 40, 41, 42, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 56, 57,
58, 59, 60, 61, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76,
77, 78, 79, 81, 82, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95,
96, 97, 99,100,101,102,103,105,106,107,108,109,111,112,113,114,
115,117,118,119,120,121,122,124,125,126,127,128,130,131,132,133,
134,136,137,138,139,140,142,143,144,145,146,148,149,150,151,152,
154,155,156,157,158,160,161,162,163,164,166,167,168,169,170,172,
173,174,175,176,178,179,180,181,182,183,185,186,187,188,189,191,
192,193,194,195,197,198,199,200,201,203,204,205,206,207,209,210,
211,212,213,215,216,217,218,219,221,222,223,224,225,227,228,229,
230,231,233,234,235,236,237,239,240,241,242,243,244,246,247,248,
249,250,252,253,254,255,257
};
const unsigned short vdpsl2cyc_32[] = { // slot # to 68k cycles/2
0, 16, 36, 56, 67, 79,102,113,125,148,159,171,194,205,217,239,
240,260
240,260,280
};
const unsigned short vdpsl2cyc_40[] = { // slot # to 68k cycles/2
0, 24, 55, 64, 73, 92,101,110,129,138,147,166,175,184,203,212,
221,239,240,268
221,239,240,268,299
};
#ifndef _ASM_MISC_C