mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-06 07:38:05 -04:00
32x: implement dreq1, improve dmac
This commit is contained in:
notaz
parent
a7f82a776a
commit
df63f1a6ff
4 changed files with 314 additions and 94 deletions
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@ -172,42 +172,210 @@ static u32 sh2_comm_faker(u32 a)
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#endif
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// DMAC handling
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static struct {
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unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
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unsigned int chcr0; // chan ctl
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unsigned int sar1, dar1, tcr1; // same for chan 1
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unsigned int chcr1;
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int pad[4];
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unsigned int dmaor;
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} * dmac0;
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struct dma_chan {
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unsigned int sar, dar; // src, dst addr
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unsigned int tcr; // transfer count
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unsigned int chcr; // chan ctl
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// -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
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// ts - transfer size: 1, 2, 4, 16 bytes
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// ar - auto request if 1, else dreq signal
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// ie - irq enable
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// te - transfer end
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// de - dma enable
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#define DMA_AR (1 << 9)
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#define DMA_IE (1 << 2)
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#define DMA_TE (1 << 1)
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#define DMA_DE (1 << 0)
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};
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static void dma_68k2sh2_do(void)
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struct dmac {
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struct dma_chan chan[2];
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unsigned int vcrdma0;
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unsigned int unknown0;
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unsigned int vcrdma1;
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unsigned int unknown1;
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unsigned int dmaor;
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// -- pr ae nmif dme
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// pr - priority: chan0 > chan1 or round-robin
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// ae - address error
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// nmif - nmi occurred
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// dme - DMA master enable
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#define DMA_DME (1 << 0)
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};
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static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
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{
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char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
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struct dmac *dmac = (void *)(regs + 0x180);
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int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
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int vector = (chan == &dmac->chan[0]) ?
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dmac->vcrdma0 : dmac->vcrdma1;
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elprintf(EL_32X, "dmac irq %d %d", level, vector);
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sh2_internal_irq(sh2, level, vector & 0x7f);
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}
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static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
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{
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chan->chcr |= DMA_TE; // DMA has ended normally
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p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
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if (chan->chcr & DMA_IE)
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dmac_te_irq(sh2, chan);
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}
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static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
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{
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u32 size, d;
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size = (chan->chcr >> 10) & 3;
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switch (size) {
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case 0:
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d = p32x_sh2_read8(chan->sar, sh2);
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p32x_sh2_write8(chan->dar, d, sh2);
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case 1:
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d = p32x_sh2_read16(chan->sar, sh2);
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p32x_sh2_write16(chan->dar, d, sh2);
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break;
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case 2:
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d = p32x_sh2_read32(chan->sar, sh2);
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p32x_sh2_write32(chan->dar, d, sh2);
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break;
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case 3:
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elprintf(EL_32X|EL_ANOMALY, "TODO: 16byte DMA");
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chan->sar += 16; // always?
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chan->tcr -= 4;
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return;
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}
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chan->tcr--;
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size = 1 << size;
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if (chan->chcr & (1 << 15))
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chan->dar -= size;
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if (chan->chcr & (1 << 14))
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chan->dar += size;
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if (chan->chcr & (1 << 13))
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chan->sar -= size;
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if (chan->chcr & (1 << 12))
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chan->sar += size;
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}
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static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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{
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unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
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int i;
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if (dmac0->tcr0 != *dreqlen)
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elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
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// debug/sanity checks
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if (chan->tcr != *dreqlen)
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elprintf(EL_32X|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
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chan->tcr, *dreqlen);
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// note: DACK is not connected, single addr mode should not be used
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if ((chan->chcr & 0x3f08) != 0x0400)
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elprintf(EL_32X|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
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if (chan->sar != 0x20004012)
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elprintf(EL_32X|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
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// HACK: assume bus is busy and SH2 is halted
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msh2.state |= SH2_STATE_SLEEP;
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sh2->state |= SH2_STATE_SLEEP;
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for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
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elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
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p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
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dmac0->dar0 += 2;
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dmac0->tcr0--;
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for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
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elprintf(EL_32X, "dmaw [%08x] %04x, left %d",
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chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
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p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
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chan->dar += 2;
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chan->tcr--;
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(*dreqlen)--;
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}
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Pico32x.dmac_ptr = 0; // HACK
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if (Pico32x.dmac0_fifo_ptr != i)
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memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
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(Pico32x.dmac0_fifo_ptr - i) * 2);
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Pico32x.dmac0_fifo_ptr -= i;
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Pico32x.regs[6 / 2] &= ~P32XS_FULL;
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if (*dreqlen == 0)
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Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
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if (dmac0->tcr0 == 0) {
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dmac0->chcr0 |= 2; // DMA has ended normally
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_SLEEP, SekCyclesDoneT());
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if (chan->tcr == 0)
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dmac_transfer_complete(sh2, chan);
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else
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sh2_end_run(sh2, 16);
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}
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static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
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{
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// debug/sanity checks
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if ((chan->chcr & 0xc308) != 0x0000)
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elprintf(EL_32X|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
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if ((chan->dar & ~0xf) != 0x20004030)
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elprintf(EL_32X|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
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dmac_transfer_one(sh2, chan);
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if (chan->tcr == 0)
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dmac_transfer_complete(sh2, chan);
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}
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static void dreq0_trigger(void)
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{
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struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
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struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
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elprintf(EL_32X, "dreq0_trigger\n");
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if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
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dreq0_do(&msh2, &mdmac->chan[0]);
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}
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if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
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dreq0_do(&ssh2, &sdmac->chan[0]);
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}
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}
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void p32x_dreq1_trigger(void)
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{
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struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
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struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
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int hit = 0;
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elprintf(EL_32X, "dreq1_trigger\n");
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if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
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dreq1_do(&msh2, &mdmac->chan[1]);
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hit = 1;
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}
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if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
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dreq1_do(&ssh2, &sdmac->chan[1]);
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hit = 1;
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}
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if (!hit)
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elprintf(EL_32X|EL_ANOMALY, "dreq1: nobody cared");
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}
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// DMA trigger by SH2 register write
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static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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{
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elprintf(EL_32X, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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chan->tcr &= 0xffffff;
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if (chan->chcr & DMA_AR) {
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// auto-request transfer
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while ((int)chan->tcr > 0)
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dmac_transfer_one(sh2, chan);
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dmac_transfer_complete(sh2, chan);
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return;
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}
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// DREQ0 is only sent after first 4 words are written.
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// we do multiple of 4 words to avoid messing up alignment
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if (chan->sar == 0x20004012) {
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if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
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elprintf(EL_32X, "68k -> sh2 DMA");
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dreq0_trigger();
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}
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return;
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}
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elprintf(EL_32X|EL_ANOMALY, "unhandled DMA: "
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"%08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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}
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// ------------------------------------------------------------------
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@ -252,7 +420,7 @@ static u32 p32x_reg_read16(u32 a)
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}
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if ((a & 0x30) == 0x30)
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return p32x_pwm_read16(a, SekCyclesDoneT() * 3);
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return p32x_pwm_read16(a, SekCyclesDoneT());
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out:
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return Pico32x.regs[a / 2];
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@ -347,11 +515,11 @@ static void p32x_reg_write16(u32 a, u32 d)
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elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
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return;
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}
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if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
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Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
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if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
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dma_68k2sh2_do();
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if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
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if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
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Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
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if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
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dreq0_trigger();
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if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
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r[6 / 2] |= P32XS_FULL;
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}
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break;
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@ -385,7 +553,7 @@ static void p32x_reg_write16(u32 a, u32 d)
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}
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// PWM
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else if ((a & 0x30) == 0x30) {
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p32x_pwm_write16(a, d, SekCyclesDoneT() * 3);
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p32x_pwm_write16(a, d, SekCyclesDoneT());
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return;
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}
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@ -495,7 +663,7 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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return r[a / 2];
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}
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if ((a & 0x30) == 0x30) {
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return p32x_pwm_read16(a, sh2_cycles_done_t(&sh2s[cpuid]));
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return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
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}
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return 0;
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@ -571,7 +739,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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}
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// PWM
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else if ((a & 0x30) == 0x30) {
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p32x_pwm_write16(a, d, sh2_cycles_done_t(&sh2s[cpuid]));
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p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
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return;
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}
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@ -586,8 +754,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
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case 0x1c:
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Pico32x.sh2irqs &= ~P32XI_PWM;
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if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
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p32x_pwm_schedule_sh2(&sh2s[cpuid]);
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p32x_pwm_schedule_sh2(&sh2s[cpuid]);
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goto irls;
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}
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@ -721,20 +888,16 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
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break;
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}
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if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
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elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
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dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
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dmac0->tcr0 &= 0xffffff;
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// perhaps starting a DMA?
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if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
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struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
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if (!(dmac->dmaor & DMA_DME))
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return;
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// HACK: assume 68k starts writing soon and end the timeslice
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sh2_end_run(&sh2s[id], 16);
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// DREQ is only sent after first 4 words are written.
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// we do multiple of 4 words to avoid messing up alignment
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if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
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elprintf(EL_32X, "68k -> sh2 DMA");
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dma_68k2sh2_do();
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}
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if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
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dmac_trigger(&sh2s[id], &dmac->chan[0]);
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if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
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dmac_trigger(&sh2s[id], &dmac->chan[1]);
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}
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}
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@ -1542,8 +1705,6 @@ void PicoMemSetup32x(void)
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return;
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}
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dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
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get_bios();
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// cartridge area becomes unmapped
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