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32x: drc: inline dispatcher and irq handling; do write-caused irqs
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@849 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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10 changed files with 535 additions and 246 deletions
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@ -155,6 +155,10 @@
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#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
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EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
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#define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \
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EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
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((shift_imm)<<7) | ((shift_op)<<5) | (rm))
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/* addressing mode 3 */
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#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
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EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
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@ -165,12 +169,16 @@
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#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
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/* ldr and str */
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#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
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#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
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#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
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#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
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#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
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#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
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@ -192,8 +200,6 @@
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#define EOP_C_BX(cond,rm) \
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EMIT(((cond)<<28) | 0x012fff10 | (rm))
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#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
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#define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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@ -232,6 +238,7 @@
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#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
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// XXX: AND, RSB, *C, MVN will break if 1 insn is not enough
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static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
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{
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int ror2;
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@ -253,10 +260,9 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
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if (op == A_OP_MOV) {
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if (op == A_OP_MOV)
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op = A_OP_ORR;
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rn = rd;
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}
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rn = rd;
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}
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}
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@ -461,6 +467,12 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_and_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
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#define emith_add_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm)
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#define emith_sub_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
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#define emith_neg_r_r(d, s) \
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EOP_RSB_IMM(d, s, 0, 0)
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@ -583,18 +595,12 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_pass_arg_imm(arg, imm) \
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emith_move_r_imm(arg, imm)
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#define emith_call_cond(cond, target) \
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emith_xbranch(cond, target, 1)
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#define emith_jump(target) \
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emith_jump_cond(A_COND_AL, target)
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#define emith_jump_cond(cond, target) \
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emith_xbranch(cond, target, 0)
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#define emith_call(target) \
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emith_call_cond(A_COND_AL, target)
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#define emith_jump(target) \
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emith_jump_cond(A_COND_AL, target)
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#define emith_jump_patchable(cond) \
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emith_jump_cond(cond, 0)
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@ -604,8 +610,37 @@ static int emith_xbranch(int cond, void *target, int is_call)
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*ptr_ = (*ptr_ & 0xff000000) | (val & 0x00ffffff); \
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} while (0)
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#define emith_jump_reg_c(cond, r) \
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EOP_C_BX(cond, r)
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#define emith_jump_reg(r) \
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EOP_BX(r)
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emith_jump_reg_c(A_COND_AL, r)
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#define emith_jump_ctx_c(cond, offs) \
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EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs)
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#define emith_jump_ctx(offs) \
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emith_jump_ctx_c(A_COND_AL, offs)
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#define emith_call_cond(cond, target) \
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emith_xbranch(cond, target, 1)
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#define emith_call(target) \
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emith_call_cond(A_COND_AL, target)
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#define emith_call_ctx(offs) { \
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emith_move_r_r(14, 15); \
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emith_jump_ctx(offs); \
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}
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#define emith_ret_c(cond) \
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emith_jump_reg_c(cond, 14)
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#define emith_ret() \
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emith_ret_c(A_COND_AL)
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#define emith_ret_to_ctx(offs) \
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emith_ctx_write(14, offs)
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/* SH2 drc specific */
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#define emith_sh2_drc_entry() \
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@ -614,6 +649,18 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_sh2_drc_exit() \
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EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R15M)
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#define emith_sh2_wcall(a, tab, ret_ptr) { \
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int val_ = (char *)(ret_ptr) - (char *)tcache_ptr - 2*4; \
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if (val_ >= 0) \
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emith_add_r_r_imm(14, 15, val_); \
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else if (val_ < 0) \
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emith_sub_r_r_imm(14, 15, -val_); \
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emith_lsr(12, a, SH2_WRITE_SHIFT); \
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EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
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emith_ctx_read(2, offsetof(SH2, is_slave)); \
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emith_jump_reg(12); \
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}
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#define emith_sh2_dtbf_loop() { \
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int cr, rn; \
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int tmp_ = rcache_get_tmp(); \
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@ -239,7 +239,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_bic_r_imm(r, imm); \
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}
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#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
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#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
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#define emith_ret_c(cond) emith_ret()
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// _r_r_imm
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#define emith_add_r_r_imm(d, s, imm) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_add_r_imm(d, imm); \
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}
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#define emith_and_r_r_imm(d, s, imm) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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@ -279,6 +289,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_push(r) \
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EMIT_OP(0x50 + (r))
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#define emith_push_imm(imm) { \
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EMIT_OP(0x68); \
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EMIT(imm, u32); \
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}
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#define emith_pop(r) \
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EMIT_OP(0x58 + (r))
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@ -376,29 +391,41 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_rolcf emith_rolc
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#define emith_rorcf emith_rorc
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// XXX: offs is 8bit only
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#define emith_ctx_read(r, offs) do { \
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EMIT_OP_MODRM(0x8b, 1, r, xBP); \
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EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
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#define emith_ctx_op(op, r, offs) do { \
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/* mov r <-> [ebp+#offs] */ \
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if ((offs) >= 0x80) { \
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EMIT_OP_MODRM(op, 2, r, xBP); \
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EMIT(offs, u32); \
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} else { \
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EMIT_OP_MODRM(op, 1, r, xBP); \
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EMIT(offs, u8); \
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} \
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} while (0)
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#define emith_ctx_read(r, offs) \
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emith_ctx_op(0x8b, r, offs)
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#define emith_ctx_write(r, offs) \
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emith_ctx_op(0x89, r, offs)
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#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
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int r_ = r, offs_ = offs, cnt_ = cnt; \
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for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
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emith_ctx_read(r_, offs_); \
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} while (0)
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#define emith_ctx_write(r, offs) do { \
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EMIT_OP_MODRM(0x89, 1, r, xBP); \
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EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
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} while (0)
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#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
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int r_ = r, offs_ = offs, cnt_ = cnt; \
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for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
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emith_ctx_write(r_, offs_); \
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} while (0)
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// assumes EBX is free
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#define emith_ret_to_ctx(offs) { \
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emith_pop(xBX); \
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emith_ctx_write(xBX, offs); \
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}
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#define emith_jump(ptr) { \
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u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
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EMIT_OP(0xe9); \
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@ -429,9 +456,25 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_call_cond(cond, ptr) \
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emith_call(ptr)
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#define emith_call_reg(r) \
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EMIT_OP_MODRM(0xff, 3, 2, r)
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#define emith_call_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 2, xBP); \
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EMIT(offs, u32); \
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}
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#define emith_ret() \
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EMIT_OP(0xc3)
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#define emith_jump_reg(r) \
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EMIT_OP_MODRM(0xff, 3, 4, r)
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#define emith_jump_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 4, xBP); \
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EMIT(offs, u32); \
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}
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#define EMITH_JMP_START(cond) { \
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u8 *cond_ptr; \
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JMP8_POS(cond_ptr)
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@ -476,7 +519,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_pop(xSI); \
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emith_pop(xBP); \
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emith_pop(xBX); \
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EMIT_OP(0xc3); /* ret */\
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emith_ret(); \
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}
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// assumes EBX is free temporary
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#define emith_sh2_wcall(a, tab, ret_ptr) { \
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int arg2_; \
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host_arg2reg(arg2_, 2); \
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emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
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EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
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EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
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emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
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emith_push_imm((long)(ret_ptr)); \
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emith_jump_reg(xBX); \
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}
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#define emith_sh2_dtbf_loop() { \
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