mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: drc: inline dispatcher and irq handling; do write-caused irqs
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@849 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
efd100fc0a
commit
e05b81fc5b
10 changed files with 535 additions and 246 deletions
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@ -41,6 +41,16 @@ static char sh2dasm_buff[64];
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#else
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#define do_host_disasm(x)
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#endif
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#if (DRC_DEBUG & 4)
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static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr)
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{
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if (block != NULL)
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dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
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sh2->pc, block, (signed int)sr >> 12);
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return block;
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}
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#endif
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// } debug
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#define BLOCK_CYCLE_LIMIT 100
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@ -101,7 +111,7 @@ static temp_reg_t reg_temp[] = {
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{ 3, },
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};
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#else
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#elif defined(__i386__)
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#include "../drc/emit_x86.c"
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static const int reg_map_g2h[] = {
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@ -121,6 +131,8 @@ static temp_reg_t reg_temp[] = {
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{ xDX, },
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};
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#else
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#error unsupported arch
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#endif
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#define T 0x00000001
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@ -130,6 +142,7 @@ static temp_reg_t reg_temp[] = {
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#define M 0x00000200
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#define T_save 0x00000800
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#define I_SHIFT 4
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#define Q_SHIFT 8
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#define M_SHIFT 9
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@ -159,12 +172,16 @@ static void **hash_table;
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#define HASH_FUNC(hash_tab, addr) \
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((block_desc **)(hash_tab))[(addr) & HASH_MASK]
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static void REGPARM(2) (*sh2_drc_entry)(const void *block, SH2 *sh2);
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static void (*sh2_drc_exit)(void);
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static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
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static void (*sh2_drc_dispatcher)(void);
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static void (*sh2_drc_exit)(void);
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static void (*sh2_drc_test_irq)(void);
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static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
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// tmp
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extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
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static void REGPARM(1) sh2_test_irq(SH2 *sh2);
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static void flush_tcache(int tcid)
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{
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@ -484,9 +501,14 @@ static int emit_memhandler_read(int size)
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emith_move_r_r(ctxr, CONTEXT_REG);
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switch (size) {
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case 0: // 8
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// must writeback cycles for poll detection stuff
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
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emith_call(p32x_sh2_read8);
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break;
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case 1: // 16
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
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emith_call(p32x_sh2_read16);
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break;
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case 2: // 32
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@ -498,19 +520,32 @@ static int emit_memhandler_read(int size)
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return rcache_get_tmp_arg(0);
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}
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static void emit_memhandler_write(int size)
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static void emit_memhandler_write(int size, u32 pc, int delay)
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{
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int ctxr;
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host_arg2reg(ctxr, 2);
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emith_move_r_r(ctxr, CONTEXT_REG);
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switch (size) {
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case 0: // 8
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emith_call(p32x_sh2_write8);
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// XXX: consider inlining sh2_drc_write8
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if (delay) {
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emith_call(sh2_drc_write8_slot);
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} else {
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emit_move_r_imm32(SHR_PC, pc);
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rcache_clean();
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emith_call(sh2_drc_write8);
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}
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break;
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case 1: // 16
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emith_call(p32x_sh2_write16);
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if (delay) {
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emith_call(sh2_drc_write16_slot);
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} else {
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emit_move_r_imm32(SHR_PC, pc);
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rcache_clean();
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emith_call(sh2_drc_write16);
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}
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break;
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case 2: // 32
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emith_move_r_r(ctxr, CONTEXT_REG);
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emith_call(p32x_sh2_write32);
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break;
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}
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@ -528,19 +563,6 @@ static int emit_indirect_indexed_read(int rx, int ry, int size)
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return emit_memhandler_read(size);
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}
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// tmp_wr -> @(Rx,Ry)
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static void emit_indirect_indexed_write(int tmp_wr, int rx, int ry, int size)
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{
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int a0, t;
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rcache_clean();
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t = rcache_get_tmp_arg(1);
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emith_move_r_r(t, tmp_wr);
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a0 = rcache_get_reg_arg(0, rx);
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t = rcache_get_reg(ry, RC_GR_READ);
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emith_add_r_r(a0, t);
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emit_memhandler_write(size);
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}
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// read @Rn, @rm
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static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
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{
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@ -593,27 +615,67 @@ static void emit_do_static_regs(int is_write, int tmpr)
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}
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}
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static void sh2_generate_utils(void)
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static void emit_block_entry(void)
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{
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int ctx, blk, tmp;
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int arg0, arg1, arg2;
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host_arg2reg(blk, 0);
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host_arg2reg(ctx, 1);
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host_arg2reg(tmp, 2);
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// sh2_drc_entry(void *block, SH2 *sh2)
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sh2_drc_entry = (void *)tcache_ptr;
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emith_sh2_drc_entry();
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emith_move_r_r(CONTEXT_REG, ctx); // move ctx, arg1
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emit_do_static_regs(0, tmp);
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emith_jump_reg(blk); // jump arg0
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// sh2_drc_exit(void)
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sh2_drc_exit = (void *)tcache_ptr;
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emit_do_static_regs(1, tmp);
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emith_sh2_drc_exit();
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host_arg2reg(arg0, 0);
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host_arg2reg(arg1, 1);
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host_arg2reg(arg2, 2);
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#if (DRC_DEBUG & 4)
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emith_move_r_r(arg1, CONTEXT_REG);
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emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
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emith_call(sh2_drc_announce_entry);
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rcache_invalidate();
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#endif
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emith_tst_r_r(arg0, arg0);
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EMITH_SJMP_START(DCOND_EQ);
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emith_jump_reg_c(DCOND_NE, arg0);
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EMITH_SJMP_END(DCOND_EQ);
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}
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static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id)
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{
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block_desc *bd = NULL;
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void *block = NULL;
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*tcache_id = 0;
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// we have full block id tables for data_array and RAM
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// BIOS goes to data_array table too
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if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
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int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
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*tcache_id = 1 + is_slave;
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if (blkid & 1) {
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bd = &block_tables[*tcache_id][blkid >> 1];
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block = bd->tcache_ptr;
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}
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}
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// RAM
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else if ((pc & 0xc6000000) == 0x06000000) {
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int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
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if (blkid & 1) {
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bd = &block_tables[0][blkid >> 1];
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block = bd->tcache_ptr;
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}
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}
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// ROM
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else if ((pc & 0xc6000000) == 0x02000000) {
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bd = HASH_FUNC(hash_table, pc);
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if (bd != NULL) {
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if (bd->addr == pc)
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block = bd->tcache_ptr;
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else
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block = dr_find_block(bd, pc);
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}
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}
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#if (DRC_DEBUG & 1)
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if (bd != NULL)
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bd->refcount++;
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#endif
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return block;
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}
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#define DELAYED_OP \
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@ -628,6 +690,12 @@ static void sh2_generate_utils(void)
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drcf.use_saved_t = 1; \
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}
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#define FLUSH_CYCLES(sr) \
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if (cycles > 0) { \
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emith_sub_r_imm(sr, cycles << 12); \
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cycles = 0; \
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}
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#define CHECK_UNHANDLED_BITS(mask) { \
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if ((op & (mask)) != 0) \
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goto default_; \
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@ -651,7 +719,7 @@ static void sh2_generate_utils(void)
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#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
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#define OF_DELAY_OP (1 << 0)
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static void *sh2_translate(SH2 *sh2, int tcache_id)
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static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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{
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// XXX: maybe use structs instead?
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void *branch_target_ptr[MAX_LOCAL_BRANCHES];
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@ -768,8 +836,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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int blkid;
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_sub_r_imm(sr, cycles << 12);
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cycles = 0;
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FLUSH_CYCLES(sr);
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rcache_flush();
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do_host_disasm(tcache_id);
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@ -863,8 +930,12 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
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case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
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case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
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tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emit_indirect_indexed_write(tmp, SHR_R0, GET_Rn(), op & 3);
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rcache_clean();
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tmp = rcache_get_reg_arg(1, GET_Rm());
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tmp2 = rcache_get_reg_arg(0, SHR_R0);
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tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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emith_add_r_r(tmp2, tmp3);
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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goto end_op;
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case 0x07:
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// MUL.L Rm,Rn 0000nnnnmmmm0111
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@ -954,9 +1025,8 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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emit_move_r_imm32(SHR_PC, pc - 2);
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_clear_msb(tmp, tmp, 20); // clear cycles
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drcf.test_irq = 1;
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cycles = 1;
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break;
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goto end_op;
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case 2: // RTE 0000000000101011
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DELAYED_OP;
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rcache_clean();
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@ -1036,7 +1106,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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tmp = rcache_get_reg_arg(0, GET_Rn());
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tmp2 = rcache_get_reg_arg(1, GET_Rm());
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emith_add_r_imm(tmp, (op & 0x0f) * 4);
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emit_memhandler_write(2);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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goto end_op;
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case 0x02:
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@ -1048,7 +1118,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_clean();
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rcache_get_reg_arg(0, GET_Rn());
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rcache_get_reg_arg(1, GET_Rm());
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emit_memhandler_write(op & 3);
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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goto end_op;
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case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
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case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
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@ -1058,7 +1128,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_clean();
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rcache_get_reg_arg(0, GET_Rn());
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rcache_get_reg_arg(1, GET_Rm());
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emit_memhandler_write(op & 3);
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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goto end_op;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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@ -1380,8 +1450,8 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_get_reg_arg(0, GET_Rn());
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tmp3 = rcache_get_reg_arg(1, tmp);
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if (tmp == SHR_SR)
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emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0
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emit_memhandler_write(2);
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emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
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emit_memhandler_write(2, pc, drcf.delayed_op);
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goto end_op;
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case 0x04:
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case 0x05:
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@ -1541,7 +1611,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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emith_move_r_r(tmp2, tmp);
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rcache_free_tmp(tmp);
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rcache_get_reg_arg(0, GET_Rn());
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emit_memhandler_write(0);
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emit_memhandler_write(0, pc, drcf.delayed_op);
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cycles += 3;
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break;
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default:
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@ -1720,7 +1790,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = rcache_get_reg_arg(1, SHR_R0);
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tmp3 = (op & 0x100) >> 8;
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emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
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emit_memhandler_write(tmp3);
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emit_memhandler_write(tmp3, pc, drcf.delayed_op);
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goto end_op;
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case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
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case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
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@ -1824,7 +1894,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = rcache_get_reg_arg(1, SHR_R0);
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tmp3 = (op & 0x300) >> 8;
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emith_add_r_imm(tmp, (op & 0xff) << tmp3);
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emit_memhandler_write(tmp3);
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emit_memhandler_write(tmp3, pc, drcf.delayed_op);
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goto end_op;
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case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
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case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
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@ -1850,12 +1920,12 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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emith_add_r_imm(tmp, 4);
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tmp = rcache_get_reg_arg(1, SHR_SR);
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emith_clear_msb(tmp, tmp, 22);
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emit_memhandler_write(2);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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// push PC
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rcache_get_reg_arg(0, SHR_SP);
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tmp = rcache_get_tmp_arg(1);
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emith_move_r_imm(tmp, pc);
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emit_memhandler_write(2);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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// obtain new PC
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tmp = rcache_get_reg_arg(0, SHR_VBR);
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emith_add_r_imm(tmp, (op & 0xff) * 4);
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@ -1918,7 +1988,7 @@ static void *sh2_translate(SH2 *sh2, int tcache_id)
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tmp3 = rcache_get_reg_arg(0, SHR_GBR);
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tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
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emith_add_r_r(tmp3, tmp4);
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emit_memhandler_write(0);
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emit_memhandler_write(0, pc, drcf.delayed_op);
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cycles += 2;
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goto end_op;
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}
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@ -1962,8 +2032,7 @@ end_op:
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if (branch_patch_cond != -1 && drcf.delayed_op != 2) {
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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// handle cycles
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emith_sub_r_imm(sr, cycles << 12);
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cycles = 0;
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FLUSH_CYCLES(sr);
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rcache_clean();
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if (drcf.use_saved_t)
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@ -1983,8 +2052,16 @@ end_op:
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}
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}
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// test irq?
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if (drcf.test_irq && drcf.delayed_op != 2)
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break;
|
||||
// XXX: delay slots..
|
||||
if (drcf.test_irq && drcf.delayed_op != 2) {
|
||||
if (!drcf.delayed_op)
|
||||
emit_move_r_imm32(SHR_PC, pc);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
FLUSH_CYCLES(sr);
|
||||
rcache_flush();
|
||||
emith_call(sh2_drc_test_irq);
|
||||
drcf.test_irq = 0;
|
||||
}
|
||||
if (drcf.delayed_op == 1)
|
||||
break;
|
||||
|
||||
|
|
@ -1995,19 +2072,13 @@ end_op:
|
|||
if (!drcf.delayed_op)
|
||||
emit_move_r_imm32(SHR_PC, pc);
|
||||
|
||||
if (drcf.test_irq) {
|
||||
rcache_flush();
|
||||
emith_pass_arg_r(0, CONTEXT_REG);
|
||||
emith_call(sh2_test_irq);
|
||||
}
|
||||
|
||||
end_block_btf:
|
||||
this_block->end_addr = pc;
|
||||
|
||||
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_sub_r_imm(tmp, cycles << 12);
|
||||
FLUSH_CYCLES(tmp);
|
||||
rcache_flush();
|
||||
emith_jump(sh2_drc_exit);
|
||||
emith_jump(sh2_drc_dispatcher);
|
||||
|
||||
// link local branches
|
||||
for (i = 0; i < branch_patch_count; i++) {
|
||||
|
|
@ -2023,7 +2094,7 @@ end_block_btf:
|
|||
target = tcache_ptr;
|
||||
emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
|
||||
rcache_flush();
|
||||
emith_jump(sh2_drc_exit);
|
||||
emith_jump(sh2_drc_dispatcher);
|
||||
}
|
||||
emith_jump_patch(branch_patch_ptr[i], target);
|
||||
}
|
||||
|
|
@ -2085,67 +2156,165 @@ unimplemented:
|
|||
*/
|
||||
}
|
||||
|
||||
void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
|
||||
static void sh2_generate_utils(void)
|
||||
{
|
||||
// TODO: need to handle self-caused interrupts
|
||||
sh2_test_irq(sh2);
|
||||
int arg0, arg1, arg2, sr, tmp;
|
||||
void *sh2_drc_write_end, *sh2_drc_write_slot_end;
|
||||
|
||||
while (((signed int)sh2->sr >> 12) > 0)
|
||||
{
|
||||
void *block = NULL;
|
||||
block_desc *bd = NULL;
|
||||
int tcache_id = 0;
|
||||
host_arg2reg(arg0, 0);
|
||||
host_arg2reg(arg1, 1);
|
||||
host_arg2reg(arg2, 2);
|
||||
emith_move_r_r(arg0, arg0); // nop
|
||||
|
||||
// FIXME: must avoid doing it so often..
|
||||
//sh2_test_irq(sh2);
|
||||
// sh2_drc_exit(void)
|
||||
sh2_drc_exit = (void *)tcache_ptr;
|
||||
emit_do_static_regs(1, arg2);
|
||||
emith_sh2_drc_exit();
|
||||
|
||||
// we have full block id tables for data_array and RAM
|
||||
// BIOS goes to data_array table too
|
||||
if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
|
||||
int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
|
||||
tcache_id = 1 + sh2->is_slave;
|
||||
if (blkid & 1) {
|
||||
bd = &block_tables[tcache_id][blkid >> 1];
|
||||
block = bd->tcache_ptr;
|
||||
}
|
||||
}
|
||||
// RAM
|
||||
else if ((sh2->pc & 0xc6000000) == 0x06000000) {
|
||||
int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
|
||||
if (blkid & 1) {
|
||||
bd = &block_tables[tcache_id][blkid >> 1];
|
||||
block = bd->tcache_ptr;
|
||||
}
|
||||
}
|
||||
// ROM
|
||||
else if ((sh2->pc & 0xc6000000) == 0x02000000) {
|
||||
bd = HASH_FUNC(hash_table, sh2->pc);
|
||||
// sh2_drc_dispatcher(void)
|
||||
sh2_drc_dispatcher = (void *)tcache_ptr;
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_cmp_r_imm(sr, 0);
|
||||
emith_jump_cond(DCOND_LT, sh2_drc_exit);
|
||||
rcache_invalidate();
|
||||
emith_ctx_read(arg0, SHR_PC * 4);
|
||||
emith_ctx_read(arg1, offsetof(SH2, is_slave));
|
||||
emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
|
||||
emith_call(lookup_block);
|
||||
emit_block_entry();
|
||||
// lookup failed, call sh2_translate()
|
||||
emith_move_r_r(arg0, CONTEXT_REG);
|
||||
emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
|
||||
emith_call(sh2_translate);
|
||||
emit_block_entry();
|
||||
// sh2_translate() failed, flush cache and retry
|
||||
emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
|
||||
emith_call(flush_tcache);
|
||||
emith_move_r_r(arg0, CONTEXT_REG);
|
||||
emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
|
||||
emith_call(sh2_translate);
|
||||
emit_block_entry();
|
||||
// XXX: can't translate, fail
|
||||
emith_call(exit);
|
||||
|
||||
if (bd != NULL) {
|
||||
if (bd->addr == sh2->pc)
|
||||
block = bd->tcache_ptr;
|
||||
else
|
||||
block = dr_find_block(bd, sh2->pc);
|
||||
}
|
||||
}
|
||||
|
||||
if (block == NULL)
|
||||
block = sh2_translate(sh2, tcache_id);
|
||||
if (block == NULL) {
|
||||
// sh2_translate failed, possibly tcache overflow, clean up and try again
|
||||
flush_tcache(tcache_id);
|
||||
block = sh2_translate(sh2, tcache_id);
|
||||
}
|
||||
|
||||
dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
|
||||
sh2->pc, block, (signed int)sh2->sr >> 12);
|
||||
#if (DRC_DEBUG & 1)
|
||||
if (bd != NULL)
|
||||
bd->refcount++;
|
||||
// sh2_drc_test_irq(void)
|
||||
// assumes it's called from main function (may jump to dispatcher)
|
||||
sh2_drc_test_irq = (void *)tcache_ptr;
|
||||
emith_ctx_read(arg1, offsetof(SH2, pending_level));
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_lsr(arg0, sr, I_SHIFT);
|
||||
emith_and_r_imm(arg0, 0x0f);
|
||||
emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
|
||||
EMITH_SJMP_START(DCOND_GT);
|
||||
emith_ret_c(DCOND_LE); // nope, return
|
||||
EMITH_SJMP_END(DCOND_GT);
|
||||
// adjust SP
|
||||
tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
|
||||
emith_sub_r_imm(tmp, 4*2);
|
||||
rcache_clean();
|
||||
// push SR
|
||||
tmp = rcache_get_reg_arg(0, SHR_SP);
|
||||
emith_add_r_imm(tmp, 4);
|
||||
tmp = rcache_get_reg_arg(1, SHR_SR);
|
||||
emith_clear_msb(tmp, tmp, 22);
|
||||
emith_move_r_r(arg2, CONTEXT_REG);
|
||||
emith_call(p32x_sh2_write32);
|
||||
rcache_invalidate();
|
||||
// push PC
|
||||
rcache_get_reg_arg(0, SHR_SP);
|
||||
emith_ctx_read(arg1, SHR_PC * 4);
|
||||
emith_move_r_r(arg2, CONTEXT_REG);
|
||||
emith_call(p32x_sh2_write32);
|
||||
rcache_invalidate();
|
||||
// update I, cycles, do callback
|
||||
emith_ctx_read(arg1, offsetof(SH2, pending_level));
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, I);
|
||||
emith_or_r_r_lsl(sr, arg1, I_SHIFT);
|
||||
emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
|
||||
rcache_flush();
|
||||
emith_move_r_r(arg0, CONTEXT_REG);
|
||||
emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
|
||||
// obtain new PC
|
||||
emith_lsl(arg0, arg0, 2);
|
||||
emith_ctx_read(arg1, SHR_VBR * 4);
|
||||
emith_add_r_r(arg0, arg1);
|
||||
emit_memhandler_read(2);
|
||||
emith_ctx_write(arg0, SHR_PC * 4);
|
||||
#ifdef __i386__
|
||||
emith_add_r_imm(xSP, 4); // fix stack
|
||||
#endif
|
||||
emith_jump(sh2_drc_dispatcher);
|
||||
rcache_invalidate();
|
||||
|
||||
// sh2_drc_entry(SH2 *sh2)
|
||||
sh2_drc_entry = (void *)tcache_ptr;
|
||||
emith_sh2_drc_entry();
|
||||
emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
|
||||
emit_do_static_regs(0, arg2);
|
||||
emith_call(sh2_drc_test_irq);
|
||||
emith_jump(sh2_drc_dispatcher);
|
||||
|
||||
// write-caused irq detection
|
||||
sh2_drc_write_end = tcache_ptr;
|
||||
emith_tst_r_r(arg0, arg0);
|
||||
EMITH_SJMP_START(DCOND_NE);
|
||||
emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
|
||||
EMITH_SJMP_END(DCOND_NE);
|
||||
// since PC is up to date, jump to it's block instead of returning
|
||||
emith_call(sh2_drc_test_irq);
|
||||
emith_jump_ctx(offsetof(SH2, drc_tmp));
|
||||
|
||||
// write-caused irq detection for writes in delay slot
|
||||
sh2_drc_write_slot_end = tcache_ptr;
|
||||
emith_tst_r_r(arg0, arg0);
|
||||
EMITH_SJMP_START(DCOND_NE);
|
||||
emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
|
||||
EMITH_SJMP_END(DCOND_NE);
|
||||
// just burn cycles to get back to dispatcher after branch is handled
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_ctx_write(sr, offsetof(SH2, irq_cycles));
|
||||
emith_clear_msb(sr, sr, 20); // clear cycles
|
||||
rcache_flush();
|
||||
emith_jump_ctx(offsetof(SH2, drc_tmp));
|
||||
|
||||
// sh2_drc_write8(u32 a, u32 d)
|
||||
sh2_drc_write8 = (void *)tcache_ptr;
|
||||
emith_ret_to_ctx(offsetof(SH2, drc_tmp));
|
||||
emith_ctx_read(arg2, offsetof(SH2, write8_tab));
|
||||
emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
|
||||
|
||||
// sh2_drc_write16(u32 a, u32 d)
|
||||
sh2_drc_write16 = (void *)tcache_ptr;
|
||||
emith_ret_to_ctx(offsetof(SH2, drc_tmp));
|
||||
emith_ctx_read(arg2, offsetof(SH2, write16_tab));
|
||||
emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
|
||||
|
||||
// sh2_drc_write8_slot(u32 a, u32 d)
|
||||
sh2_drc_write8_slot = (void *)tcache_ptr;
|
||||
emith_ret_to_ctx(offsetof(SH2, drc_tmp));
|
||||
emith_ctx_read(arg2, offsetof(SH2, write8_tab));
|
||||
emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
|
||||
|
||||
// sh2_drc_write16_slot(u32 a, u32 d)
|
||||
sh2_drc_write16_slot = (void *)tcache_ptr;
|
||||
emith_ret_to_ctx(offsetof(SH2, drc_tmp));
|
||||
emith_ctx_read(arg2, offsetof(SH2, write16_tab));
|
||||
emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
|
||||
|
||||
rcache_invalidate();
|
||||
#if (DRC_DEBUG & 2)
|
||||
host_dasm_new_symbol(sh2_drc_entry);
|
||||
host_dasm_new_symbol(sh2_drc_dispatcher);
|
||||
host_dasm_new_symbol(sh2_drc_exit);
|
||||
host_dasm_new_symbol(sh2_drc_test_irq);
|
||||
host_dasm_new_symbol(sh2_drc_write_end);
|
||||
host_dasm_new_symbol(sh2_drc_write_slot_end);
|
||||
host_dasm_new_symbol(sh2_drc_write8);
|
||||
host_dasm_new_symbol(sh2_drc_write8_slot);
|
||||
host_dasm_new_symbol(sh2_drc_write16);
|
||||
host_dasm_new_symbol(sh2_drc_write16_slot);
|
||||
#endif
|
||||
sh2_drc_entry(block, sh2);
|
||||
dbg(4, "= leave %p", block);
|
||||
}
|
||||
}
|
||||
|
||||
static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
|
||||
|
|
@ -2193,6 +2362,7 @@ void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
|
|||
|
||||
void sh2_execute(SH2 *sh2c, int cycles)
|
||||
{
|
||||
int ret_cycles;
|
||||
sh2 = sh2c; // XXX
|
||||
|
||||
sh2c->cycles_aim += cycles;
|
||||
|
|
@ -2203,23 +2373,14 @@ void sh2_execute(SH2 *sh2c, int cycles)
|
|||
// others are usual SH2 flags
|
||||
sh2c->sr &= 0x3f3;
|
||||
sh2c->sr |= cycles << 12;
|
||||
sh2_drc_dispatcher(sh2c);
|
||||
sh2_drc_entry(sh2c);
|
||||
|
||||
sh2c->cycles_done += cycles - ((signed int)sh2c->sr >> 12);
|
||||
}
|
||||
// TODO: irq cycles
|
||||
ret_cycles = (signed int)sh2c->sr >> 12;
|
||||
if (ret_cycles > 0)
|
||||
printf("warning: drc returned with cycles: %d\n", ret_cycles);
|
||||
|
||||
static void REGPARM(1) sh2_test_irq(SH2 *sh2)
|
||||
{
|
||||
if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
|
||||
{
|
||||
if (sh2->pending_irl > sh2->pending_int_irq)
|
||||
sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
|
||||
else {
|
||||
sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
|
||||
sh2->pending_int_irq = 0; // auto-clear
|
||||
sh2->pending_level = sh2->pending_irl;
|
||||
}
|
||||
}
|
||||
sh2c->cycles_done += cycles - ret_cycles;
|
||||
}
|
||||
|
||||
#if (DRC_DEBUG & 1)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue