mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: drc: inline dispatcher and irq handling; do write-caused irqs
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@849 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
efd100fc0a
commit
e05b81fc5b
10 changed files with 535 additions and 246 deletions
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@ -4,10 +4,19 @@
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struct Pico32x Pico32x;
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SH2 sh2s[2];
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static void sh2_irq_cb(int id, int level)
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static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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{
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// diagnostic for now
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elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id));
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if (sh2->pending_irl > sh2->pending_int_irq) {
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elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
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sh2->is_slave ? 's' : 'm', level, sh2->pc);
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return 64 + sh2->pending_irl / 2;
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} else {
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elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
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sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
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sh2->pending_int_irq = 0; // auto-clear
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sh2->pending_level = sh2->pending_irl;
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return sh2->pending_int_vector;
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}
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}
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void p32x_update_irls(void)
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@ -523,7 +523,7 @@ static u32 sh2_peripheral_read32(u32 a, int id)
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return d;
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}
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static void sh2_peripheral_write8(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
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{
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u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
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elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
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@ -540,11 +540,13 @@ static void sh2_peripheral_write8(u32 a, u32 d, int id)
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int vector = PREG8(oregs, 0x63) & 0x7f;
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elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
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sh2_internal_irq(&sh2s[id ^ 1], level, vector);
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return 1;
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}
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}
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return 0;
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}
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static void sh2_peripheral_write16(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
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{
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u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
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elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
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@ -559,10 +561,11 @@ static void sh2_peripheral_write16(u32 a, u32 d, int id)
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}
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if ((d & 0xff00) == 0x5a00) // WTCNT
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PREG8(r, 0x81) = d;
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return;
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return 0;
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}
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r[(a / 2) ^ 1] = d;
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return 0;
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}
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static void sh2_peripheral_write32(u32 a, u32 d, int id)
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@ -1016,52 +1019,55 @@ static u32 sh2_read16_da(u32 a, int id)
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return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
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}
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static void sh2_write_ignore(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
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{
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return 0;
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}
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// write8
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static void sh2_write8_unmapped(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
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{
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elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
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id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
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return 0;
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}
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static void sh2_write8_cs0(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
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{
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elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
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id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
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if ((a & 0x3ff00) == 0x4100) {
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p32x_vdp_write8(a, d);
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return;
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return 0;
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}
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if ((a & 0x3ff00) == 0x4000) {
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p32x_sh2reg_write8(a, d, id);
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return;
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return 1;
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}
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sh2_write8_unmapped(a, d, id);
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return sh2_write8_unmapped(a, d, id);
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}
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#define sh2_write8_dramN(n) \
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if (!(a & 0x20000) || d) { \
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u8 *dram = (u8 *)Pico32xMem->dram[n]; \
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dram[(a & 0x1ffff) ^ 1] = d; \
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}
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} \
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return 0;
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static void sh2_write8_dram0(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
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{
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sh2_write8_dramN(0);
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}
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static void sh2_write8_dram1(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
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{
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sh2_write8_dramN(1);
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}
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static void sh2_write8_sdram(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
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{
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u32 a1 = a & 0x3ffff;
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#ifdef DRC_SH2
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@ -1070,9 +1076,10 @@ static void sh2_write8_sdram(u32 a, u32 d, int id)
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sh2_drc_wcheck_ram(a, t, id);
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#endif
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Pico32xMem->sdram[a1 ^ 1] = d;
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return 0;
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}
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static void sh2_write8_da(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
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{
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u32 a1 = a & 0xfff;
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#ifdef DRC_SH2
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@ -1081,16 +1088,18 @@ static void sh2_write8_da(u32 a, u32 d, int id)
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sh2_drc_wcheck_da(a, t, id);
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#endif
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Pico32xMem->data_array[id][a1 ^ 1] = d;
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return 0;
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}
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// write16
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static void sh2_write16_unmapped(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
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{
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elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
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id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
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return 0;
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}
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static void sh2_write16_cs0(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
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{
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if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
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elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
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@ -1099,45 +1108,46 @@ static void sh2_write16_cs0(u32 a, u32 d, int id)
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if ((a & 0x3ff00) == 0x4100) {
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sh2_poll[id].cnt = 0; // for poll before VDP accesses
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p32x_vdp_write16(a, d);
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return;
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return 0;
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}
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if ((a & 0x3fe00) == 0x4200) {
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Pico32xMem->pal[(a & 0x1ff) / 2] = d;
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Pico32x.dirty_pal = 1;
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return;
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return 0;
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}
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if ((a & 0x3ff00) == 0x4000) {
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p32x_sh2reg_write16(a, d, id);
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return;
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return 1;
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}
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sh2_write16_unmapped(a, d, id);
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return sh2_write16_unmapped(a, d, id);
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}
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#define sh2_write16_dramN(n) \
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u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
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if (!(a & 0x20000)) { \
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*pd = d; \
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return; \
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return 0; \
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} \
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/* overwrite */ \
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if (!(d & 0xff00)) d |= *pd & 0xff00; \
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if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
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*pd = d
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*pd = d; \
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return 0
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static void sh2_write16_dram0(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
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{
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sh2_write16_dramN(0);
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}
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static void sh2_write16_dram1(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
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{
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sh2_write16_dramN(1);
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}
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static void sh2_write16_sdram(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
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{
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u32 a1 = a & 0x3ffff;
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#ifdef DRC_SH2
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@ -1146,9 +1156,10 @@ static void sh2_write16_sdram(u32 a, u32 d, int id)
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sh2_drc_wcheck_ram(a, t, id);
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#endif
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((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
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return 0;
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}
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static void sh2_write16_da(u32 a, u32 d, int id)
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static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
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{
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u32 a1 = a & 0xfff;
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#ifdef DRC_SH2
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@ -1157,6 +1168,7 @@ static void sh2_write16_da(u32 a, u32 d, int id)
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sh2_drc_wcheck_da(a, t, id);
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#endif
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((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
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return 0;
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}
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@ -1165,18 +1177,21 @@ typedef struct {
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u32 mask;
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} sh2_memmap;
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typedef u32 (sh2_read_handler)(u32 a, int id);
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typedef void (sh2_write_handler)(u32 a, u32 d, int id);
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typedef u32 (sh2_read_handler)(u32 a, int id);
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typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
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#define SH2MAP_ADDR2OFFS(a) \
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(((a >> 25) & 3) | ((a >> 27) & 0x1c))
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#define SH2MAP_ADDR2OFFS_R(a) \
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((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
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#define SH2MAP_ADDR2OFFS_W(a) \
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((u32)(a) >> SH2_WRITE_SHIFT)
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u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
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{
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const sh2_memmap *sh2_map = sh2->read8_map;
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uptr p;
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sh2_map += SH2MAP_ADDR2OFFS(a);
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sh2_map += SH2MAP_ADDR2OFFS_R(a);
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p = sh2_map->addr;
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if (map_flag_set(p))
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return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
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@ -1189,7 +1204,7 @@ u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
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const sh2_memmap *sh2_map = sh2->read16_map;
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uptr p;
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sh2_map += SH2MAP_ADDR2OFFS(a);
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sh2_map += SH2MAP_ADDR2OFFS_R(a);
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p = sh2_map->addr;
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if (map_flag_set(p))
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return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
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@ -1204,7 +1219,7 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
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u32 offs;
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uptr p;
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offs = SH2MAP_ADDR2OFFS(a);
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offs = SH2MAP_ADDR2OFFS_R(a);
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sh2_map += offs;
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p = sh2_map->addr;
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if (!map_flag_set(p)) {
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@ -1220,40 +1235,42 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
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return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
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}
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void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
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// return nonzero if write potentially causes an interrupt (used by drc)
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int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
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{
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const void **sh2_wmap = sh2->write8_tab;
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sh2_write_handler *wh;
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wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
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wh(a, d, sh2->is_slave);
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wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
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return wh(a, d, sh2->is_slave);
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}
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void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
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int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
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{
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const void **sh2_wmap = sh2->write16_tab;
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sh2_write_handler *wh;
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wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
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wh(a, d, sh2->is_slave);
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wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
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return wh(a, d, sh2->is_slave);
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}
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void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
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int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
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{
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const void **sh2_wmap = sh2->write16_tab;
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sh2_write_handler *handler;
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u32 offs;
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offs = SH2MAP_ADDR2OFFS(a);
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offs = SH2MAP_ADDR2OFFS_W(a);
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if (offs == 0x1f) {
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if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
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sh2_peripheral_write32(a, d, sh2->is_slave);
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return;
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return 0;
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}
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handler = sh2_wmap[offs];
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handler(a, d >> 16, sh2->is_slave);
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handler(a + 2, d, sh2->is_slave);
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return 0;
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}
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// -----------------------------------------------------------------
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@ -1380,7 +1397,7 @@ static void get_bios(void)
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static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
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// for writes we are using handlers only
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static void *sh2_write8_map[0x20], *sh2_write16_map[0x20];
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static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
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void Pico32xSwapDRAM(int b)
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{
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@ -1393,8 +1410,8 @@ void Pico32xSwapDRAM(int b)
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sh2_read8_map[2].addr = sh2_read8_map[6].addr =
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sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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sh2_write8_map[2] = sh2_write8_map[6] = b ? sh2_write8_dram1 : sh2_write8_dram0;
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sh2_write16_map[2] = sh2_write16_map[6] = b ? sh2_write16_dram1 : sh2_write16_dram0;
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sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
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sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
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}
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void PicoMemSetup32x(void)
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@ -1448,24 +1465,27 @@ void PicoMemSetup32x(void)
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// SH2 maps: A31,A30,A29,CS1,CS0
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// all unmapped by default
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for (i = 0; i < 0x20; i++) {
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for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
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sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
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sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
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}
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for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
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sh2_write8_map[i] = sh2_write8_unmapped;
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sh2_write16_map[i] = sh2_write16_unmapped;
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}
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// "purge area"
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for (i = 0x08; i <= 0x0b; i++) {
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sh2_write8_map[i] =
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sh2_write16_map[i] = sh2_write_ignore;
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for (i = 0x40; i <= 0x5f; i++) {
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sh2_write8_map[i >> 1] =
|
||||
sh2_write16_map[i >> 1] = sh2_write_ignore;
|
||||
}
|
||||
|
||||
// CS0
|
||||
sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
|
||||
sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
|
||||
sh2_write8_map[0] = sh2_write8_map[4] = sh2_write8_cs0;
|
||||
sh2_write16_map[0] = sh2_write16_map[4] = sh2_write16_cs0;
|
||||
sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
|
||||
sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
|
||||
// CS1 - ROM
|
||||
sh2_read8_map[1].addr = sh2_read8_map[5].addr =
|
||||
sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
|
||||
|
|
@ -1477,20 +1497,20 @@ void PicoMemSetup32x(void)
|
|||
// CS3 - SDRAM
|
||||
sh2_read8_map[3].addr = sh2_read8_map[7].addr =
|
||||
sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
|
||||
sh2_write8_map[3] = sh2_write8_map[7] = sh2_write8_sdram;
|
||||
sh2_write16_map[3] = sh2_write16_map[7] = sh2_write16_sdram;
|
||||
sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
|
||||
sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
|
||||
sh2_read8_map[3].mask = sh2_read8_map[7].mask =
|
||||
sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
|
||||
// SH2 data array
|
||||
sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
|
||||
sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
|
||||
sh2_write8_map[0x18] = sh2_write8_da;
|
||||
sh2_write16_map[0x18] = sh2_write16_da;
|
||||
sh2_write8_map[0xc0/2] = sh2_write8_da;
|
||||
sh2_write16_map[0xc0/2] = sh2_write16_da;
|
||||
// SH2 IO
|
||||
sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
|
||||
sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
|
||||
sh2_write8_map[0x1f] = sh2_peripheral_write8;
|
||||
sh2_write16_map[0x1f] = sh2_peripheral_write16;
|
||||
sh2_write8_map[0xff/2] = sh2_peripheral_write8;
|
||||
sh2_write16_map[0xff/2] = sh2_peripheral_write16;
|
||||
|
||||
// map DRAM area, both 68k and SH2
|
||||
Pico32xSwapDRAM(1);
|
||||
|
|
|
|||
|
|
@ -469,6 +469,8 @@ typedef struct
|
|||
#define SH2_DRCBLK_RAM_SHIFT 1
|
||||
#define SH2_DRCBLK_DA_SHIFT 1
|
||||
|
||||
#define SH2_WRITE_SHIFT 25
|
||||
|
||||
struct Pico32x
|
||||
{
|
||||
unsigned short regs[0x20];
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue