mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
'and A,A' fixed, some reorganization
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@366 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
bad5731da9
commit
e477f8f74f
2 changed files with 134 additions and 98 deletions
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@ -7,6 +7,11 @@
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// For commercial use, separate licencing terms must be obtained.
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//#define USE_DEBUGGER
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/* detect ops with unimplemented/invalid fields.
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* Useful for homebrew or if a new VR revision pops up. */
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//#define DO_CHECKS
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#include "../../PicoInt.h"
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/*
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@ -131,7 +136,7 @@
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* These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
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* ar probably invalid.
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*
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* r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
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* r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
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* They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
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* Samsung's old DSP page claims that).
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* 1 of these 4 modifiers must be used (short form direct addressing?):
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@ -173,25 +178,20 @@
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*
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* 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
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* 30fe06 - also sync related.
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* 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
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* 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
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*
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* + figure out if 'op A, P' is 32bit (nearly sure it is)
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* * does mld, mpya load their operands into X and Y?
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* * OP simm
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*
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* Assumptions in this code
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* P is not directly writeable
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* flags correspond to full 32bit accumulator
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* only Z and N status flags are emulated (others unused by SVP)
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* modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
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* Assumptions and limitations in this code
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* only Z and N status flags are emulated (others unused by VR)
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* so all condition checks except N and Z are ignored (not used by VR)
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* modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
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* loop repeat mode when (ri) is destination is ignored
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* ops not used by VR are not implemented
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*/
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#include "../../PicoInt.h"
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#define u32 unsigned int
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//#define USE_DEBUGGER
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// 0
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#define rX ssp->gr[SSP_X].h
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#define rY ssp->gr[SSP_Y].h
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@ -247,7 +247,7 @@
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else rST |= (rA32>>16)&SSP_FLAG_N;
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// standard cond processing.
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// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
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// again, only Z and N is checked, as VR doesn't seem to use any other conds.
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#define COND_CHECK \
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switch (op&0xf0) { \
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case 0x00: cond = 1; break; /* always true */ \
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@ -324,14 +324,45 @@
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UPD_ACC_ZN
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#define OP_CHECK32(OP) \
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if ((op & 0x0f) == SSP_P) { /* A <- P */ \
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read_P(); /* update P */ \
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OP(rP.v); \
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break; \
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#define OP_CHECK32(OP) { \
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if ((op & 0x0f) == SSP_P) { /* A <- P */ \
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read_P(); /* update P */ \
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OP(rP.v); \
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break; \
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} \
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if ((op & 0x0f) == SSP_A) { /* A <- A */ \
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OP(rA32); \
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break; \
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} \
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}
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#ifdef DO_CHECKS
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#define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS())
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#define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
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#else
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#define CHECK_IMM16()
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#define CHECK_B_SET()
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#define CHECK_B_CLEAR()
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#define CHECK_MOD()
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#define CHECK_10f()
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#define CHECK_008()
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#define CHECK_00f()
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#define CHECK_0f0()
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#define CHECK_1f0()
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#define CHECK_RPL()
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#define CHECK_ST(d)
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#endif
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#ifndef EMBED_INTERPRETER
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static
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#endif
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@ -365,8 +396,7 @@ static void write_unknown(u32 d)
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// 4
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static void write_ST(u32 d)
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{
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//if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
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if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
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CHECK_ST(d);
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rST = d;
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}
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@ -826,30 +856,30 @@ static void ptr1_write(int op, u32 d)
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// mod=1 (01), "+!"
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// mod=3, "+"
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case 0x08:
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case 0x18:
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case 0x09:
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case 0x19:
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case 0x0a:
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case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
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case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
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case 0x0b: ssp->RAM0[1] = d; return;
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case 0x0c:
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case 0x1c:
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case 0x0d:
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case 0x1d:
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case 0x0e:
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case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
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case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
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case 0x0f: ssp->RAM1[1] = d; return;
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// mod=2 (10), "-"
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case 0x10:
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case 0x11:
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case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
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case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
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case 0x13: ssp->RAM0[2] = d; return;
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case 0x14:
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case 0x15:
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case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
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case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
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case 0x17: ssp->RAM1[2] = d; return;
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// mod=3 (11)
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// mod=3 (11), "+"
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case 0x18:
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case 0x19:
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case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
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case 0x1b: ssp->RAM0[3] = d; return;
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case 0x1c:
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case 0x1d:
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case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
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case 0x1f: ssp->RAM1[3] = d; return;
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}
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}
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@ -1021,6 +1051,7 @@ void ssp1601_run(int cycles)
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{
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// ld d, s
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case 0x00:
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CHECK_B_SET();
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if (op == 0) break; // nop
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if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
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// not sure. MAME claims that only hi word is transfered.
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@ -1041,22 +1072,22 @@ void ssp1601_run(int cycles)
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case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
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// ldi d, imm
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case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
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case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
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// ld d, ((ri))
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case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
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case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
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// ldi (ri), imm
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case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
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case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
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// ld adr, a
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case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
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// ld d, ri
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case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
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case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
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// ld ri, s
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case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
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case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
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// ldi ri, simm
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case 0x0c:
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@ -1067,27 +1098,37 @@ void ssp1601_run(int cycles)
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// call cond, addr
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case 0x24: {
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int cond = 0;
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CHECK_00f();
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COND_CHECK
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if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
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if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
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else PC++;
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g_cycles--; // always 2 cycles
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break;
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}
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// ld d, (a)
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case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
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case 0x25:
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CHECK_10f();
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tmpv = ((unsigned short *)svp->iram_rom)[rA];
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REG_WRITE((op & 0xf0) >> 4, tmpv);
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g_cycles -= 2; // 3 cycles total
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break;
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// bra cond, addr
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case 0x26: {
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int cond = 0;
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CHECK_00f();
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COND_CHECK
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if (cond) { int new_PC = *PC++; write_PC(new_PC); }
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if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
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else PC++;
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g_cycles--;
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break;
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}
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// mod cond, op
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case 0x48: {
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int cond = 0;
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CHECK_008();
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COND_CHECK
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if (cond) {
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switch (op & 7) {
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@ -1098,52 +1139,56 @@ void ssp1601_run(int cycles)
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default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
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op&7, GET_PPC_OFFS());
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}
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UPD_ACC_ZN // ?
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UPD_ACC_ZN
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}
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break;
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}
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// mpys?
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case 0x1b:
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CHECK_B_CLEAR();
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read_P(); // update P
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rA32 -= rP.v; // maybe only upper word?
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UPD_ACC_ZN // there checking flags after this
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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rA32 -= rP.v;
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UPD_ACC_ZN
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
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break;
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// mpya (rj), (ri), b
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case 0x4b:
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CHECK_B_CLEAR();
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read_P(); // update P
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rA32 += rP.v; // confirmed to be 32bit
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UPD_ACC_ZN // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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rA32 += rP.v;
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UPD_ACC_ZN
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
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break;
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// mld (rj), (ri), b
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case 0x5b:
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CHECK_B_CLEAR();
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rA32 = 0;
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rST &= 0x0fff; // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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rST &= 0x0fff;
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rST |= SSP_FLAG_Z;
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
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break;
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// OP a, s
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case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
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case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
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case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
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case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
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case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
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case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
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case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
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case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
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case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
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case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
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case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
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case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
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// OP a, (ri)
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case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
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case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
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case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
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case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
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case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
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case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
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case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
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case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
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case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
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case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
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case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
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case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
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// OP a, adr
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case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
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@ -1155,41 +1200,37 @@ void ssp1601_run(int cycles)
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case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
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// OP a, imm
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case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
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case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
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case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
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case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
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case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
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case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
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case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
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case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
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case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
|
||||
case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
|
||||
case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
|
||||
case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
|
||||
|
||||
// OP a, ((ri))
|
||||
case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
|
||||
case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
|
||||
case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
|
||||
case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
|
||||
case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
|
||||
case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
|
||||
case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
|
||||
case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
|
||||
case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
|
||||
case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
|
||||
case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
|
||||
case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
|
||||
|
||||
// OP a, ri
|
||||
case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
|
||||
case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
|
||||
case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
|
||||
case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
|
||||
case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
|
||||
case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
|
||||
case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
|
||||
case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
|
||||
case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
|
||||
case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
|
||||
case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
|
||||
case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
|
||||
|
||||
// OP simm
|
||||
case 0x1c: OP_SUBA(op & 0xff); break;
|
||||
case 0x3c: OP_CMPA(op & 0xff); break;
|
||||
case 0x4c: OP_ADDA(op & 0xff); break;
|
||||
// MAME code only does LSB of top word, but this looks wrong to me.
|
||||
case 0x5c: OP_ANDA(op & 0xff); break;
|
||||
case 0x6c: OP_ORA (op & 0xff); break;
|
||||
case 0x7c: OP_EORA(op & 0xff); break;
|
||||
case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
|
||||
case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
|
||||
case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
|
||||
case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
|
||||
case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
|
||||
case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
|
||||
|
||||
#ifdef EMBED_INTERPRETER
|
||||
case 0x7f: goto interp_end; /* pseudo op */
|
||||
#endif
|
||||
default:
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
|
||||
break;
|
||||
|
|
@ -1198,12 +1239,6 @@ void ssp1601_run(int cycles)
|
|||
}
|
||||
|
||||
rPC = GET_PC();
|
||||
#ifdef EMBED_INTERPRETER
|
||||
interp_end:
|
||||
#endif
|
||||
read_P(); // update P
|
||||
|
||||
if (ssp->gr[SSP_GR0].v != 0xffff0000)
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ void PicoSVPStartup(void)
|
|||
|
||||
elprintf(EL_SVP, "SVP init");
|
||||
|
||||
PicoOpt |= 0x20000;
|
||||
tmp = realloc(Pico.rom, 0x200000 + sizeof(*svp));
|
||||
if (tmp == NULL)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue