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https://github.com/RaySollium99/picodrive.git
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memhandlers slightly improved
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@234 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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commit
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7 changed files with 369 additions and 159 deletions
206
Pico/Memory.s
206
Pico/Memory.s
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@ -7,6 +7,7 @@
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@ All Rights Reserved
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.include "port_config.s"
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.text
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@ -140,7 +141,10 @@ m_read32_table:
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.global PicoRead8
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.global PicoRead16
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.global PicoRead32
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.global PicoWrite8
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.global PicoWriteRomHW_SSF2
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.global m_m68k_read8_misc
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.global m_m68k_write8_misc
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PicoMemReset:
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@ -359,12 +363,70 @@ m_read8_rom12: @ 0x900000 - 0x97ffff
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m_read8_rom13: @ 0x980000 - 0x9fffff
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m_read8_rom 0x13
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m_m68k_read8_misc:
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m_read8_misc:
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bic r2, r0, #0x00ff
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bic r2, r2, #0xbf00
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cmp r2, #0xa00000 @ Z80 RAM?
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ldreq r2, =z80Read8
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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bne m_read8_misc2
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m_read8_misc_io:
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ands r0, r0, #0x1e
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beq m_read8_misc_hwreg
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cmp r0, #4
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ldrle r2, =PadRead
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movlt r0, #0
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moveq r0, #1
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bxle r2
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ldr r3, =(Pico+0x22000)
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mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])
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ldrb r0, [r3, r0]
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bx lr
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m_read8_misc_hwreg:
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ldr r3, =(Pico+0x22200)
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ldrb r0, [r3, #0x0f] @ Pico.m.hardware
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bx lr
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m_read8_misc2:
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mov r2, #0xa10000 @ games also like to poll busreq,
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orr r2, r2, #0x001100 @ so we'll try it now
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cmp r0, r2
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ldreq r2, =z80ReadBusReq
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bxeq r2
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and r2, r0, #0xff0000 @ finally it might be
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cmp r2, #0xa00000 @ z80 area
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bne m_read8_misc3
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tst r0, #0x4000
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ldreq r2, =z80Read8 @ z80 RAM
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bxeq r2
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and r2, r0, #0x6000
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cmp r2, #0x4000
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mvnne r0, #0
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bxne lr @ invalid
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.if EXTERNAL_YM2612
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ldr r1, =PicoOpt
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ldr r1, [r1]
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tst r1, #1
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beq m_read8_fake_ym2612
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tst r1, #0x200
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ldreq r2, =YM2612Read_
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ldrne r2, =YM2612Read_940
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.else
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ldr r2, =YM2612Read_
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.endif
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bx r2 @ ym2612
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m_read8_fake_ym2612:
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ldr r3, =(Pico+0x22200)
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ldrb r0, [r3, #8] @ Pico.m.rotate
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add r1, r0, #1
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strb r1, [r3, #8]
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and r0, r0, #3
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bx lr
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m_read8_misc3:
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@ if everything else fails, use generic handler
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stmfd sp!,{r0,lr}
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bic r0, r0, #1
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mov r1, #8
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@ -374,6 +436,7 @@ m_read8_misc:
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moveq r0, r0, lsr #8
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bx lr
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m_read8_vdp:
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tst r0, #0x70000
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tsteq r0, #0x000e0
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@ -738,3 +801,138 @@ pwr_banking:
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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@ Here we only handle most often used locations,
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@ everything else is passed to generic handlers
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PicoWrite8: @ u32 a, u8 d
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bic r0, r0, #0xff000000
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and r2, r0, #0x00e00000
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cmp r2, #0x00e00000 @ RAM?
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ldr r3, =Pico
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biceq r0, r0, #0x00ff0000
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eoreq r0, r0, #1
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streqb r1, [r3, r0]
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bxeq lr
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m_m68k_write8_misc:
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bic r2, r0, #0x1f @ most commonly we get i/o port write,
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cmp r2, #0xa10000 @ so check for it first
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bne m_write8_misc2
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m_write8_io:
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ldr r2, =PicoOpt
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and r0, r0, #0x1e
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ldr r2, [r2]
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ldr r3, =(Pico+0x22000) @ Pico.ioports
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tst r2, #0x20 @ 6 button pad?
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streqb r1, [r3, r0, lsr #1]
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bxeq lr
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cmp r0, #2
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cmpne r0, #4
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bne m_write8_io_done @ not likely to happen
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add r2, r3, #0x200 @ Pico+0x22200
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mov r12,#0
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cmp r0, #2
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streqb r12,[r2,#0x18]
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strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0
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tst r1, #0x40 @ TH
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beq m_write8_io_done
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ldrb r12,[r3, r0, lsr #1]
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tst r12,#0x40
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bne m_write8_io_done
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cmp r0, #2
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ldreqb r12,[r2,#0x0a]
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ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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add r12,r12,#1
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streqb r12,[r2,#0x0a]
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strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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m_write8_io_done:
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strb r1, [r3, r0, lsr #1]
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bx lr
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m_write8_misc2:
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and r2, r0, #0xff0000
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cmp r2, #0xa00000 @ z80 area?
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bne m_write8_not_z80
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tst r0, #0x4000
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bne m_write8_z80_not_ram
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ldr r3, =(Pico+0x20000) @ Pico.zram
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add r2, r3, #0x02200 @ Pico+0x22200
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ldrb r2, [r2, #9] @ Pico.m.z80Run
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bic r0, r0, #0xff0000
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bic r0, r0, #0x00e000
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tst r2, #1
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streqb r1, [r3, r0] @ zram
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bx lr
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m_write8_z80_not_ram:
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and r2, r0, #0x6000
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cmp r2, #0x4000
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bne m_write8_z80_not_ym2612
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ldr r2, =PicoOpt
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and r0, r0, #3
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ldr r2, [r2]
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tst r2, #1
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bxeq lr
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stmfd sp!,{lr}
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.if EXTERNAL_YM2612
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tst r2, #0x200
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ldreq r2, =YM2612Write_
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ldrne r2, =YM2612Write_940
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mov lr, pc
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bx r2
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.else
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bl YM2612Write_
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.endif
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ldr r2, =emustatus
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ldmfd sp!,{lr}
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ldr r1, [r2]
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orr r1, r0, r2
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str r1, [r2] @ emustatus|=YM2612Write(a&3, d);
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bx lr
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m_write8_z80_not_ym2612: @ not too likely
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mov r2, r0, lsl #17
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bic r2, r2, #6<<17
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mov r3, #0x7f00
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orr r3, r3, #0x0011
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cmp r3, r2, lsr #17 @ psg @ z80 area?
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beq m_write8_psg
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and r2, r0, #0x7f00
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cmp r2, #0x6000 @ bank register?
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bxne lr @ invalid write
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m_write8_z80_bank_reg:
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ldr r3, =(Pico+0x22208) @ Pico.m
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ldrh r2, [r3, #0x0a]
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mov r1, r1, lsr #8
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orr r2, r1, r2, lsr #1
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bic r2, r2, #0xfe00
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strh r2, [r3, #0x0a]
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bx lr
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m_write8_not_z80:
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and r2, r0, #0xe70000
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cmp r2, #0xc00000 @ VDP area?
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bne m_write8_misc4
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and r2, r0, #0xf9
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cmp r2, #0x11
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bne m_write8_misc4
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m_write8_psg:
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ldr r2, =PicoOpt
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mov r0, r1
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ldr r2, [r2]
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tst r2, #2
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bxeq lr
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ldr r2, =SN76496Write
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bx r2
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m_write8_misc4:
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@ passthrough
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ldr r2, =OtherWrite8
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bx r2
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