mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
memhandlers slightly improved
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@234 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
a5ccbfbaf0
commit
e5503e2f4f
7 changed files with 369 additions and 159 deletions
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@ -26,6 +26,7 @@ extern unsigned int lastSSRamWrite; // used by serial SRAM code
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#ifdef _ASM_MEMORY_C
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u32 PicoRead8(u32 a);
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u32 PicoRead16(u32 a);
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void PicoWrite8(u32 a,u8 d);
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void PicoWriteRomHW_SSF2(u32 a,u32 d);
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void PicoWriteRomHW_in1 (u32 a,u32 d);
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#endif
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@ -110,6 +111,38 @@ PICO_INTERNAL_ASM void PicoMemReset(void)
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// -----------------------------------------------------------------
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int PadRead(int i)
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{
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int pad,value,data_reg;
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pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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data_reg=Pico.ioports[i+1];
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// orr the bits, which are set as output
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value = data_reg&(Pico.ioports[i+4]|0x80);
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if(PicoOpt & 0x20) { // 6 button gamepad enabled
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int phase = Pico.m.padTHPhase[i];
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if(phase == 2 && !(data_reg&0x40)) { // TH
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value|=(pad&0xc0)>>2; // ?0SA 0000
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return value;
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} else if(phase == 3) {
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if(data_reg&0x40)
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value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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else
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value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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return value;
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}
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}
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if(data_reg&0x40) // TH
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value|=(pad&0x3f); // ?1CB RLDU
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else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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return value; // will mirror later
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}
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#ifndef _ASM_MEMORY_C
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// address must already be checked
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static int SRAMRead(u32 a)
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@ -399,7 +432,8 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)
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// -----------------------------------------------------------------
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// Write Ram
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static void CPU_CALL PicoWrite8(u32 a,u8 d)
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#ifndef _ASM_MEMORY_C
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PICO_INTERNAL_ASM void CPU_CALL PicoWrite8(u32 a,u8 d)
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{
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#ifdef __debug_io
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dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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@ -416,6 +450,7 @@ static void CPU_CALL PicoWrite8(u32 a,u8 d)
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a&=0xffffff;
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OtherWrite8(a,d,8);
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}
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#endif
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void CPU_CALL PicoWrite16(u32 a,u16 d)
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{
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206
Pico/Memory.s
206
Pico/Memory.s
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@ -7,6 +7,7 @@
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@ All Rights Reserved
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.include "port_config.s"
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.text
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@ -140,7 +141,10 @@ m_read32_table:
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.global PicoRead8
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.global PicoRead16
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.global PicoRead32
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.global PicoWrite8
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.global PicoWriteRomHW_SSF2
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.global m_m68k_read8_misc
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.global m_m68k_write8_misc
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PicoMemReset:
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@ -359,12 +363,70 @@ m_read8_rom12: @ 0x900000 - 0x97ffff
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m_read8_rom13: @ 0x980000 - 0x9fffff
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m_read8_rom 0x13
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m_m68k_read8_misc:
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m_read8_misc:
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bic r2, r0, #0x00ff
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bic r2, r2, #0xbf00
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cmp r2, #0xa00000 @ Z80 RAM?
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ldreq r2, =z80Read8
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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bne m_read8_misc2
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m_read8_misc_io:
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ands r0, r0, #0x1e
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beq m_read8_misc_hwreg
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cmp r0, #4
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ldrle r2, =PadRead
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movlt r0, #0
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moveq r0, #1
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bxle r2
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ldr r3, =(Pico+0x22000)
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mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])
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ldrb r0, [r3, r0]
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bx lr
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m_read8_misc_hwreg:
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ldr r3, =(Pico+0x22200)
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ldrb r0, [r3, #0x0f] @ Pico.m.hardware
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bx lr
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m_read8_misc2:
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mov r2, #0xa10000 @ games also like to poll busreq,
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orr r2, r2, #0x001100 @ so we'll try it now
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cmp r0, r2
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ldreq r2, =z80ReadBusReq
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bxeq r2
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and r2, r0, #0xff0000 @ finally it might be
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cmp r2, #0xa00000 @ z80 area
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bne m_read8_misc3
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tst r0, #0x4000
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ldreq r2, =z80Read8 @ z80 RAM
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bxeq r2
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and r2, r0, #0x6000
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cmp r2, #0x4000
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mvnne r0, #0
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bxne lr @ invalid
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.if EXTERNAL_YM2612
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ldr r1, =PicoOpt
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ldr r1, [r1]
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tst r1, #1
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beq m_read8_fake_ym2612
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tst r1, #0x200
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ldreq r2, =YM2612Read_
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ldrne r2, =YM2612Read_940
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.else
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ldr r2, =YM2612Read_
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.endif
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bx r2 @ ym2612
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m_read8_fake_ym2612:
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ldr r3, =(Pico+0x22200)
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ldrb r0, [r3, #8] @ Pico.m.rotate
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add r1, r0, #1
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strb r1, [r3, #8]
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and r0, r0, #3
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bx lr
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m_read8_misc3:
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@ if everything else fails, use generic handler
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stmfd sp!,{r0,lr}
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bic r0, r0, #1
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mov r1, #8
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@ -374,6 +436,7 @@ m_read8_misc:
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moveq r0, r0, lsr #8
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bx lr
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m_read8_vdp:
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tst r0, #0x70000
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tsteq r0, #0x000e0
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@ -738,3 +801,138 @@ pwr_banking:
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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@ Here we only handle most often used locations,
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@ everything else is passed to generic handlers
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PicoWrite8: @ u32 a, u8 d
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bic r0, r0, #0xff000000
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and r2, r0, #0x00e00000
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cmp r2, #0x00e00000 @ RAM?
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ldr r3, =Pico
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biceq r0, r0, #0x00ff0000
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eoreq r0, r0, #1
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streqb r1, [r3, r0]
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bxeq lr
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m_m68k_write8_misc:
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bic r2, r0, #0x1f @ most commonly we get i/o port write,
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cmp r2, #0xa10000 @ so check for it first
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bne m_write8_misc2
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m_write8_io:
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ldr r2, =PicoOpt
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and r0, r0, #0x1e
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ldr r2, [r2]
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ldr r3, =(Pico+0x22000) @ Pico.ioports
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tst r2, #0x20 @ 6 button pad?
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streqb r1, [r3, r0, lsr #1]
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bxeq lr
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cmp r0, #2
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cmpne r0, #4
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bne m_write8_io_done @ not likely to happen
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add r2, r3, #0x200 @ Pico+0x22200
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mov r12,#0
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cmp r0, #2
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streqb r12,[r2,#0x18]
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strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0
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tst r1, #0x40 @ TH
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beq m_write8_io_done
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ldrb r12,[r3, r0, lsr #1]
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tst r12,#0x40
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bne m_write8_io_done
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cmp r0, #2
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ldreqb r12,[r2,#0x0a]
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ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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add r12,r12,#1
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streqb r12,[r2,#0x0a]
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strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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m_write8_io_done:
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strb r1, [r3, r0, lsr #1]
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bx lr
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m_write8_misc2:
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and r2, r0, #0xff0000
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cmp r2, #0xa00000 @ z80 area?
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bne m_write8_not_z80
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tst r0, #0x4000
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bne m_write8_z80_not_ram
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ldr r3, =(Pico+0x20000) @ Pico.zram
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add r2, r3, #0x02200 @ Pico+0x22200
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ldrb r2, [r2, #9] @ Pico.m.z80Run
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bic r0, r0, #0xff0000
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bic r0, r0, #0x00e000
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tst r2, #1
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streqb r1, [r3, r0] @ zram
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bx lr
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m_write8_z80_not_ram:
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and r2, r0, #0x6000
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cmp r2, #0x4000
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bne m_write8_z80_not_ym2612
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ldr r2, =PicoOpt
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and r0, r0, #3
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ldr r2, [r2]
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tst r2, #1
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bxeq lr
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stmfd sp!,{lr}
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.if EXTERNAL_YM2612
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tst r2, #0x200
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ldreq r2, =YM2612Write_
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ldrne r2, =YM2612Write_940
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mov lr, pc
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bx r2
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.else
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bl YM2612Write_
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.endif
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ldr r2, =emustatus
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ldmfd sp!,{lr}
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ldr r1, [r2]
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orr r1, r0, r2
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str r1, [r2] @ emustatus|=YM2612Write(a&3, d);
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bx lr
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m_write8_z80_not_ym2612: @ not too likely
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mov r2, r0, lsl #17
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bic r2, r2, #6<<17
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mov r3, #0x7f00
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orr r3, r3, #0x0011
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cmp r3, r2, lsr #17 @ psg @ z80 area?
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beq m_write8_psg
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and r2, r0, #0x7f00
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cmp r2, #0x6000 @ bank register?
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bxne lr @ invalid write
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m_write8_z80_bank_reg:
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ldr r3, =(Pico+0x22208) @ Pico.m
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ldrh r2, [r3, #0x0a]
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mov r1, r1, lsr #8
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orr r2, r1, r2, lsr #1
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bic r2, r2, #0xfe00
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strh r2, [r3, #0x0a]
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bx lr
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m_write8_not_z80:
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and r2, r0, #0xe70000
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cmp r2, #0xc00000 @ VDP area?
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bne m_write8_misc4
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and r2, r0, #0xf9
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cmp r2, #0x11
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bne m_write8_misc4
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m_write8_psg:
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ldr r2, =PicoOpt
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mov r0, r1
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ldr r2, [r2]
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tst r2, #2
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bxeq lr
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ldr r2, =SN76496Write
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bx r2
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m_write8_misc4:
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@ passthrough
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ldr r2, =OtherWrite8
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bx r2
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243
Pico/MemoryCmn.c
243
Pico/MemoryCmn.c
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@ -15,38 +15,6 @@ u32 OtherRead16End(u32 a, int realsize);
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static void OtherWrite8End(u32 a,u32 d,int realsize);
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#endif
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static int PadRead(int i)
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{
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int pad=0,value=0,TH;
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pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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TH=Pico.ioports[i+1]&0x40;
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if(PicoOpt & 0x20) { // 6 button gamepad enabled
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int phase = Pico.m.padTHPhase[i];
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if(phase == 2 && !TH) {
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value=(pad&0xc0)>>2; // ?0SA 0000
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goto end;
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} else if(phase == 3 && TH) {
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value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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goto end;
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} else if(phase == 3 && !TH) {
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value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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goto end;
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}
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}
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if(TH) value=(pad&0x3f); // ?1CB RLDU
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else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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end:
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// orr the bits, which are set as output
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value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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return value; // will mirror later
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}
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#ifndef _ASM_MEMORY_C
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static
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@ -78,42 +46,12 @@ u8 z80Read8(u32 a)
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return Pico.zram[a];
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}
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#ifndef _ASM_MEMORY_C
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static
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#endif
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u32 OtherRead16(u32 a, int realsize)
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u32 z80ReadBusReq(void)
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{
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u32 d=0;
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if ((a&0xff0000)==0xa00000) {
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if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled
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if(PicoOpt&1) d=YM2612Read();
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else d=Pico.m.rotate++&3;
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dprintf("read ym2612: %04x", d);
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goto end;
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}
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d=0xffff;
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goto end;
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}
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if ((a&0xffffe0)==0xa10000) { // I/O ports
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a=(a>>1)&0xf;
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switch(a) {
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case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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}
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d|=d<<8;
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goto end;
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}
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// |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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if (a==0xa11100) { // z80 busreq
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d=Pico.m.z80Run&1;
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#if 1
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u32 d=Pico.m.z80Run&1;
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if (!d) {
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// needed by buggy Terminator (Sega CD)
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int stop_before = SekCyclesDone() - z80stopCycle;
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@ -121,51 +59,15 @@ u32 OtherRead16(u32 a, int realsize)
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if (stop_before > 0 && stop_before <= 32) // Gens uses 16 here
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d = 1; // bus not yet available
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}
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#endif
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d=(d<<8)|0x8000|Pico.m.rotate++;
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dprintf("get_zrun: %04x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), SekPc);
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goto end;
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}
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#ifndef _ASM_MEMORY_C
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if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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#endif
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d = OtherRead16End(a, realsize);
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end:
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return d;
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// |=0x80 for Shadow of the Beast & Super Offroad
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return d|0x80;
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}
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//extern UINT32 mz80GetRegisterValue(void *, UINT32);
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#ifndef _ASM_CD_MEMORY_C
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#ifndef _ASM_MEMORY_C
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static
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#endif
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void OtherWrite8(u32 a,u32 d,int realsize)
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void z80WriteBusReq(u32 d)
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{
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if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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if ((a&0xffffe0)==0xa10000) { // I/O ports
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a=(a>>1)&0xf;
|
||||
// 6 button gamepad: if TH went from 0 to 1, gamepad changes state
|
||||
if(PicoOpt&0x20) {
|
||||
if(a==1) {
|
||||
Pico.m.padDelay[0] = 0;
|
||||
if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
|
||||
}
|
||||
else if(a==2) {
|
||||
Pico.m.padDelay[1] = 0;
|
||||
if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
|
||||
}
|
||||
}
|
||||
Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
|
||||
return;
|
||||
}
|
||||
if (a==0xa11100) {
|
||||
//int lineCycles=(488-SekCyclesLeft)&0x1ff;
|
||||
d&=1; d^=1;
|
||||
if(!d) {
|
||||
// this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
|
||||
|
|
@ -186,40 +88,59 @@ void OtherWrite8(u32 a,u32 d,int realsize)
|
|||
//if(Pico.m.scanline != -1)
|
||||
}
|
||||
dprintf("set_zrun: %02x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), /*mz80GetRegisterValue(NULL, 0),*/ SekPc);
|
||||
Pico.m.z80Run=(u8)d; return;
|
||||
}
|
||||
if (a==0xa11200) {
|
||||
dprintf("write z80Reset: %02x", d);
|
||||
if(!(d&1)) z80_reset();
|
||||
return;
|
||||
}
|
||||
|
||||
if ((a&0xff7f00)==0xa06000) // Z80 BANK register
|
||||
{
|
||||
Pico.m.z80_bank68k>>=1;
|
||||
Pico.m.z80_bank68k|=(d&1)<<8;
|
||||
Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
|
||||
return;
|
||||
}
|
||||
|
||||
if ((a&0xe700e0)==0xc00000) {
|
||||
PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
|
||||
return;
|
||||
}
|
||||
|
||||
OtherWrite8End(a, d, realsize);
|
||||
Pico.m.z80Run=(u8)d;
|
||||
}
|
||||
|
||||
|
||||
#ifndef _ASM_CD_MEMORY_C
|
||||
#ifndef _ASM_MEMORY_C
|
||||
static
|
||||
#endif
|
||||
void OtherWrite16(u32 a,u32 d)
|
||||
u32 OtherRead16(u32 a, int realsize)
|
||||
{
|
||||
if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
|
||||
if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
|
||||
u32 d=0;
|
||||
|
||||
if ((a&0xffffe0)==0xa10000) { // I/O ports
|
||||
a=(a>>1)&0xf;
|
||||
switch(a) {
|
||||
case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
|
||||
case 1: d=PadRead(0); break;
|
||||
case 2: d=PadRead(1); break;
|
||||
default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
|
||||
}
|
||||
d|=d<<8;
|
||||
goto end;
|
||||
}
|
||||
|
||||
// |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
|
||||
if (a==0xa11100) { // z80 busreq
|
||||
d=(z80ReadBusReq()<<8)|Pico.m.rotate++;
|
||||
dprintf("get_zrun: %04x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), SekPc);
|
||||
goto end;
|
||||
}
|
||||
|
||||
if ((a&0xff0000)==0xa00000) {
|
||||
if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
|
||||
if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled
|
||||
if(PicoOpt&1) d=YM2612Read();
|
||||
else d=Pico.m.rotate++&3;
|
||||
dprintf("read ym2612: %04x", d);
|
||||
goto end;
|
||||
}
|
||||
d=0xffff;
|
||||
goto end;
|
||||
}
|
||||
|
||||
#ifndef _ASM_MEMORY_C
|
||||
if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
|
||||
#endif
|
||||
|
||||
d = OtherRead16End(a, realsize);
|
||||
|
||||
end:
|
||||
return d;
|
||||
}
|
||||
|
||||
static void IoWrite8(u32 a, u32 d)
|
||||
{
|
||||
a=(a>>1)&0xf;
|
||||
// 6 button gamepad: if TH went from 0 to 1, gamepad changes state
|
||||
if(PicoOpt&0x20) {
|
||||
|
|
@ -233,13 +154,65 @@ void OtherWrite16(u32 a,u32 d)
|
|||
}
|
||||
}
|
||||
Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
|
||||
}
|
||||
|
||||
#ifndef _ASM_CD_MEMORY_C
|
||||
static
|
||||
#endif
|
||||
void OtherWrite8(u32 a,u32 d)
|
||||
{
|
||||
#ifndef _ASM_MEMORY_C
|
||||
if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
|
||||
if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
|
||||
if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
|
||||
if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
|
||||
#endif
|
||||
if (a==0xa11100) { z80WriteBusReq(d); return; }
|
||||
if (a==0xa11200) {
|
||||
dprintf("write z80Reset: %02x", d);
|
||||
if(!(d&1)) z80_reset();
|
||||
return;
|
||||
}
|
||||
#ifndef _ASM_MEMORY_C
|
||||
if ((a&0xff7f00)==0xa06000) // Z80 BANK register
|
||||
{
|
||||
Pico.m.z80_bank68k>>=1;
|
||||
Pico.m.z80_bank68k|=(d&1)<<8;
|
||||
Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
if ((a&0xe700e0)==0xc00000) {
|
||||
PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
|
||||
return;
|
||||
}
|
||||
if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
|
||||
if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
|
||||
|
||||
OtherWrite8(a, d>>8, 16);
|
||||
OtherWrite8(a+1,d&0xff, 16);
|
||||
OtherWrite8End(a, d, 8);
|
||||
}
|
||||
|
||||
|
||||
#ifndef _ASM_CD_MEMORY_C
|
||||
static
|
||||
#endif
|
||||
void OtherWrite16(u32 a,u32 d)
|
||||
{
|
||||
if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
|
||||
if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
|
||||
if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
|
||||
if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
|
||||
if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
|
||||
if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
|
||||
if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound (??)
|
||||
if ((a&0xff7f00)==0xa06000) // Z80 BANK register
|
||||
{
|
||||
Pico.m.z80_bank68k>>=1;
|
||||
Pico.m.z80_bank68k|=(d&1)<<8;
|
||||
Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
|
||||
return;
|
||||
}
|
||||
|
||||
OtherWrite8End(a, d>>8, 16);
|
||||
OtherWrite8End(a+1,d&0xff, 16);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -154,17 +154,17 @@ struct PicoMisc
|
|||
{
|
||||
unsigned char rotate;
|
||||
unsigned char z80Run;
|
||||
unsigned char padTHPhase[2]; // phase of gamepad TH switches
|
||||
short scanline; // 0 to 261||311; -1 in fast mode
|
||||
char dirtyPal; // Is the palette dirty (1 - change @ this frame, 2 - some time before)
|
||||
unsigned char hardware; // Hardware value for country
|
||||
unsigned char pal; // 1=PAL 0=NTSC
|
||||
unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches
|
||||
short scanline; // 04 0 to 261||311; -1 in fast mode
|
||||
char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)
|
||||
unsigned char hardware; // 07 Hardware value for country
|
||||
unsigned char pal; // 08 1=PAL 0=NTSC
|
||||
unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)
|
||||
unsigned short z80_bank68k;
|
||||
unsigned short z80_bank68k; // 0a
|
||||
unsigned short z80_lastaddr; // this is for Z80 faking
|
||||
unsigned char z80_fakeval;
|
||||
unsigned char pad0;
|
||||
unsigned char padDelay[2]; // gamepad phase time outs, so we count a delay
|
||||
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay
|
||||
unsigned short sram_addr; // EEPROM address register
|
||||
unsigned char sram_cycle; // EEPROM SRAM cycle number
|
||||
unsigned char sram_slave; // EEPROM slave word for X24C02 and better SRAMs
|
||||
|
|
@ -297,6 +297,7 @@ PICO_INTERNAL int PicoInitPc(unsigned int pc);
|
|||
PICO_INTERNAL_ASM unsigned int CPU_CALL PicoRead32(unsigned int a);
|
||||
PICO_INTERNAL void PicoMemSetup(void);
|
||||
PICO_INTERNAL_ASM void PicoMemReset(void);
|
||||
PICO_INTERNAL int PadRead(int i);
|
||||
PICO_INTERNAL unsigned char z80_read(unsigned short a);
|
||||
PICO_INTERNAL unsigned short z80_read16(unsigned short a);
|
||||
PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);
|
||||
|
|
|
|||
|
|
@ -139,6 +139,8 @@ m_s68k_decode_write_table:
|
|||
.extern PicoCpuS68k
|
||||
.extern s68k_poll_detect
|
||||
.extern SN76496Write
|
||||
.extern m_m68k_read8_misc
|
||||
.extern m_m68k_write8_misc
|
||||
|
||||
|
||||
@ r0=reg3, r1-r3=temp
|
||||
|
|
@ -502,7 +504,7 @@ m_m68k_read8_system_io:
|
|||
bic r2, r0, #0xfe0000
|
||||
bic r2, r2, #0x3f
|
||||
cmp r2, #0x012000
|
||||
bne m_m68k_read8_misc
|
||||
bne m_m68k_read8_misc @ now from Pico/Memory.s
|
||||
|
||||
ldr r1, =(Pico+0x22200)
|
||||
and r0, r0, #0x3f
|
||||
|
|
@ -588,7 +590,7 @@ m_m68k_read8_hi:
|
|||
ldrb r0, [r1, r0]
|
||||
bx lr
|
||||
|
||||
|
||||
/*
|
||||
m_m68k_read8_misc:
|
||||
bic r2, r0, #0x00ff
|
||||
bic r2, r2, #0xbf00
|
||||
|
|
@ -604,7 +606,7 @@ m_m68k_read8_misc:
|
|||
tst r1, #1
|
||||
moveq r0, r0, lsr #8
|
||||
bx lr
|
||||
|
||||
*/
|
||||
|
||||
m_m68k_read8_vdp:
|
||||
tst r0, #0x70000
|
||||
|
|
@ -1116,7 +1118,8 @@ m_m68k_write8_system_io:
|
|||
cmp r2, #0x012000
|
||||
beq m68k_reg_write8
|
||||
mov r2, #8
|
||||
b OtherWrite8
|
||||
@ b OtherWrite8
|
||||
b m_m68k_write8_misc
|
||||
|
||||
|
||||
m_m68k_write8_vdp:
|
||||
|
|
|
|||
|
|
@ -116,11 +116,10 @@ DrZ80Ver: .long 0x0001
|
|||
ldr r1,=PicoOpt
|
||||
ldr r1,[r1]
|
||||
tst r1,#0x200
|
||||
bne 10f
|
||||
bl YM2612Read_
|
||||
ldmfd sp!,{r3,r12,pc}
|
||||
10:
|
||||
bl YM2612Read_940
|
||||
ldrne r2, =YM2612Read_940
|
||||
ldreq r2, =YM2612Read_
|
||||
mov lr,pc
|
||||
bx r2
|
||||
.else
|
||||
bl YM2612Read_
|
||||
.endif
|
||||
|
|
@ -133,12 +132,10 @@ DrZ80Ver: .long 0x0001
|
|||
ldr r0,=PicoOpt
|
||||
ldr r0,[r0]
|
||||
tst r0,#0x200
|
||||
bne 10f
|
||||
bl YM2612Read_
|
||||
orr r0,r0,r0,lsl #8
|
||||
ldmfd sp!,{r3,r12,pc}
|
||||
10:
|
||||
bl YM2612Read_940
|
||||
ldrne r2, =YM2612Read_940
|
||||
ldreq r2, =YM2612Read_
|
||||
mov lr,pc
|
||||
bx r2
|
||||
orr r0,r0,r0,lsl #8
|
||||
.else
|
||||
bl YM2612Read_
|
||||
|
|
|
|||
|
|
@ -74,6 +74,9 @@ PicoDrive : $(OBJS) ../gp2x/helix/helix_mp3_x86.a
|
|||
@$(GCC) $(COPT) $^ $(LDFLAGS) -lm -lpng -Wl,-Map=PicoDrive.map -o $@
|
||||
|
||||
|
||||
../../cpu/musashi/m68kops.c :
|
||||
@make -C ../../cpu/musashi
|
||||
|
||||
../../cpu/mz80/mz80.o : ../../cpu/mz80/mz80.asm
|
||||
@echo $@
|
||||
@nasm -f elf $< -o $@
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue