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32x: drc: more wip, ARM untested
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@828 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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3863edbd9d
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3 changed files with 240 additions and 57 deletions
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@ -40,6 +40,8 @@
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#define A_COND_LT 0xb
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#define A_COND_GT 0xc
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#define A_COND_LE 0xd
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#define A_COND_CS A_COND_HS
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#define A_COND_CC A_COND_LO
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/* unified conditions */
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#define DCOND_EQ A_COND_EQ
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@ -56,8 +58,6 @@
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#define DCOND_LE A_COND_LE
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#define DCOND_VS A_COND_VS
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#define DCOND_VC A_COND_VC
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#define DCOND_CS A_COND_HS
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#define DCOND_CC A_COND_LO
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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@ -225,8 +225,6 @@ static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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if (op == A_OP_MOV)
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rn = 0;
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else if (op == A_OP_TST || op == A_OP_TEQ)
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rd = 0;
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else if (imm == 0)
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return;
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@ -244,6 +242,14 @@ static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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}
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}
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// test op
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#define emith_top_imm(cond, op, r, imm) { \
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u32 ror2, v; \
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for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
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ror2--; \
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EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
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}
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#define is_offset_24(val) \
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((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
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@ -350,9 +356,12 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_or_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
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// note: use 8bit imm only
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// note: only use 8bit imm for these
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#define emith_tst_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_TST, r, imm)
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emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_top_imm(A_COND_AL, A_OP_CMP, r, imm)
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#define emith_subf_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
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@ -375,12 +384,34 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_lsr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
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#define emith_ror(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
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#define emith_lslf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
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#define emith_lsrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
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#define emith_asrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
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// note: only C flag updated correctly
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#define emith_rolf(d, s, cnt) { \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
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/* we don't have ROL so we shift to get the right carry */ \
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EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
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}
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#define emith_rorf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
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#define emith_rolcf(d) \
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emith_adcf_r_r(d, d)
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#define emith_rorcf(d) \
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EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
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#define emith_mul(d, s1, s2) { \
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if ((d) != (s1)) /* rd != rm limitation */ \
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EOP_MUL(d, s1, s2); \
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@ -483,3 +514,19 @@ static int emith_xbranch(int cond, void *target, int is_call)
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rcache_free_tmp(tmp); \
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}
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#define emith_write_sr(srcr) { \
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int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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emith_lsr(srr, srr, 12); \
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emith_or_r_r_r_lsl(srr, srr, srcr, 20); \
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emith_ror(srr, srr, 20); \
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}
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#define emith_carry_to_t(srr, is_sub) { \
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if (is_sub) { /* has inverted C on ARM */ \
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emith_or_r_imm_c(A_COND_CC, srr, 1); \
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emith_bic_r_imm_c(A_COND_CS, srr, 1); \
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} else { \
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emith_or_r_imm_c(A_COND_CS, srr, 1); \
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emith_bic_r_imm_c(A_COND_CC, srr, 1); \
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} \
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}
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@ -39,8 +39,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define DCOND_LT IOP_JL // less (signed)
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#define DCOND_VS IOP_JO // oVerflow Set
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#define DCOND_VC IOP_JNO // oVerflow Clear
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#define DCOND_CS IOP_JB // Carry Set
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#define DCOND_CC IOP_JAE // Carry Clear
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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@ -141,7 +139,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(imm, u32); \
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}
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// 2 - adc, 3 - sbb, 6 - xor, 7 - cmp
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// 2 - adc, 3 - sbb, 6 - xor
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#define emith_add_r_imm(r, imm) \
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emith_arith_r_imm(0, r, imm)
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@ -154,6 +152,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_sub_r_imm(r, imm) \
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emith_arith_r_imm(5, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_arith_r_imm(7, r, imm)
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#define emith_tst_r_imm(r, imm) { \
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EMIT_OP_MODRM(0xf7, 3, 0, r); \
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EMIT(imm, u32); \
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@ -201,6 +202,18 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_asr(d, s, cnt) \
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emith_shift(7, d, s, cnt)
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#define emith_rol(d, s, cnt) \
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emith_shift(0, d, s, cnt)
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#define emith_ror(d, s, cnt) \
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emith_shift(1, d, s, cnt)
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#define emith_rolc(r) \
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EMIT_OP_MODRM(0xd1, 3, 2, r)
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#define emith_rorc(r) \
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EMIT_OP_MODRM(0xd1, 3, 3, r)
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// misc
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#define emith_push(r) \
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EMIT_OP(0x50 + (r))
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@ -280,9 +293,13 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_adcf_r_r emith_adc_r_r
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#define emith_sbcf_r_r emith_sbc_r_r
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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#define emith_asrf emith_asr
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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#define emith_asrf emith_asr
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#define emith_rolf emith_rol
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#define emith_rorf emith_ror
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#define emith_rolcf emith_rolc
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#define emith_rorcf emith_rorc
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// XXX: offs is 8bit only
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#define emith_ctx_read(r, offs) { \
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@ -368,3 +385,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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rcache_free_tmp(tmp); \
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}
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#define emith_write_sr(srcr) { \
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int tmp = rcache_get_tmp(); \
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int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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emith_clear_msb(tmp, srcr, 20); \
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emith_bic_r_imm(srr, 0xfff); \
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emith_or_r_r(srr, tmp); \
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rcache_free_tmp(tmp); \
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}
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#define emith_carry_to_t(srr, is_sub) { \
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int tmp = rcache_get_tmp(); \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, tmp); /* SETC */ \
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emith_bic_r_imm(srr, 1); \
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EMIT_OP_MODRM(0x08, 3, tmp, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp); \
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}
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