mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: drc: more wip, ARM untested
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@828 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
3863edbd9d
commit
ed8cf79be8
3 changed files with 240 additions and 57 deletions
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@ -40,6 +40,8 @@
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#define A_COND_LT 0xb
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#define A_COND_GT 0xc
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#define A_COND_LE 0xd
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#define A_COND_CS A_COND_HS
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#define A_COND_CC A_COND_LO
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/* unified conditions */
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#define DCOND_EQ A_COND_EQ
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@ -56,8 +58,6 @@
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#define DCOND_LE A_COND_LE
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#define DCOND_VS A_COND_VS
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#define DCOND_VC A_COND_VC
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#define DCOND_CS A_COND_HS
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#define DCOND_CC A_COND_LO
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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@ -225,8 +225,6 @@ static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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if (op == A_OP_MOV)
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rn = 0;
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else if (op == A_OP_TST || op == A_OP_TEQ)
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rd = 0;
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else if (imm == 0)
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return;
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@ -244,6 +242,14 @@ static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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}
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}
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// test op
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#define emith_top_imm(cond, op, r, imm) { \
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u32 ror2, v; \
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for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
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ror2--; \
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EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
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}
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#define is_offset_24(val) \
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((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
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@ -350,9 +356,12 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_or_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
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// note: use 8bit imm only
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// note: only use 8bit imm for these
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#define emith_tst_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_TST, r, imm)
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emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_top_imm(A_COND_AL, A_OP_CMP, r, imm)
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#define emith_subf_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
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@ -375,12 +384,34 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_lsr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
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#define emith_ror(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
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#define emith_lslf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
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#define emith_lsrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
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#define emith_asrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
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// note: only C flag updated correctly
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#define emith_rolf(d, s, cnt) { \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
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/* we don't have ROL so we shift to get the right carry */ \
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EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
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}
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#define emith_rorf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
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#define emith_rolcf(d) \
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emith_adcf_r_r(d, d)
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#define emith_rorcf(d) \
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EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
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#define emith_mul(d, s1, s2) { \
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if ((d) != (s1)) /* rd != rm limitation */ \
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EOP_MUL(d, s1, s2); \
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@ -483,3 +514,19 @@ static int emith_xbranch(int cond, void *target, int is_call)
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rcache_free_tmp(tmp); \
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}
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#define emith_write_sr(srcr) { \
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int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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emith_lsr(srr, srr, 12); \
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emith_or_r_r_r_lsl(srr, srr, srcr, 20); \
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emith_ror(srr, srr, 20); \
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}
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#define emith_carry_to_t(srr, is_sub) { \
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if (is_sub) { /* has inverted C on ARM */ \
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emith_or_r_imm_c(A_COND_CC, srr, 1); \
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emith_bic_r_imm_c(A_COND_CS, srr, 1); \
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} else { \
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emith_or_r_imm_c(A_COND_CS, srr, 1); \
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emith_bic_r_imm_c(A_COND_CC, srr, 1); \
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} \
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}
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@ -39,8 +39,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define DCOND_LT IOP_JL // less (signed)
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#define DCOND_VS IOP_JO // oVerflow Set
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#define DCOND_VC IOP_JNO // oVerflow Clear
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#define DCOND_CS IOP_JB // Carry Set
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#define DCOND_CC IOP_JAE // Carry Clear
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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@ -141,7 +139,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(imm, u32); \
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}
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// 2 - adc, 3 - sbb, 6 - xor, 7 - cmp
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// 2 - adc, 3 - sbb, 6 - xor
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#define emith_add_r_imm(r, imm) \
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emith_arith_r_imm(0, r, imm)
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@ -154,6 +152,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_sub_r_imm(r, imm) \
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emith_arith_r_imm(5, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_arith_r_imm(7, r, imm)
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#define emith_tst_r_imm(r, imm) { \
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EMIT_OP_MODRM(0xf7, 3, 0, r); \
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EMIT(imm, u32); \
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@ -201,6 +202,18 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_asr(d, s, cnt) \
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emith_shift(7, d, s, cnt)
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#define emith_rol(d, s, cnt) \
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emith_shift(0, d, s, cnt)
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#define emith_ror(d, s, cnt) \
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emith_shift(1, d, s, cnt)
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#define emith_rolc(r) \
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EMIT_OP_MODRM(0xd1, 3, 2, r)
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#define emith_rorc(r) \
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EMIT_OP_MODRM(0xd1, 3, 3, r)
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// misc
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#define emith_push(r) \
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EMIT_OP(0x50 + (r))
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@ -283,6 +296,10 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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#define emith_asrf emith_asr
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#define emith_rolf emith_rol
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#define emith_rorf emith_ror
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#define emith_rolcf emith_rolc
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#define emith_rorcf emith_rorc
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// XXX: offs is 8bit only
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#define emith_ctx_read(r, offs) { \
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@ -368,3 +385,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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rcache_free_tmp(tmp); \
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}
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#define emith_write_sr(srcr) { \
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int tmp = rcache_get_tmp(); \
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int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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emith_clear_msb(tmp, srcr, 20); \
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emith_bic_r_imm(srr, 0xfff); \
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emith_or_r_r(srr, tmp); \
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rcache_free_tmp(tmp); \
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}
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#define emith_carry_to_t(srr, is_sub) { \
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int tmp = rcache_get_tmp(); \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, tmp); /* SETC */ \
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emith_bic_r_imm(srr, 1); \
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EMIT_OP_MODRM(0x08, 3, tmp, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp); \
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}
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@ -512,8 +512,6 @@ SWAP.B Rm,Rn 0110nnnnmmmm1000
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SWAP.W Rm,Rn 0110nnnnmmmm1001
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ADD #imm,Rn 0111nnnniiiiiiii
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CMP/EQ #imm,R0 10001000iiiiiiii
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CMP/PZ Rn 0100nnnn00010001
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CMP/PL Rn 0100nnnn00010101
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EXTS.B Rm,Rn 0110nnnnmmmm1110
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EXTS.W Rm,Rn 0110nnnnmmmm1111
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EXTU.B Rm,Rn 0110nnnnmmmm1100
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@ -531,12 +529,6 @@ TST #imm,R0 11001000iiiiiiii
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TST.B #imm,@(R0,GBR) 11001100iiiiiiii
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XOR #imm,R0 11001010iiiiiiii
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XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
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ROTL Rn 0100nnnn00000100
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ROTR Rn 0100nnnn00000101
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ROTCL Rn 0100nnnn00100100
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ROTCR Rn 0100nnnn00100101
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SHAR Rn 0100nnnn00100001
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SHLR Rn 0100nnnn00000001
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SHLL2 Rn 0100nnnn00001000
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SHLR2 Rn 0100nnnn00001001
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SHLL8 Rn 0100nnnn00011000
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@ -545,20 +537,9 @@ SHLL16 Rn 0100nnnn00101000
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SHLR16 Rn 0100nnnn00101001
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LDC Rm,GBR 0100mmmm00011110
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LDC Rm,VBR 0100mmmm00101110
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LDC.L @Rm+,GBR 0100mmmm00010111
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LDC.L @Rm+,VBR 0100mmmm00100111
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LDS Rm,MACH 0100mmmm00001010
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LDS Rm,MACL 0100mmmm00011010
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LDS Rm,PR 0100mmmm00101010
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LDS.L @Rm+,MACH 0100mmmm00000110
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LDS.L @Rm+,MACL 0100mmmm00010110
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LDS.L @Rm+,PR 0100mmmm00100110
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STC.L SR,@–Rn 0100nnnn00000011
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STC.L GBR,@–Rn 0100nnnn00010011
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STC.L VBR,@–Rn 0100nnnn00100011
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STS.L MACH,@–Rn 0100nnnn00000010
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STS.L MACL,@–Rn 0100nnnn00010010
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STS.L PR,@–Rn 0100nnnn00100010
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TRAPA #imm 11000011iiiiiiii
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*/
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@ -578,8 +559,8 @@ TRAPA #imm 11000011iiiiiiii
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#define GET_Rn() \
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((op >> 8) & 0x0f)
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#define CHECK_FX_GT_3() \
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if (GET_Fx() > 3) \
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#define CHECK_FX_LT(n) \
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if (GET_Fx() < n) \
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goto default_
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static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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@ -670,8 +651,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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default:
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goto default_;
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}
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tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
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emith_move_r_r(tmp, tmp2);
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tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
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emith_move_r_r(tmp, tmp3);
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if (tmp2 == SHR_SR)
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emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0
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goto end_op;
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case 0x03:
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CHECK_UNHANDLED_BITS(0xd0);
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@ -751,17 +734,18 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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switch (GET_Fx())
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{
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case 0: // STS MACH,Rn 0000nnnn00001010
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tmp2 = rcache_get_reg(SHR_MACH, RC_GR_READ);
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tmp2 = SHR_MACH;
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break;
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case 1: // STS MACL,Rn 0000nnnn00011010
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tmp2 = rcache_get_reg(SHR_MACL, RC_GR_READ);
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tmp2 = SHR_MACL;
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break;
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case 2: // STS PR,Rn 0000nnnn00101010
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tmp2 = rcache_get_reg(SHR_PR, RC_GR_READ);
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tmp2 = SHR_PR;
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break;
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default:
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goto default_;
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}
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tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
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emith_move_r_r(tmp, tmp2);
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goto end_op;
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case 0x0b:
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@ -1013,20 +997,12 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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if (op & 4) { // adc
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emith_set_carry(tmp3);
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emith_adcf_r_r(tmp, tmp2);
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tmp = DCOND_CS; // set condition
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tmp2 = DCOND_CC; // clear condition
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emith_carry_to_t(tmp3, 0);
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} else {
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emith_set_carry_sub(tmp3);
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emith_sbcf_r_r(tmp, tmp2);
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tmp = DCOND_LO; // using LO/HS instead of CS/CC
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tmp2 = DCOND_HS; // due to ARM target..
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emith_carry_to_t(tmp3, 1);
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}
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EMITH_SJMP_START(tmp);
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emith_bic_r_imm_c(tmp2, tmp3, T);
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EMITH_SJMP_END(tmp);
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EMITH_SJMP_START(tmp2);
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emith_or_r_imm_c(tmp, tmp3, T);
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EMITH_SJMP_END(tmp2);
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goto end_op;
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case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
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case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
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@ -1063,11 +1039,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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case 2: // SHAL Rn 0100nnnn00100000
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp2, T);
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emith_lslf(tmp, tmp, 1);
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EMITH_SJMP_START(DCOND_CC);
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emith_or_r_imm_c(DCOND_CS, tmp2, T);
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EMITH_SJMP_END(DCOND_CC);
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emith_carry_to_t(tmp2, 0);
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goto end_op;
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case 1: // DT Rn 0100nnnn00010000
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if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
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@ -1084,12 +1057,139 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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goto end_op;
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}
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goto default_;
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case 0x01:
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switch (GET_Fx())
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{
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case 0: // SHLR Rn 0100nnnn00000001
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case 2: // SHAR Rn 0100nnnn00100001
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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if (op & 0x20) {
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emith_asrf(tmp, tmp, 1);
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} else
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emith_lsrf(tmp, tmp, 1);
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emith_carry_to_t(tmp2, 0);
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goto end_op;
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case 1: // CMP/PZ Rn 0100nnnn00010001
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp2, T);
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emith_cmp_r_imm(tmp, 0);
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EMITH_SJMP_START(DCOND_LT);
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emith_or_r_imm_c(DCOND_GE, tmp2, T);
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EMITH_SJMP_END(DCOND_LT);
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goto end_op;
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}
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goto default_;
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case 0x02:
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case 0x03:
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switch (op & 0x3f)
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{
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case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
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tmp = SHR_MACH;
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break;
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case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
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tmp = SHR_MACL;
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break;
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case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
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tmp = SHR_PR;
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break;
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case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
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tmp = SHR_SR;
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break;
|
||||
case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
|
||||
tmp = SHR_GBR;
|
||||
break;
|
||||
case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
|
||||
tmp = SHR_VBR;
|
||||
break;
|
||||
default:
|
||||
goto default_;
|
||||
}
|
||||
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
emith_sub_r_imm(tmp2, 4);
|
||||
rcache_clean();
|
||||
rcache_get_reg_arg(0, GET_Rn());
|
||||
tmp3 = rcache_get_reg_arg(1, tmp);
|
||||
if (tmp == SHR_SR)
|
||||
emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0
|
||||
emit_memhandler_write(2);
|
||||
goto end_op;
|
||||
case 0x04:
|
||||
case 0x05:
|
||||
switch (op & 0x3f)
|
||||
{
|
||||
case 0x04: // ROTL Rn 0100nnnn00000100
|
||||
case 0x05: // ROTR Rn 0100nnnn00000101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
if (op & 1) {
|
||||
emith_rorf(tmp, tmp, 1);
|
||||
} else
|
||||
emith_rolf(tmp, tmp, 1);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
goto end_op;
|
||||
case 0x24: // ROTCL Rn 0100nnnn00100100
|
||||
case 0x25: // ROTCR Rn 0100nnnn00100101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry(tmp2);
|
||||
if (op & 1) {
|
||||
emith_rorcf(tmp);
|
||||
} else
|
||||
emith_rolcf(tmp);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
goto end_op;
|
||||
case 0x15: // CMP/PL Rn 0100nnnn00010101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
emith_cmp_r_imm(tmp, 0);
|
||||
EMITH_SJMP_START(DCOND_LE);
|
||||
emith_or_r_imm_c(DCOND_GT, tmp2, T);
|
||||
EMITH_SJMP_END(DCOND_LE);
|
||||
goto end_op;
|
||||
}
|
||||
goto default_;
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
if ((op & 0xf0) != 0)
|
||||
switch (op & 0x3f)
|
||||
{
|
||||
case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
|
||||
tmp = SHR_MACH;
|
||||
break;
|
||||
case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
|
||||
tmp = SHR_MACL;
|
||||
break;
|
||||
case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
|
||||
tmp = SHR_PR;
|
||||
break;
|
||||
case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
|
||||
tmp = SHR_SR;
|
||||
break;
|
||||
case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
|
||||
tmp = SHR_GBR;
|
||||
break;
|
||||
case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
|
||||
tmp = SHR_VBR;
|
||||
break;
|
||||
default:
|
||||
goto default_;
|
||||
// LDC.L @Rm+,SR 0100mmmm00000111
|
||||
}
|
||||
rcache_clean();
|
||||
rcache_get_reg_arg(0, GET_Rn());
|
||||
tmp2 = emit_memhandler_read(2);
|
||||
if (tmp == SHR_SR) {
|
||||
emith_write_sr(tmp2);
|
||||
test_irq = 1;
|
||||
goto default_;
|
||||
} else {
|
||||
tmp = rcache_get_reg(tmp, RC_GR_WRITE);
|
||||
emith_move_r_r(tmp, tmp2);
|
||||
}
|
||||
rcache_free_tmp(tmp2);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
emith_add_r_imm(tmp, 4);
|
||||
goto end_op;
|
||||
case 0x0b:
|
||||
if ((op & 0xd0) != 0)
|
||||
goto default_;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue