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https://github.com/RaySollium99/picodrive.git
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svp compiler: some PMAR handling, code detection
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@377 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
0e4d7ba5f4
commit
ede7220f67
4 changed files with 250 additions and 62 deletions
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@ -12,7 +12,7 @@ static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x08aa
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#define DUMP_BLOCK 0x084a
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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@ -533,6 +533,10 @@ static struct
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{
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ssp_reg_t gr[8];
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unsigned char r[8];
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unsigned int pmac_read[5];
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unsigned int pmac_write[5];
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unsigned int pmc;
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unsigned int emu_status;
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} known_regs;
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#define KRREG_X (1 << SSP_X)
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@ -545,12 +549,23 @@ static struct
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#define KRREG_PR0 (1 << 8)
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#define KRREG_PR4 (1 << 12)
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#define KRREG_AL (1 << 16)
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#define KRREG_PMC (1 << 19) /* PMx are always dirty */
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#define KRREG_PM0R (1 << 20)
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#define KRREG_PM1R (1 << 21)
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#define KRREG_PM2R (1 << 22)
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#define KRREG_PM3R (1 << 23)
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#define KRREG_PM4R (1 << 24)
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#define KRREG_PM0W (1 << 25)
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#define KRREG_PM1W (1 << 26)
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#define KRREG_PM2W (1 << 27)
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#define KRREG_PM3W (1 << 28)
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#define KRREG_PM4W (1 << 29)
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/* bitfield of known register values */
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static u32 known_regb = 0;
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/* known vals, which need to be flushed
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* (only ST, P, r0-r7)
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* (only ST, P, r0-r7, PMxR, PMxW)
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* ST means flags are being held in ARM PSR
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* P means that it needs to be recalculated
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*/
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@ -579,7 +594,8 @@ static void hostreg_sspreg_changed(int sspreg)
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}
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#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
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#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
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#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
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static void tr_unhandled(void)
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{
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@ -694,6 +710,40 @@ static void tr_mov16_cond(int cond, int r, int val)
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hostreg_r[r] = -1;
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}
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/* trashes r0 */
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static void tr_flush_dirty_pmcrs(void)
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{
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u32 i, val = (u32)-1;
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if (!(known_regb & 0x3ff80000)) return;
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if (known_regb & KRREG_PMC) {
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val = known_regs.pmc;
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emit_mov_const(A_COND_AL, 0, val);
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EOP_STR_IMM(0,7,0x400+SSP_PMC*4);
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if (known_regs.emu_status & SSP_PMC_SET)
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printf("!! SSP_PMC_SET set on flush\n");
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}
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for (i = 0; i < 5; i++)
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{
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if (known_regb & (1 << (20+i))) {
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if (val != known_regs.pmac_read[i]) {
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val = known_regs.pmac_read[i];
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emit_mov_const(A_COND_AL, 0, val);
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}
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EOP_STR_IMM(0,7,0x454+i*4); // pmac_read
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}
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if (known_regb & (1 << (25+i))) {
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if (val != known_regs.pmac_write[i]) {
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val = known_regs.pmac_write[i];
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emit_mov_const(A_COND_AL, 0, val);
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}
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EOP_STR_IMM(0,7,0x46c+i*4); // pmac_write
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}
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}
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hostreg_r[0] = -1;
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}
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/* read bank word to r0 (upper bits zero). Thrashes r1. */
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static void tr_bank_read(int addr) /* word addr 0-0x1ff */
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{
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@ -905,6 +955,23 @@ static int tr_neg_cond(int cond)
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return 0;
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}
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static int tr_aop_ssp2arm(int op)
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{
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switch (op) {
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case 1: return A_OP_SUB;
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case 3: return A_OP_CMP;
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case 4: return A_OP_ADD;
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case 5: return A_OP_AND;
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case 6: return A_OP_ORR;
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case 7: return A_OP_EOR;
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}
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tr_unhandled();
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return 0;
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}
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// -----------------------------------------------------
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// SSP_GR0, SSP_X, SSP_Y, SSP_A,
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// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
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//@ r4: XXYY
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@ -974,6 +1041,66 @@ static void tr_P_to_r0(void)
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EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
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hostreg_r[0] = -1;
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}
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/*
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static void tr_PM0_to_r0(void)
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{
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}
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*/
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static int tr_PM4_to_r0(void)
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{
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int reg = 4;
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u32 pmcv = known_regs.pmac_read[reg];
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if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
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{
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known_regs.pmac_read[reg] = known_regs.pmc;
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known_regs.emu_status &= ~SSP_PMC_SET;
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return 0;
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}
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if (known_regb & (1 << (20+4)))
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{
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int mode = known_regs.pmac_read[reg]>>16;
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if ((mode & 0xfff0) == 0x0800)
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{
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known_regs.pmac_read[reg] += 1;
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EOP_LDR_IMM(1,7,0x488); // rom_ptr
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emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
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EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
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hostreg_r[0] = hostreg_r[1] = -1;
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}
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else if ((mode & 0x47ff) == 0x0018) // DRAM
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{
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int inc = get_inc(mode);
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ssp->pmac_read[reg] += inc;
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EOP_LDR_IMM(1,7,0x490); // dram_ptr
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emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
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EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
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if (pmcv == 0x187f03 || pmcv == 0x187f04) // wait loop detection
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{
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int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
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tr_flush_dirty_ST();
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EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
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EOP_TST_REG_SIMPLE(0,0);
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
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EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
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}
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hostreg_r[0] = hostreg_r[1] = -1;
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}
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else
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{
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tr_unhandled();
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}
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known_regs.pmc = known_regs.pmac_read[reg];
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known_regb |= KRREG_PMC;
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return 0;
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}
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return -1;
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}
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typedef void (tr_read_func)(void);
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@ -1090,26 +1217,96 @@ static void tr_mac_load_XY(int op)
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known_regb &= ~KRREG_Y;
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}
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static int tr_aop_ssp2arm(int op)
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// -----------------------------------------------------
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static const short startup_seq[] = { 0xb802, 0x4d50, 0x400 };
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static int tr_detect_startup(unsigned int op, int *pc, int imm)
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{
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switch (op) {
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case 1: return A_OP_SUB;
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case 3: return A_OP_CMP;
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case 4: return A_OP_ADD;
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case 5: return A_OP_AND;
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case 6: return A_OP_ORR;
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case 7: return A_OP_EOR;
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// ld A, PM0
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// andi 2
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// bra z=1, gloc_0800
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unsigned short *pp;
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if (op != 0x38) return 0;
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pp = PROGRAM_P(*pc);
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if (memcmp(pp, startup_seq, sizeof(startup_seq)) != 0) return 0;
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// the only place when we GPO bits are set in ST is the startup code
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// (excluding memtest, which we do not support).
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EOP_LDR_IMM(0,7,0x400+SSP_PM0*4);
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EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
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EOP_TST_IMM(0,16/2,2);
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,SSP_WAIT_PM0>>8); // orreq r1, r1, #SSP_WAIT_PM0
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // addeq r11, r11, #1024
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EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
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tr_mov16_cond(A_COND_NE, 0, 0x04040000);
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EOP_C_AM2_IMM(A_COND_NE,1,0,0,7,0,0x400+SSP_PC*4);
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hostreg_r[0] = hostreg_r[1] = -1;
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(*pc) += 3;
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return 4 | 0x10000;
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}
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static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
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{
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u32 pmcv, tmpv;
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if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
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// programming PMC:
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// ldi PMC, imm1
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// ldi PMC, imm2
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(*pc)++;
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pmcv = imm | (PROGRAM((*pc)++) << 16);
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known_regs.pmc = pmcv;
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known_regb |= KRREG_PMC;
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known_regs.emu_status |= SSP_PMC_SET;
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// check for possible reg programming
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tmpv = PROGRAM(*pc);
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if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
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{
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int is_write = (tmpv & 0xff8f) == 0x80;
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int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
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if (reg > 4) tr_unhandled();
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known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
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known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
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known_regs.emu_status &= ~SSP_PMC_SET;
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(*pc)++;
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return 5;
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}
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tr_unhandled();
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return 0;
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return 4;
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}
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static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
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static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
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{
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// ldi ST, 0
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// ldi PM0, 0
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// ldi PM0, 0
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// ldi ST, 60h
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unsigned short *pp;
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if (op != 0x0840 || imm != 0) return 0;
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pp = PROGRAM_P(*pc);
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if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
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EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
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EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
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hostreg_sspreg_changed(SSP_ST);
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known_regs.gr[SSP_ST].h = 0x60;
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known_regb |= 1 << SSP_ST;
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dirty_regb &= ~KRREG_ST;
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(*pc) += 3*2;
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return 4*2;
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}
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// -----------------------------------------------------
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static int translate_op(unsigned int op, int *pc, int imm)
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{
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u32 tmpv, tmpv2, tmpv3;
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int ret = 0;
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known_regs.gr[SSP_PC].h = *pc;
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known_regs.emu_status = 0;
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switch (op >> 9)
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{
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@ -1118,7 +1315,9 @@ static int translate_op(unsigned int op, int *pc, int imm)
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if (op == 0) { ret++; break; } // nop
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tmpv = op & 0xf; // src
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tmpv2 = (op >> 4) & 0xf; // dst
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if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO
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ret = tr_detect_startup(op, pc, imm);
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if (ret > 0) break;
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if (tmpv != 0xc && (tmpv >= 8 || tmpv2 >= 8)) return -1; // TODO
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if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
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tr_flush_dirty_P();
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EOP_MOV_REG_SIMPLE(5, 10);
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@ -1126,8 +1325,13 @@ static int translate_op(unsigned int op, int *pc, int imm)
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known_regb &= ~(KRREG_A|KRREG_AL);
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ret++; break;
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}
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tr_read_funcs[tmpv]();
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if (tmpv == 0xc) {
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ret = tr_PM4_to_r0();
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if (ret != 0) return -1;
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}
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else tr_read_funcs[tmpv](); // TODO
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tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
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if (tmpv2 == SSP_PC) ret |= 0x10000;
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ret++; break;
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// ld d, (ri)
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@ -1141,6 +1345,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
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tr_rX_read(r, mod);
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else tr_ptrr_mod(r, mod, 1, 1);
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tr_write_funcs[tmpv](-1);
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if (tmpv == SSP_PC) ret |= 0x10000;
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ret++; break;
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}
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@ -1160,41 +1365,19 @@ static int translate_op(unsigned int op, int *pc, int imm)
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// ldi d, imm
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case 0x04:
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tmpv = (op & 0xf0) >> 4;
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tmpv = (op & 0xf0) >> 4; // dst
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ret = tr_detect_pm0_block(op, pc, imm);
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if (ret > 0) break;
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if (tmpv < 8)
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{
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tr_mov16(0, imm);
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tr_write_funcs[tmpv](imm);
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ret += 2; break;
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}
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else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
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{
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// programming PMC..
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(*pc)++;
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tmpv = imm | (PROGRAM((*pc)++) << 16);
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ret += 2;
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emit_mov_const(A_COND_AL, 0, tmpv);
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EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
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EOP_STR_IMM(0,7,0x400+14*4); // PMC
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// reads on fe06, fe08; next op is ld -,
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if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
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{
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int flag = (tmpv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
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tr_flush_dirty_ST();
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EOP_LDR_IMM(0,7,0x490); // dram_ptr
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EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
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EOP_LDRH_IMM(0,0,(tmpv == 0x187f03) ? 6 : 8); // ldrh r0, [r0, #8]
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EOP_TST_REG_SIMPLE(0,0);
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
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}
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EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET
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EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
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hostreg_r[0] = hostreg_r[1] = -1;
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ret += 2; break;
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}
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else
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return -1; /* TODO.. */
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ret = tr_detect_set_pm(op, pc, imm);
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if (ret > 0) break;
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if (tmpv == SSP_PC) ret |= 0x10000;
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return -1; /* TODO.. */
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// ld d, ((ri))
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case 0x05:
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@ -1202,6 +1385,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
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if (tmpv2 >= 8) return -1; // TODO
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tr_rX_read2(op);
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tr_write_funcs[tmpv2](-1);
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if (tmpv2 == SSP_PC) ret |= 0x10000;
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ret += 3; break;
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// ldi (ri), imm
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@ -1292,6 +1476,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
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tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
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}
|
||||
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
|
||||
ret |= 0x10000;
|
||||
ret += 2; break;
|
||||
}
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||||
|
||||
|
|
@ -1306,6 +1491,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
|
|||
EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
|
||||
hostreg_r[0] = hostreg_r[1] = -1;
|
||||
tr_write_funcs[tmpv2](-1);
|
||||
if (tmpv2 == SSP_PC) ret |= 0x10000;
|
||||
ret += 3; break;
|
||||
|
||||
// bra cond, addr
|
||||
|
|
@ -1316,6 +1502,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
|
|||
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
|
||||
}
|
||||
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
|
||||
ret |= 0x10000;
|
||||
ret += 2; break;
|
||||
|
||||
// mod cond, op
|
||||
|
|
@ -1519,7 +1706,7 @@ static void *translate_block(int pc)
|
|||
{
|
||||
unsigned int op, op1, imm, ccount = 0;
|
||||
unsigned int *block_start;
|
||||
int ret, ret_prev = -1;
|
||||
int ret, ret_prev = -1, tpc;
|
||||
|
||||
// create .pool
|
||||
//*tcache_ptr++ = (u32) in_funcs; // -1 func pool
|
||||
|
|
@ -1541,12 +1728,14 @@ static void *translate_block(int pc)
|
|||
|
||||
if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
|
||||
imm = PROGRAM(pc++); // immediate
|
||||
tpc = pc;
|
||||
|
||||
ret = translate_op(op, &pc, imm);
|
||||
if (ret <= 0)
|
||||
{
|
||||
tr_flush_dirty_prs();
|
||||
tr_flush_dirty_ST();
|
||||
tr_flush_dirty_pmcrs();
|
||||
|
||||
emit_mov_const(A_COND_AL, 0, op);
|
||||
|
||||
|
|
@ -1571,18 +1760,17 @@ static void *translate_block(int pc)
|
|||
known_regb = 0;
|
||||
}
|
||||
else
|
||||
ccount += ret;
|
||||
|
||||
if (op1 == 0x24 || op1 == 0x26 || // call, bra
|
||||
((op1 == 0 || op1 == 1 || op1 == 4 || op1 == 5 || op1 == 9 || op1 == 0x25) &&
|
||||
(op & 0xf0) == 0x60)) { // ld PC
|
||||
break;
|
||||
{
|
||||
ccount += ret & 0xffff;
|
||||
if (ret & 0x10000) break;
|
||||
}
|
||||
|
||||
ret_prev = ret;
|
||||
}
|
||||
|
||||
tr_flush_dirty_prs();
|
||||
tr_flush_dirty_ST();
|
||||
tr_flush_dirty_pmcrs();
|
||||
emit_block_epilogue(ccount + 1);
|
||||
*tcache_ptr++ = 0xffffffff; // end of block
|
||||
//printf(" %i inst\n", icount);
|
||||
|
|
|
|||
|
|
@ -91,9 +91,13 @@
|
|||
EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
|
||||
|
||||
/* addressing mode 3 */
|
||||
#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) \
|
||||
EMIT(((cond)<<28) | 0x01400090 | ((u)<<23) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (((offset_8)&0xf0)<<4) | \
|
||||
((s)<<6) | ((h)<<5) | ((offset_8)&0xf))
|
||||
#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
|
||||
EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
|
||||
((s)<<6) | ((h)<<5) | (immed_reg))
|
||||
|
||||
#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
|
||||
|
||||
#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
|
||||
|
||||
/* ldr and str */
|
||||
#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
|
||||
|
|
@ -104,6 +108,7 @@
|
|||
|
||||
#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
|
||||
#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
|
||||
#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
|
||||
#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
|
||||
#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
|
||||
|
||||
|
|
|
|||
|
|
@ -454,7 +454,7 @@ static int get_inc(int mode)
|
|||
return inc;
|
||||
}
|
||||
|
||||
#define overwite_write(dst, d) \
|
||||
#define overwrite_write(dst, d) \
|
||||
{ \
|
||||
if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
|
||||
if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
|
||||
|
|
@ -508,7 +508,7 @@ static u32 pm_io(int reg, int write, u32 d)
|
|||
elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
|
||||
reg, CADDR, d, inc, (mode>>10)&1);
|
||||
if (mode & 0x0400) {
|
||||
overwite_write(dram[addr], d);
|
||||
overwrite_write(dram[addr], d);
|
||||
} else dram[addr] = d;
|
||||
ssp->pmac_write[reg] += inc;
|
||||
}
|
||||
|
|
@ -517,7 +517,7 @@ static u32 pm_io(int reg, int write, u32 d)
|
|||
elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
|
||||
reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
|
||||
if (mode & 0x0400) {
|
||||
overwite_write(dram[addr], d);
|
||||
overwrite_write(dram[addr], d);
|
||||
} else dram[addr] = d;
|
||||
ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,11 +44,6 @@ static void PicoSVPReset(void)
|
|||
|
||||
static void PicoSVPLine(int count)
|
||||
{
|
||||
static int inited = 0;
|
||||
if (!(svp->ssp1601.gr[SSP_PM0].h & 2) && !inited) return;
|
||||
inited = 1;
|
||||
|
||||
// ???
|
||||
if (PicoOpt&0x20000)
|
||||
ssp1601_run(PicoSVPCycles * count);
|
||||
else
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue