sh2 drc, fix for mapping in register cache

This commit is contained in:
kub 2020-11-23 00:24:34 +01:00
parent 1a95ce340b
commit efb6bc7d73
2 changed files with 22 additions and 54 deletions

View file

@ -1724,11 +1724,7 @@ static void rcache_remove_vreg_alias(int x, sh2_reg_e r)
static void rcache_evict_vreg(int x) static void rcache_evict_vreg(int x)
{ {
#if REMAP_REGISTER
rcache_remap_vreg(x); rcache_remap_vreg(x);
#else
rcache_clean_vreg(x);
#endif
rcache_unmap_vreg(x); rcache_unmap_vreg(x);
} }
@ -1821,10 +1817,10 @@ static int rcache_allocate_temp(void)
return x; return x;
} }
#if REMAP_REGISTER
// maps a host register to a REG // maps a host register to a REG
static int rcache_map_reg(sh2_reg_e r, int hr) static int rcache_map_reg(sh2_reg_e r, int hr)
{ {
#if REMAP_REGISTER
int i; int i;
gconst_kill(r); gconst_kill(r);
@ -1855,11 +1851,15 @@ static int rcache_map_reg(sh2_reg_e r, int hr)
RCACHE_CHECK("after map"); RCACHE_CHECK("after map");
#endif #endif
return cache_regs[i].hreg; return cache_regs[i].hreg;
#else
return rcache_get_reg(r, RC_GR_WRITE, NULL);
#endif
} }
// remap vreg from a TEMP to a REG if it will be used (upcoming TEMP invalidation) // remap vreg from a TEMP to a REG if it will be used (upcoming TEMP invalidation)
static void rcache_remap_vreg(int x) static void rcache_remap_vreg(int x)
{ {
#if REMAP_REGISTER
u32 rsl_d = rcache_regs_soon | rcache_regs_late; u32 rsl_d = rcache_regs_soon | rcache_regs_late;
int d; int d;
@ -1898,12 +1898,14 @@ static void rcache_remap_vreg(int x)
#if DRC_DEBUG & 64 #if DRC_DEBUG & 64
RCACHE_CHECK("after remap"); RCACHE_CHECK("after remap");
#endif #endif
} #else
rcache_clean_vreg(x);
#endif #endif
}
#if ALIAS_REGISTERS
static void rcache_alias_vreg(sh2_reg_e rd, sh2_reg_e rs) static void rcache_alias_vreg(sh2_reg_e rd, sh2_reg_e rs)
{ {
#if ALIAS_REGISTERS
int x; int x;
// if s isn't constant, it must be in cache for aliasing // if s isn't constant, it must be in cache for aliasing
@ -1931,8 +1933,14 @@ static void rcache_alias_vreg(sh2_reg_e rd, sh2_reg_e rs)
#if DRC_DEBUG & 64 #if DRC_DEBUG & 64
RCACHE_CHECK("after alias"); RCACHE_CHECK("after alias");
#endif #endif
} #else
int hr_s = rcache_get_reg(rs, RC_GR_READ, NULL);
int hr_d = rcache_get_reg(rd, RC_GR_WRITE, NULL);
emith_move_r_r(hr_d, hr_s);
gconst_copy(rd, rs);
#endif #endif
}
// note: must not be called when doing conditional code // note: must not be called when doing conditional code
static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking, int *hr) static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking, int *hr)
@ -2380,11 +2388,7 @@ static void rcache_clean_tmp(void)
for (i = 0; i < ARRAY_SIZE(cache_regs); i++) for (i = 0; i < ARRAY_SIZE(cache_regs); i++)
if (cache_regs[i].type == HR_CACHED && (cache_regs[i].htype & HRT_TEMP)) { if (cache_regs[i].type == HR_CACHED && (cache_regs[i].htype & HRT_TEMP)) {
rcache_unlock(i); rcache_unlock(i);
#if REMAP_REGISTER
rcache_remap_vreg(i); rcache_remap_vreg(i);
#else
rcache_clean_vreg(i);
#endif
} }
rcache_regs_clean = 0; rcache_regs_clean = 0;
} }
@ -2658,16 +2662,9 @@ static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
{ {
if (gconst_check(src) || rcache_is_cached(src)) { if (gconst_check(src) || rcache_is_cached(src))
#if ALIAS_REGISTERS
rcache_alias_vreg(dst, src); rcache_alias_vreg(dst, src);
#else else {
int hr_s = rcache_get_reg(src, RC_GR_READ, NULL);
int hr_d = rcache_get_reg(dst, RC_GR_WRITE, NULL);
emith_move_r_r(hr_d, hr_s);
gconst_copy(dst, src);
#endif
} else {
int hr_d = rcache_get_reg(dst, RC_GR_WRITE, NULL); int hr_d = rcache_get_reg(dst, RC_GR_WRITE, NULL);
emith_ctx_read(hr_d, src * 4); emith_ctx_read(hr_d, src * 4);
} }
@ -2828,11 +2825,7 @@ static int emit_memhandler_read_rr(SH2 *sh2, sh2_reg_e rd, sh2_reg_e rs, u32 off
if (rd == SHR_TMP) if (rd == SHR_TMP)
hr2 = hr; hr2 = hr;
else else
#if REMAP_REGISTER
hr2 = rcache_map_reg(rd, hr); hr2 = rcache_map_reg(rd, hr);
#else
hr2 = rcache_get_reg(rd, RC_GR_WRITE, NULL);
#endif
if (hr != hr2) { if (hr != hr2) {
emith_move_r_r(hr2, hr); emith_move_r_r(hr2, hr);
@ -2902,11 +2895,7 @@ static int emit_indirect_indexed_read(SH2 *sh2, sh2_reg_e rd, sh2_reg_e rx, sh2_
if (rd == SHR_TMP) if (rd == SHR_TMP)
hr2 = hr; hr2 = hr;
else else
#if REMAP_REGISTER
hr2 = rcache_map_reg(rd, hr); hr2 = rcache_map_reg(rd, hr);
#else
hr2 = rcache_get_reg(rd, RC_GR_WRITE, NULL);
#endif
if (hr != hr2) { if (hr != hr2) {
emith_move_r_r(hr2, hr); emith_move_r_r(hr2, hr);
@ -3795,11 +3784,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2); emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
} }
tmp2 = emit_memhandler_read(opd->size); tmp2 = emit_memhandler_read(opd->size);
#if REMAP_REGISTER
tmp3 = rcache_map_reg(GET_Rn(), tmp2); tmp3 = rcache_map_reg(GET_Rn(), tmp2);
#else
tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE, NULL);
#endif
if (tmp3 != tmp2) { if (tmp3 != tmp2) {
emith_move_r_r(tmp3, tmp2); emith_move_r_r(tmp3, tmp2);
rcache_free_tmp(tmp2); rcache_free_tmp(tmp2);
@ -3903,11 +3888,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
rcache_invalidate_tmp(); rcache_invalidate_tmp();
emith_abicall(sh2_drc_divu32); emith_abicall(sh2_drc_divu32);
tmp = rcache_get_tmp_ret(); tmp = rcache_get_tmp_ret();
#if REMAP_REGISTER
tmp2 = rcache_map_reg(div(opd).rn, tmp); tmp2 = rcache_map_reg(div(opd).rn, tmp);
#else
tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
#endif
if (tmp != tmp2) if (tmp != tmp2)
emith_move_r_r(tmp2, tmp); emith_move_r_r(tmp2, tmp);
@ -3930,11 +3911,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
rcache_invalidate_tmp(); rcache_invalidate_tmp();
emith_abicall(sh2_drc_divu64); emith_abicall(sh2_drc_divu64);
tmp = rcache_get_tmp_ret(); tmp = rcache_get_tmp_ret();
#if REMAP_REGISTER
tmp2 = rcache_map_reg(div(opd).rn, tmp); tmp2 = rcache_map_reg(div(opd).rn, tmp);
#else
tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
#endif
tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL); tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL);
if (tmp != tmp2) if (tmp != tmp2)
emith_move_r_r(tmp2, tmp); emith_move_r_r(tmp2, tmp);
@ -4028,11 +4005,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
rcache_invalidate_tmp(); rcache_invalidate_tmp();
emith_abicall(sh2_drc_divs32); emith_abicall(sh2_drc_divs32);
tmp = rcache_get_tmp_ret(); tmp = rcache_get_tmp_ret();
#if REMAP_REGISTER
tmp2 = rcache_map_reg(div(opd).rn, tmp); tmp2 = rcache_map_reg(div(opd).rn, tmp);
#else
tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
#endif
if (tmp != tmp2) if (tmp != tmp2)
emith_move_r_r(tmp2, tmp); emith_move_r_r(tmp2, tmp);
tmp3 = rcache_get_tmp(); tmp3 = rcache_get_tmp();
@ -4058,11 +4031,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
rcache_invalidate_tmp(); rcache_invalidate_tmp();
emith_abicall(sh2_drc_divs64); emith_abicall(sh2_drc_divs64);
tmp = rcache_get_tmp_ret(); tmp = rcache_get_tmp_ret();
#if REMAP_REGISTER
tmp2 = rcache_map_reg(div(opd).rn, tmp); tmp2 = rcache_map_reg(div(opd).rn, tmp);
#else
tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
#endif
tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL); tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL);
if (tmp != tmp2) if (tmp != tmp2)
emith_move_r_r(tmp2, tmp); emith_move_r_r(tmp2, tmp);

View file

@ -1,7 +1,7 @@
int sh2_drc_init(SH2 *sh2); int sh2_drc_init(SH2 *sh2);
void sh2_drc_finish(SH2 *sh2); void sh2_drc_finish(SH2 *sh2);
void sh2_drc_wcheck_ram(uint32_t a, unsigned len, SH2 *sh2); void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2);
void sh2_drc_wcheck_da(uint32_t a, unsigned len, SH2 *sh2); void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2);
#ifdef DRC_SH2 #ifdef DRC_SH2
void sh2_drc_mem_setup(SH2 *sh2); void sh2_drc_mem_setup(SH2 *sh2);
@ -27,9 +27,8 @@ void sh2_drc_flush_all(void);
#define OF_DELAY_LOOP (2 << 2) #define OF_DELAY_LOOP (2 << 2)
#define OF_POLL_LOOP (3 << 2) #define OF_POLL_LOOP (3 << 2)
unsigned short scan_block(uint32_t base_pc, int is_slave, u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc,
unsigned char *op_flags, uint32_t *end_pc, u32 *base_literals, u32 *end_literals);
uint32_t *base_literals, uint32_t *end_literals);
#if defined(DRC_SH2) && defined(__GNUC__) && !defined(__clang__) #if defined(DRC_SH2) && defined(__GNUC__) && !defined(__clang__)
// direct access to some host CPU registers used by the DRC if gcc is used. // direct access to some host CPU registers used by the DRC if gcc is used.