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32x: drc: first implementation finished, no more interpreter dep
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@832 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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11 changed files with 397 additions and 161 deletions
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@ -189,8 +189,11 @@
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#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
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#define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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#define EOP_C_B(cond,l,signed_immed_24) \
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EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
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#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
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#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
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@ -205,6 +208,9 @@
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#define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
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#define EOP_C_MRS(cond,rd) \
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@ -308,6 +314,15 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
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#define emith_or_r_r_lsl(d, s, lslimm) \
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emith_or_r_r_r_lsl(d, d, s, lslimm)
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#define emith_eor_r_r_lsr(d, s, lsrimm) \
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emith_eor_r_r_r_lsr(d, d, s, lsrimm)
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#define emith_or_r_r_r(d, s1, s2) \
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emith_or_r_r_r_lsl(d, s1, s2, 0)
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@ -390,6 +405,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ORR, r, imm)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_EOR, r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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@ -459,6 +477,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_mul_s64(dlo, dhi, s1, s2) \
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EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
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#define emith_mula_s64(dlo, dhi, s1, s2) \
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EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
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// misc
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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@ -466,27 +487,42 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_ctx_write(r, offs) \
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EOP_STR_IMM(r, CONTEXT_REG, offs)
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#define emith_clear_msb(d, s, count) { \
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#define emith_clear_msb_c(cond, d, s, count) { \
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u32 t; \
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if ((count) <= 8) { \
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t = (count) - 8; \
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t = (0xff << t) & 0xff; \
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EOP_BIC_IMM(d,s,8/2,t); \
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EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
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} else if ((count) >= 24) { \
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t = (count) - 24; \
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t = 0xff >> t; \
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EOP_AND_IMM(d,s,0,t); \
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EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
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} else { \
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EOP_MOV_REG_LSL(d,s,count); \
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EOP_MOV_REG_LSR(d,d,count); \
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EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
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EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
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} \
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}
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#define emith_clear_msb(d, s, count) \
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emith_clear_msb_c(A_COND_AL, d, s, count)
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#define emith_sext(d, s, bits) { \
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EOP_MOV_REG_LSL(d,s,32 - (bits)); \
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EOP_MOV_REG_ASR(d,d,32 - (bits)); \
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}
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#define JMP_POS(ptr) \
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ptr = tcache_ptr; \
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tcache_ptr += sizeof(u32)
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#define JMP_EMIT(cond, ptr) { \
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int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
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EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
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}
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// _r_r
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// put bit0 of r0 to carry
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#define emith_set_carry(r0) \
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EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
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@ -564,3 +600,24 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_bic_r_imm_c(A_COND_CC, srr, 1); \
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} \
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}
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/*
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* if Q
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* t = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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*/
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#define emith_sh2_div1_step(rn, rm, sr) { \
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void *jmp0, *jmp1; \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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JMP_POS(jmp0); /* beq do_sub */ \
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emith_addf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CS, sr, T); \
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JMP_POS(jmp1); /* b done */ \
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JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
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emith_subf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CC, sr, T); \
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JMP_EMIT(A_COND_AL, jmp1); /* done: */ \
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}
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@ -1,5 +1,5 @@
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/*
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* note about silly things like emith_or_r_r_r_lsl:
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* note about silly things like emith_eor_r_r_r:
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* these are here because the compiler was designed
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* for ARM as it's primary target.
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*/
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@ -9,6 +9,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define CONTEXT_REG xBP
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#define IOP_JMP 0xeb
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#define IOP_JO 0x70
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#define IOP_JNO 0x71
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#define IOP_JB 0x72
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@ -56,6 +57,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define EMIT_MODRM(mod,r,rm) \
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EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
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#define EMIT_SIB(scale,index,base) \
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EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
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#define EMIT_OP_MODRM(op,mod,r,rm) { \
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EMIT_OP(op); \
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EMIT_MODRM(mod, r, rm); \
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@ -139,14 +143,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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} \
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}
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) { \
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// _r_r_shift
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#define emith_or_r_r_lsl(d, s, lslimm) { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsl(tmp_, s2, lslimm); \
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emith_or_r_r(tmp_, s1); \
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emith_move_r_r(d, tmp_); \
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emith_lsl(tmp_, s, lslimm); \
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emith_or_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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// d != s
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#define emith_eor_r_r_lsr(d, s, lsrimm) { \
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emith_push(s); \
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emith_lsr(s, s, lsrimm); \
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emith_eor_r_r(d, s); \
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emith_pop(s); \
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}
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// _r_imm
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#define emith_move_r_imm(r, imm) { \
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EMIT_OP(0xb8 + (r)); \
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@ -200,6 +212,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_or_r_imm(r, imm); \
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}
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#define emith_eor_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_eor_r_imm(r, imm); \
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}
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#define emith_sub_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_sub_r_imm(r, imm); \
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@ -264,11 +281,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_and_r_imm(d, t); \
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}
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#define emith_clear_msb_c(cond, d, s, count) { \
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(void)(cond); \
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emith_clear_msb(d, s, count); \
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}
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#define emith_sext(d, s, bits) { \
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emith_lsl(d, s, 32 - (bits)); \
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emith_asr(d, d, 32 - (bits)); \
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}
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#define emith_setc(r) { \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, r); /* SETC r */ \
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}
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// put bit0 of r0 to carry
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#define emith_set_carry(r0) { \
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emith_tst_r_imm(r0, 1); /* clears C */ \
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@ -318,6 +346,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_mul(d, s1, s2) \
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emith_mul_(4, d, -1, s1, s2)
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// (dlo,dhi) += signed(s1) * signed(s2)
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#define emith_mula_s64(dlo, dhi, s1, s2) { \
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emith_push(dhi); \
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emith_push(dlo); \
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emith_mul_(5, dlo, dhi, s1, s2); \
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EMIT_OP_MODRM(0x03, 0, dlo, 4); \
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EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
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EMIT_OP_MODRM(0x13, 1, dhi, 4); \
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EMIT_SIB(0, 4, 4); \
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EMIT(4, u8); /* adc dhi, [esp+4] */ \
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emith_add_r_imm(xSP, 4*2); \
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}
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// "flag" instructions are the same
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#define emith_subf_r_imm emith_sub_r_imm
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#define emith_addf_r_r emith_add_r_r
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@ -357,6 +398,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(disp, u32); \
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}
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#define emith_call_cond(cond, ptr) \
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emith_call(ptr)
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// "simple" or "short" jump
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#define EMITH_SJMP_START(cond) { \
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u8 *cond_ptr; \
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@ -429,11 +473,31 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_carry_to_t(srr, is_sub) { \
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int tmp_ = rcache_get_tmp(); \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, tmp_); /* SETC */ \
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emith_setc(tmp_); \
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emith_bic_r_imm(srr, 1); \
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EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp_); \
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}
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/*
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* if Q
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* t = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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*/
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#define emith_sh2_div1_step(rn, rm, sr) { \
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u8 *jmp0, *jmp1; \
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int tmp_ = rcache_get_tmp(); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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JMP8_POS(jmp0); /* je do_sub */ \
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emith_add_r_r(rn, rm); \
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JMP8_POS(jmp1); /* jmp done */ \
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JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
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emith_sub_r_r(rn, rm); \
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JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
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emith_setc(tmp_); \
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EMIT_OP_MODRM(0x30, 3, tmp_, sr); /* T = Q1 ^ Q2 (byte) */ \
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rcache_free_tmp(tmp_); \
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}
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