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32x: drc: first implementation finished, no more interpreter dep
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@832 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
parent
4b315c210a
commit
f0d7b1faa1
11 changed files with 397 additions and 161 deletions
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@ -1,6 +1,7 @@
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/*
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* vim:shiftwidth=2:expandtab
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*/
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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@ -125,6 +126,9 @@ static temp_reg_t reg_temp[] = {
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#define Q 0x00000100
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#define M 0x00000200
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#define Q_SHIFT 8
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#define M_SHIFT 9
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typedef enum {
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SHR_R0 = 0, SHR_SP = 15,
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SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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@ -517,6 +521,58 @@ static void emit_indirect_indexed_write(int rx, int ry, int wr, int size)
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emit_memhandler_write(size);
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}
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// read @Rn, @rm
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static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
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{
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int tmp;
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rcache_clean();
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rcache_get_reg_arg(0, rn);
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tmp = emit_memhandler_read(size);
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emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
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rcache_free_tmp(tmp);
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tmp = rcache_get_reg(rn, RC_GR_RMW);
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emith_add_r_imm(tmp, 1 << size);
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rcache_clean();
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rcache_get_reg_arg(0, rm);
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*rmr = emit_memhandler_read(size);
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*rnr = rcache_get_tmp();
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emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
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tmp = rcache_get_reg(rm, RC_GR_RMW);
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emith_add_r_imm(tmp, 1 << size);
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}
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// fixup for saturated MAC, to be called from generated code
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// FIXME: statically alloced regs need to be fixed
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static void sh2_macl_sat_fixup(void)
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{
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if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000)
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{
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sh2->mach = 0x00008000;
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sh2->macl = 0x00000000;
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}
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else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff)
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{
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sh2->mach = 0x00007fff;
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sh2->macl = 0xffffffff;
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}
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}
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static void sh2_macw_sat_fixup(void)
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{
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signed int t = sh2->mach;
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if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000)))
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{
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sh2->mach = 0xffffffff; // ?
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sh2->macl = 0x80000000;
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}
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else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000)))
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{
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sh2->mach = 0x7fffffff;
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sh2->macl = 0xffffffff;
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}
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}
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#define DELAYED_OP \
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delayed_op = 2
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@ -546,7 +602,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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int op, delayed_op = 0, test_irq = 0;
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int tcache_id = 0, blkid = 0;
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int cycles = 0;
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u32 tmp, tmp2, tmp3, tmp4;
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u32 tmp, tmp2, tmp3, tmp4, sr;
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// validate PC
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tmp = sh2->pc >> 29;
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@ -771,8 +827,27 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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rcache_free_tmp(tmp);
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goto end_op;
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case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
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// TODO
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break;
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emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
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tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
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/* MS 16 MAC bits unused if saturated */
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emith_tst_r_imm(tmp3, S);
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EMITH_SJMP_START(DCOND_EQ);
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emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
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EMITH_SJMP_END(DCOND_EQ);
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tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
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emith_mula_s64(tmp3, tmp4, tmp, tmp2);
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rcache_free_tmp(tmp);
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rcache_free_tmp(tmp2);
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rcache_clean();
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
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emith_tst_r_imm(tmp3, S);
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EMITH_SJMP_START(DCOND_EQ);
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emith_call_cond(DCOND_NE, sh2_macl_sat_fixup);
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EMITH_SJMP_END(DCOND_EQ);
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rcache_invalidate();
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cycles += 3;
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goto end_op;
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}
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goto default_;
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@ -869,7 +944,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emith_lsr(tmp, tmp, 16);
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emith_or_r_r_r_lsl(tmp, tmp, tmp2, 16);
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emith_or_r_r_lsl(tmp, tmp2, 16);
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goto end_op;
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case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
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case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
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@ -935,8 +1010,37 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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}
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goto end_op;
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case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
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// TODO
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break;
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// Q1 = carry(Rn = (Rn << 1) | T)
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// if Q ^ M
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// Q2 = carry(Rn += Rm)
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// else
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// Q2 = carry(Rn -= Rm)
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// Q = M ^ Q1 ^ Q2
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// T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_set_carry(sr);
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emith_adcf_r_r(tmp2, tmp2);
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emith_carry_to_t(sr, 0); // keep Q1 in T for now
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tmp4 = rcache_get_tmp();
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emith_and_r_r_imm(tmp4, sr, M);
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emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
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rcache_free_tmp(tmp4);
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// add or sub, invert T if carry to get Q1 ^ Q2
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// in: (Q ^ M) passed in Q, Q1 in T
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emith_sh2_div1_step(tmp2, tmp3, sr);
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emith_bic_r_imm(sr, Q);
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emith_tst_r_imm(sr, M);
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EMITH_SJMP_START(DCOND_EQ);
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emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
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EMITH_SJMP_END(DCOND_EQ);
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emith_tst_r_imm(sr, T);
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EMITH_SJMP_START(DCOND_EQ);
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emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
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EMITH_SJMP_END(DCOND_EQ);
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emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
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goto end_op;
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case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
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tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
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tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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@ -1248,7 +1352,6 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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}
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if (tmp2 == SHR_SR) {
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emith_write_sr(tmp);
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emit_move_r_imm32(SHR_PC, pc);
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test_irq = 1;
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} else {
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tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
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@ -1257,7 +1360,24 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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goto end_op;
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case 0x0f:
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// MAC @Rm+,@Rn+ 0100nnnnmmmm1111
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break; // TODO
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emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
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emith_sext(tmp, tmp, 16);
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emith_sext(tmp2, tmp2, 16);
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tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
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tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
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emith_mula_s64(tmp3, tmp4, tmp, tmp2);
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rcache_free_tmp(tmp);
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rcache_free_tmp(tmp2);
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rcache_clean();
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// XXX: MACH should be untouched when S is set?
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
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emith_tst_r_imm(tmp3, S);
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EMITH_SJMP_START(DCOND_EQ);
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emith_call_cond(DCOND_NE, sh2_macw_sat_fixup);
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EMITH_SJMP_END(DCOND_EQ);
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rcache_invalidate();
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cycles += 2;
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goto end_op;
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}
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goto default_;
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@ -1315,9 +1435,9 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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tmp3 = rcache_get_tmp();
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tmp4 = rcache_get_tmp();
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emith_lsr(tmp3, tmp, 16);
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emith_or_r_r_r_lsl(tmp3, tmp3, tmp, 24);
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emith_or_r_r_lsl(tmp3, tmp, 24);
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emith_and_r_r_imm(tmp4, tmp, 0xff00);
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emith_or_r_r_r_lsl(tmp3, tmp3, tmp4, 8);
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emith_or_r_r_lsl(tmp3, tmp4, 8);
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emith_rol(tmp2, tmp3, 16);
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rcache_free_tmp(tmp4);
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if (tmp == tmp2)
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@ -1429,8 +1549,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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/////////////////////////////////////////////
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case 0x09:
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// MOV.W @(disp,PC),Rn 1001nnnndddddddd
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// TODO
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goto default_;
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rcache_clean();
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tmp = rcache_get_tmp_arg(0);
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emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
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tmp = emit_memhandler_read(1);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
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emith_sext(tmp2, tmp, 16);
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rcache_free_tmp(tmp);
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goto end_op;
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/////////////////////////////////////////////
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case 0x0a:
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@ -1557,8 +1683,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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/////////////////////////////////////////////
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case 0x0d:
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// MOV.L @(disp,PC),Rn 1101nnnndddddddd
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// TODO
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goto default_;
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rcache_clean();
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tmp = rcache_get_tmp_arg(0);
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emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
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tmp = emit_memhandler_read(2);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
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emith_move_r_r(tmp2, tmp);
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rcache_free_tmp(tmp);
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goto end_op;
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/////////////////////////////////////////////
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case 0x0e:
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@ -1569,11 +1701,15 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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default:
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default_:
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elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
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sh2->is_slave ? 's' : 'm', op, pc - 2);
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#ifdef DRC_DEBUG_INTERP
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emit_move_r_imm32(SHR_PC, pc - 2);
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rcache_flush();
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_pass_arg_imm(1, op);
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emith_call(sh2_do_op);
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#endif
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break;
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}
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@ -1582,10 +1718,12 @@ end_op:
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emit_move_r_r(SHR_PC, SHR_PPC);
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if (test_irq && delayed_op != 2) {
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if (!delayed_op)
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emit_move_r_imm32(SHR_PC, pc);
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rcache_flush();
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_call(sh2_test_irq);
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break;
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goto end_block_btf;
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}
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if (delayed_op == 1)
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break;
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