mirror of
https://github.com/RaySollium99/picodrive.git
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sh2 drc, small improvements and bug fixes for code emitters
This commit is contained in:
kub
parent
cf0dd6ae48
commit
f2d19ddf2a
6 changed files with 194 additions and 83 deletions
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@ -478,6 +478,7 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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switch (op) {
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case A_OP_MOV:
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case A_OP_MVN:
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rn = 0;
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// use MVN if more bits 1 than 0
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if (count_bits(imm) > 16) {
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@ -501,7 +502,7 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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return;
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}
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#else
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for (i = 2, u = v; i > 0; i--, u >>= 8)
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for (i = 3, u = v; i > 0; i--, u >>= 8)
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while (u > 0xff && !(u & 3))
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u >>= 2;
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if (u) { // 4 insns needed...
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@ -1387,22 +1388,25 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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} while (0)
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/*
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* T = carry(Rn = (Rn << 1) | T)
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* if Q
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* t = carry(Rn += Rm)
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* T ^= !carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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* T ^= !carry(Rn -= Rm)
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*/
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#define emith_sh2_div1_step(rn, rm, sr) do { \
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void *jmp0, *jmp1; \
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emith_tpop_carry(sr, 0); /* Rn = 2*Rn+T */\
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emith_adcf_r_r_r(rn, rn, rn); \
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emith_tpush_carry(sr, 0); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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JMP_POS(jmp0); /* beq do_sub */ \
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emith_addf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CS, sr, T); \
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emith_addf_r_r(rn, rm); /* Rn += Rm */ \
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emith_eor_r_imm_c(A_COND_CC, sr, T); \
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JMP_POS(jmp1); /* b done */ \
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JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
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emith_subf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CC, sr, T); \
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emith_subf_r_r(rn, rm); /* Rn -= Rm */ \
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emith_eor_r_imm_c(A_COND_CS, sr, T); \
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JMP_EMIT(A_COND_AL, jmp1); /* done: */ \
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} while (0)
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@ -372,7 +372,7 @@ enum { AM_IDX, AM_IDXPOST, AM_IDXREG, AM_IDXPRE };
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#define EMITH_HINT_COND(cond) /**/
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// "simple" jump (no more then a few insns)
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// "simple" jump (no more than a few insns)
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// ARM32 will use conditional instructions here
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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@ -1240,22 +1240,26 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
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} while (0)
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/*
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* T = carry(Rn = (Rn << 1) | T)
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* if Q
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* t = carry(Rn += Rm)
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* t = !carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* t = !carry(Rn -= Rm)
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* T ^= t
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*/
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#define emith_sh2_div1_step(rn, rm, sr) do { \
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int tmp_ = rcache_get_tmp(); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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emith_tpop_carry(sr, 0); \
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emith_adcf_r_r_r(rn, rn, rn); \
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emith_tpush_carry(sr, 0); \
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emith_tst_r_imm(sr, Q); \
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EMITH_SJMP3_START(DCOND_EQ); \
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emith_addf_r_r(rn, rm); \
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emith_adc_r_r_r(tmp_, Z0, Z0); \
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emith_eor_r_imm(tmp_, 1); \
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EMITH_SJMP3_MID(DCOND_EQ); \
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emith_subf_r_r(rn, rm); \
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emith_adc_r_r_r(tmp_, Z0, Z0); \
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emith_eor_r_imm(tmp_, 1); \
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EMITH_SJMP3_END(); \
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emith_eor_r_r(sr, tmp_); \
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rcache_free_tmp(tmp_); \
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@ -7,9 +7,10 @@
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*/
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#define HOST_REGS 32
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// MIPS ABI: params: r4-r7, return: r2-r3, temp: r1(at),r8-r15,r24-r25,r31(ra),
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// MIPS32 ABI: params: r4-r7, return: r2-r3, temp: r1(at),r8-r15,r24-r25,r31(ra)
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// saved: r16-r23,r30, reserved: r0(zero), r26-r27(irq), r28(gp), r29(sp)
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// r1,r15,r24,r25(at,t7-t9) are used internally by the code emitter
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// MIPSN32/MIPS64 ABI: params: r4-r11, no caller-reserved save area on stack
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#define RET_REG 2 // v0
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#define PARAM_REGS { 4, 5, 6, 7 } // a0-a3
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#define PRESERVED_REGS { 16, 17, 18, 19, 20, 21, 22, 23 } // s0-s7
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@ -424,7 +425,7 @@ static void *emith_branch(u32 op)
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JMP_EMIT_NC(else_ptr); \
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}
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// "simple" jump (no more then a few insns)
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// "simple" jump (no more than a few insns)
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// ARM32 will use conditional instructions here
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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@ -761,7 +762,7 @@ static void emith_move_imm(int r, uintptr_t imm)
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EMIT(MIPS_OR_IMM(r, r, imm & 0xffff));
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} else
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#endif
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if ((s16)imm == imm) {
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if ((s16)imm == imm) {
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EMIT(MIPS_ADD_IMM(r, Z0, imm));
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} else if (!((u32)imm >> 16)) {
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EMIT(MIPS_OR_IMM(r, Z0, imm));
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@ -1576,22 +1577,31 @@ static int emith_cond_check(int cond, int *r)
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} while (0)
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/*
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* T = !carry(Rn = (Rn << 1) | T)
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* if Q
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* t = carry(Rn += Rm)
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* C = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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* C = carry(Rn -= Rm)
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* T ^= C
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*/
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#define emith_sh2_div1_step(rn, rm, sr) do { \
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int t_ = rcache_get_tmp(); \
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emith_and_r_r_imm(AT, sr, T); \
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emith_lsr(FC, rn, 31); /*Rn = (Rn<<1)+T*/ \
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emith_lsl(t_, rn, 1); \
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emith_or_r_r(t_, AT); \
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emith_or_r_imm(sr, T); /* T = !carry */ \
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emith_eor_r_r(sr, FC); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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EMITH_JMP3_START(DCOND_EQ); \
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EMITH_HINT_COND(DCOND_CS); \
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emith_addf_r_r(rn, rm); \
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emith_add_r_r_r(rn, t_, rm); \
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EMIT(MIPS_SLTU_REG(FC, rn, t_)); \
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EMITH_JMP3_MID(DCOND_EQ); \
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EMITH_HINT_COND(DCOND_CS); \
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emith_subf_r_r(rn, rm); \
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emith_sub_r_r_r(rn, t_, rm); \
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EMIT(MIPS_SLTU_REG(FC, t_, rn)); \
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EMITH_JMP3_END(); \
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emith_eor_r_r(sr, FC); \
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emith_eor_r_r(sr, FC); /* T ^= carry */ \
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rcache_free_tmp(t_); \
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} while (0)
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/* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
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@ -7,7 +7,7 @@
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*/
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#define HOST_REGS 32
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// RISC-V ABI: params: x10-x17, return: r10-x11, temp: x1(ra),x5-x7,x28-x31
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// RISC-V ABI: params: x10-x17, return: x10-x11, temp: x1(ra),x5-x7,x28-x31
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// saved: x8(fp),x9,x18-x27, reserved: x0(zero), x4(tp), x3(gp), x2(sp)
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// x28-x31(t3-t6) are used internally by the code emitter
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#define RET_REG 10 // a0
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@ -74,13 +74,14 @@
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_CB(imm,8,12,0), rd, op)
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// opcode
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enum { OP_LUI=0x37, OP_JAL=0x6f, OP_JALR=0x67, OP_BCOND=0x63, OP_LD=0x03,
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OP_ST=0x23, OP_IMM=0x13, OP_IMM32=0x1b, OP_REG=0x33, OP_REG32=0x3b };
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enum { OP_LUI=0x37, OP_AUIPC=0x17, OP_JAL=0x6f, // 20-bit immediate
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OP_JALR=0x67, OP_BCOND=0x63, OP_LD=0x03, OP_ST=0x23, // 12-bit immediate
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OP_IMM=0x13, OP_REG=0x33, OP_IMM32=0x1b, OP_REG32=0x3b };
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// func3
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enum { F1_ADD, F1_SL, F1_SLT, F1_SLTU, F1_XOR, F1_SR, F1_OR, F1_AND };
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enum { F1_BEQ, F1_BNE, F1_BLT=4, F1_BGE, F1_BLTU, F1_BGEU };
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enum { F1_B, F1_H, F1_W, F1_D, F1_BU, F1_HU, F1_WU };
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enum { F1_ADD, F1_SL, F1_SLT, F1_SLTU, F1_XOR, F1_SR, F1_OR, F1_AND };// IMM/REG
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enum { F1_MUL, F1_MULH, F1_MULHSU, F1_MULHU, F1_DIV, F1_DIVU, F1_REM, F1_REMU };
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enum { F1_BEQ, F1_BNE, F1_BLT=4, F1_BGE, F1_BLTU, F1_BGEU }; // BCOND
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enum { F1_B, F1_H, F1_W, F1_D, F1_BU, F1_HU, F1_WU }; // LD/ST
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// func7
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enum { F2_ALT=0x20, F2_MULDIV=0x01 };
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@ -141,6 +142,8 @@ enum { F2_ALT=0x20, F2_MULDIV=0x01 };
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R5_OR_IMM(rd, Z0, imm12)
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#define R5_MOVT_IMM(rd, imm20) \
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R5_U_INSN(OP_LUI, rd, imm20)
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#define R5_MOVA_IMM(rd, imm20) \
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R5_U_INSN(OP_AUIPC, rd, imm20)
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// rd = rs SHIFT imm5/imm6
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#define R5_LSL_IMM(rd, rs, bits) \
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@ -212,8 +215,10 @@ enum { F2_ALT=0x20, F2_MULDIV=0x01 };
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#define PTR_SCALE 3
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// NB: must split 64 bit result into 2 32 bit registers
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// NB: this expects 32 bit values in s1+s2, correctly sign extended to 64 bits
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// NB: expects 32 bit values in s1+s2, correctly sign extended to 64 bits
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#define EMIT_R5_MULLU_REG(dlo, dhi, s1, s2) do { \
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/*EMIT(R5_ADDW_IMM(s1, s1, 0));*/ \
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/*EMIT(R5_ADDW_IMM(s2, s2, 0));*/ \
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EMIT(R5_MUL(dlo, s1, s2)); \
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EMIT(R5_LSR_IMM(dhi, dlo, 32)); \
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EMIT(R5_LSL_IMM(dlo, dlo, 32)); \
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@ -307,7 +312,7 @@ enum { F2_ALT=0x20, F2_MULDIV=0x01 };
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JMP_EMIT_NC(else_ptr); \
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}
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// "simple" jump (no more then a few insns)
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// "simple" jump (no more than a few insns)
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// ARM32 will use conditional instructions here
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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@ -620,6 +625,67 @@ static void emith_set_compare_flags(int rs, int rt, s32 imm)
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// move immediate
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#define MAX_HOST_LITERALS 32 // pool must be smaller than 4 KB
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static uintptr_t literal_pool[MAX_HOST_LITERALS];
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static u32 *literal_insn[MAX_HOST_LITERALS];
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static int literal_pindex, literal_iindex;
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static inline int emith_pool_literal(uintptr_t imm)
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{
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int idx = literal_pindex - 8; // max look behind in pool
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// see if one of the last literals was the same (or close enough)
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for (idx = (idx < 0 ? 0 : idx); idx < literal_pindex; idx++)
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if (imm == literal_pool[idx])
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break;
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if (idx == literal_pindex) // store new literal
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literal_pool[literal_pindex++] = imm;
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return idx;
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}
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static void emith_pool_commit(int jumpover)
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{
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int i, sz = literal_pindex * sizeof(uintptr_t);
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u8 *pool = (u8 *)tcache_ptr;
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// nothing to commit if pool is empty
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if (sz == 0)
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return;
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// align pool to pointer size
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if (jumpover)
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pool += sizeof(u32);
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i = (uintptr_t)pool & (sizeof(void *)-1);
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pool += (i ? sizeof(void *)-i : 0);
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// need branch over pool if not at block end
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if (jumpover)
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EMIT(R5_B(sz + (pool-(u8 *)tcache_ptr)));
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// safety check - pool must be after insns and reachable
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if ((u32)(pool - (u8 *)literal_insn[0] + 8) > 0x7ff) {
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elprintf(EL_STATUS|EL_SVP|EL_ANOMALY,
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"pool offset out of range");
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exit(1);
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}
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// copy pool and adjust addresses in insns accessing the pool
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memcpy(pool, literal_pool, sz);
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for (i = 0; i < literal_iindex; i++) {
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*literal_insn[i] += ((u8 *)pool - (u8 *)literal_insn[i]) << 20;
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}
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// count pool constants as insns for statistics
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for (i = 0; i < literal_pindex * sizeof(uintptr_t)/sizeof(u32); i++)
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COUNT_OP;
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tcache_ptr = (void *)((u8 *)pool + sz);
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literal_pindex = literal_iindex = 0;
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}
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static void emith_pool_check(void)
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{
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// check if pool must be committed
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if (literal_iindex > MAX_HOST_LITERALS-4 || (literal_pindex &&
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(u8 *)tcache_ptr - (u8 *)literal_insn[0] > 0x700))
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// pool full, or displacement is approaching the limit
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emith_pool_commit(1);
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}
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static void emith_move_imm(int r, uintptr_t imm)
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{
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u32 lui = imm + _CB(imm,1,11,12);
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@ -632,8 +698,24 @@ static void emith_move_imm(int r, uintptr_t imm)
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EMIT(R5_ADD_IMM(r, Z0, imm));
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}
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static void emith_move_ptr_imm(int r, uintptr_t imm)
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{
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#if __riscv_xlen == 64
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if ((s32)imm != imm) {
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int idx;
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if (literal_iindex >= MAX_HOST_LITERALS)
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emith_pool_commit(1);
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idx = emith_pool_literal(imm);
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EMIT(R5_MOVA_IMM(AT, 0)); // loads PC of MOVA insn... + 4 in LD
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literal_insn[literal_iindex++] = (u32 *)tcache_ptr;
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EMIT(R5_I_INSN(OP_LD, F1_P, r, AT, idx*sizeof(uintptr_t) + 4));
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} else
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#endif
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emith_move_imm(r, imm);
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}
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#define emith_move_r_ptr_imm(r, imm) \
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emith_move_imm(r, (uintptr_t)(imm))
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emith_move_ptr_imm(r, (uintptr_t)(imm))
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#define emith_move_r_imm(r, imm) \
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emith_move_imm(r, (u32)(imm))
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@ -644,7 +726,6 @@ static void emith_move_imm(int r, uintptr_t imm)
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EMIT(R5_ADD_IMM(r, Z0, (s8)(imm)))
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#define emith_move_r_imm_s8_patch(ptr, imm) do { \
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u32 *ptr_ = (u32 *)ptr; \
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while ((*ptr_ & 0xff07f) != R5_ADD_IMM(Z0, Z0, 0)) ptr_++; \
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EMIT_PTR(ptr_, (*ptr_ & 0x000fffff) | ((u16)(s8)(imm)<<20)); \
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} while (0)
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@ -1235,7 +1316,6 @@ static int emith_cond_check(int cond, int *r, int *s)
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// NB: returns position of patch for cache maintenance
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#define emith_jump_patch(ptr, target, pos) do { \
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u32 *ptr_ = (u32 *)ptr; /* must skip condition check code */ \
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while ((*ptr_&0x77) != OP_JALR && (*ptr_&0x77) != OP_BCOND) ptr_ ++; \
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if ((*ptr_&0x77) == OP_BCOND) { \
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u32 *p_ = ptr_, disp_ = (u8 *)target - (u8 *)ptr_; \
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u32 f1_ = _CB(*ptr_,3,12,0); \
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@ -1319,8 +1399,6 @@ static int emith_cond_check(int cond, int *r, int *s)
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// emitter ABI stuff
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#define emith_pool_check() /**/
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#define emith_pool_commit(j) /**/
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#define emith_insn_ptr() ((u8 *)tcache_ptr)
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#define emith_flush() /**/
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#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
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@ -1404,22 +1482,31 @@ static int emith_cond_check(int cond, int *r, int *s)
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} while (0)
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/*
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* T = !carry(Rn = (Rn << 1) | T)
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* if Q
|
||||
* t = carry(Rn += Rm)
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* C = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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||||
* C = carry(Rn -= Rm)
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* T ^= C
|
||||
*/
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#define emith_sh2_div1_step(rn, rm, sr) do { \
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||||
int t_ = rcache_get_tmp(); \
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emith_and_r_r_imm(AT, sr, T); \
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emith_lsr(FC, rn, 31); /*Rn = (Rn<<1)+T*/ \
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emith_lsl(t_, rn, 1); \
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emith_or_r_r(t_, AT); \
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emith_or_r_imm(sr, T); /* T = !carry */ \
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emith_eor_r_r(sr, FC); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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EMITH_JMP3_START(DCOND_EQ); \
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EMITH_HINT_COND(DCOND_CS); \
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||||
emith_addf_r_r(rn, rm); \
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||||
emith_add_r_r_r(rn, t_, rm); \
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EMIT(R5_SLTU_REG(FC, rn, t_)); \
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||||
EMITH_JMP3_MID(DCOND_EQ); \
|
||||
EMITH_HINT_COND(DCOND_CS); \
|
||||
emith_subf_r_r(rn, rm); \
|
||||
emith_sub_r_r_r(rn, t_, rm); \
|
||||
EMIT(R5_SLTU_REG(FC, t_, rn)); \
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||||
EMITH_JMP3_END(); \
|
||||
emith_eor_r_r(sr, FC); \
|
||||
emith_eor_r_r(sr, FC); /* T ^= carry */ \
|
||||
rcache_free_tmp(t_); \
|
||||
} while (0)
|
||||
|
||||
/* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
|
||||
|
|
|
|||
|
|
@ -974,7 +974,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
|
|||
JMP8_EMIT_NC(else_ptr); \
|
||||
}
|
||||
|
||||
// "simple" jump (no more then a few insns)
|
||||
// "simple" jump (no more than a few insns)
|
||||
// ARM will use conditional instructions here
|
||||
#define EMITH_SJMP_START EMITH_JMP_START
|
||||
#define EMITH_SJMP_END EMITH_JMP_END
|
||||
|
|
@ -1287,15 +1287,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
|
|||
emith_adc_r_r(sr, sr)
|
||||
|
||||
/*
|
||||
* T = carry(Rn = (Rn << 1) | T)
|
||||
* if Q
|
||||
* t = carry(Rn += Rm)
|
||||
* else
|
||||
* t = carry(Rn -= Rm)
|
||||
* T ^= t
|
||||
* T = !(T ^ t)
|
||||
*/
|
||||
#define emith_sh2_div1_step(rn, rm, sr) do { \
|
||||
u8 *jmp0, *jmp1; \
|
||||
int tmp_ = rcache_get_tmp(); \
|
||||
emith_tpop_carry(sr, 0); /* Rn = 2*Rn+T */\
|
||||
emith_adcf_r_r_r(rn, rn, rn); \
|
||||
emith_tpush_carry(sr, 0); /* T = C1 */ \
|
||||
emith_eor_r_r(tmp_, tmp_); \
|
||||
emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
|
||||
JMP8_POS(jmp0); /* je do_sub */ \
|
||||
|
|
@ -1305,7 +1309,8 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
|
|||
emith_sub_r_r(rn, rm); \
|
||||
JMP8_EMIT_NC(jmp1); /* done: */ \
|
||||
emith_adc_r_r(tmp_, tmp_); \
|
||||
emith_eor_r_r(sr, tmp_); \
|
||||
emith_eor_r_r(sr, tmp_);/* T = !(C1^C2) */\
|
||||
emith_eor_r_imm(sr, T); \
|
||||
rcache_free_tmp(tmp_); \
|
||||
} while (0)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue