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sound, fixes for ym2612 (ARM and C)

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This commit is contained in:
kub 2023-06-21 18:15:33 +00:00
parent 70ef073f66
commit f3876af7f9
2 changed files with 19 additions and 9 deletions
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8
pico/sound/ym2612.c
View file

@ -550,7 +550,7 @@ static INLINE void recalc_volout(FM_SLOT *SLOT)
{ {
INT16 vol_out = SLOT->volume; INT16 vol_out = SLOT->volume;
if ((SLOT->ssg&0x0c) == 0x0c) if ((SLOT->ssg&0x0c) == 0x0c)
vol_out = (0x200 - SLOT->volume) & MAX_ATT_INDEX; vol_out = (0x200 - vol_out) & MAX_ATT_INDEX;
SLOT->vol_out = vol_out + SLOT->tl; SLOT->vol_out = vol_out + SLOT->tl;
} }
@ -880,7 +880,7 @@ static INLINE UINT32 update_ssg_eg_phase(FM_SLOT *SLOT, UINT32 phase)
} }
} }
} }
// recalc_volout(SLOT); recalc_volout(SLOT);
return phase; return phase;
} }
#endif #endif
@ -1663,8 +1663,8 @@ static int OPNWriteReg(int r, int v)
SLOT->ssg ^= SLOT->ssgn; SLOT->ssg ^= SLOT->ssgn;
if (v&0x08) ym2612.ssg_mask |= 1<<(OPN_SLOT(r) + c*4); if (v&0x08) ym2612.ssg_mask |= 1<<(OPN_SLOT(r) + c*4);
else ym2612.ssg_mask &= ~(1<<(OPN_SLOT(r) + c*4)); else ym2612.ssg_mask &= ~(1<<(OPN_SLOT(r) + c*4));
// if (SLOT->state > EG_REL) if (SLOT->state > EG_REL)
// recalc_volout(SLOT); recalc_volout(SLOT);
break; break;
case 0xa0: case 0xa0:

20
pico/sound/ym2612_arm.S
View file

@ -198,10 +198,10 @@
ldrb r2, [r5,#0x17] @ state ldrb r2, [r5,#0x17] @ state
ldrh r3, [r5,#0x1a] @ volume ldrh r3, [r5,#0x1a] @ volume
tst r0, #0x08 @ ssg enabled && tst r0, #0x08 @ ssg enabled &&
beq 9f beq 10f
cmp r2, #EG_REL+1 @ state > EG_REL && cmp r2, #EG_REL+1 @ state > EG_REL &&
cmpge r3, #0x200 @ volume >= 0x200? cmpge r3, #0x200 @ volume >= 0x200?
blt 9f blt 10f
tst r0, #0x01 tst r0, #0x01
beq 1f beq 1f
@ -245,6 +245,15 @@
movgt r2, #EG_ATT movgt r2, #EG_ATT
8: strb r2, [r5,#0x17] @ state 8: strb r2, [r5,#0x17] @ state
9: 9:
ldrb r0, [r5,#0x30] @ ssg
ldrh r2, [r5,#0x18] @ tl
cmp r0, #0x0c
rsbge r3, r3, #0x200 @ volume = (0x200-volume) & MAX_ATT
movge r3, r3, lsl #22
movge r3, r3, lsr #22
add r3, r3, r2 @ volume += tl
strh r3, [r5,#0x34] @ vol_out
10:
.endm .endm
@ r5=slot, trashes: r0,r2,r3 @ r5=slot, trashes: r0,r2,r3
@ -703,11 +712,11 @@ ssg_upd_loop:
addne lr, lr, #4 addne lr, lr, #4
addne r5, r5, #SLOT_STRUCT_SIZE addne r5, r5, #SLOT_STRUCT_SIZE
#else #else
add lr, lr, #4*2 add lr, lr, #4
add r5, r5, #SLOT_STRUCT_SIZE*2 add r5, r5, #SLOT_STRUCT_SIZE*2
update_ssg_eg update_ssg_eg
subs r6, r6, #2 subs r6, r6, #2
subne lr, lr, #4 addne lr, lr, #4
subne r5, r5, #SLOT_STRUCT_SIZE subne r5, r5, #SLOT_STRUCT_SIZE
#endif #endif
bne ssg_upd_loop bne ssg_upd_loop
@ -861,8 +870,9 @@ crl_smp_loop_end:
cmn r1, r0, asr #13 cmn r1, r0, asr #13
subne r0, r1, #0x80000001 subne r0, r1, #0x80000001
movne r0, r0, asr #18 movne r0, r0, asr #18
tst r4, r1, lsl #7 @ (sample < 0) && dac? tst r4, #0x80 @ dac?
bicne r0, r0, #0x1f bicne r0, r0, #0x1f
tst r4, r1, lsl #7 @ (sample < 0) && dac?
subne r0, r0, #7<<5 subne r0, r0, #7<<5
tst r12, #1 tst r12, #1
beq ctl_sample_mono beq ctl_sample_mono