mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-10-27 05:29:39 +01:00
remove regs union due to compiler issues
GP2X toolchains are padding the unions no matter what :(
This commit is contained in:
notaz
parent
9770f5316f
commit
f47d0a2898
5 changed files with 144 additions and 160 deletions
184
pico/cd/cdc.c
184
pico/cd/cdc.c
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@ -80,10 +80,10 @@ typedef struct
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{
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uint8 ifstat;
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uint8 ifctrl;
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reg16_t dbc;
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reg16_t dac;
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reg16_t pt;
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reg16_t wa;
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uint16 dbc;
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uint16 dac;
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uint16 pt;
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uint16 wa;
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uint8 ctrl[2];
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uint8 head[2][4];
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uint8 stat[4];
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@ -103,7 +103,7 @@ void cdc_init(void)
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void cdc_reset(void)
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{
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/* reset CDC register index */
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Pico_mcd->regs[0x04>>1].byte.l = 0x00;
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Pico_mcd->s68k_regs[0x04+1] = 0x00;
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/* reset CDC registers */
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cdc.ifstat = 0xff;
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@ -216,7 +216,7 @@ int cdc_context_load_old(uint8 *state)
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old_load(stat, 67916);
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cdc.dma_w = 0;
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switch (Pico_mcd->regs[0x04>>1].byte.h & 0x07)
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switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
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{
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case 4: /* PCM RAM DMA */
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cdc.dma_w = pcm_ram_dma_w;
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@ -225,16 +225,16 @@ int cdc_context_load_old(uint8 *state)
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cdc.dma_w = prg_ram_dma_w;
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break;
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case 7: /* WORD-RAM DMA */
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x04)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
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{
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x01)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
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cdc.dma_w = word_ram_0_dma_w;
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else
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cdc.dma_w = word_ram_1_dma_w;
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}
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else
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{
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x02)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
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cdc.dma_w = word_ram_2M_dma_w;
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}
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break;
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@ -247,7 +247,7 @@ int cdc_context_load_old(uint8 *state)
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static void do_dma(enum dma_type type, int words_in)
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{
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int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b];
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int src_addr = cdc.dac.w & 0x3ffe;
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int src_addr = cdc.dac & 0x3ffe;
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int dst_addr = dma_addr;
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int words = words_in;
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int dst_limit = 0;
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@ -255,7 +255,7 @@ static void do_dma(enum dma_type type, int words_in)
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int len;
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elprintf(EL_CD, "dma %d %04x->%04x %x",
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type, cdc.dac.w, dst_addr, words_in);
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type, cdc.dac, dst_addr, words_in);
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switch (type)
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{
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@ -331,7 +331,7 @@ static void do_dma(enum dma_type type, int words_in)
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update_dma:
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/* update DMA addresses */
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cdc.dac.w += words_in * 2;
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cdc.dac += words_in * 2;
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if (type == pcm_ram_dma_w)
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dma_addr += words_in >> 1;
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else
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@ -344,14 +344,14 @@ update_dma:
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void cdc_dma_update(void)
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{
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/* end of DMA transfer ? */
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//if (cdc.dbc.w < DMA_BYTES_PER_LINE)
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//if (cdc.dbc < DMA_BYTES_PER_LINE)
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{
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/* transfer remaining words using 16-bit DMA */
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//cdc.dma_w((cdc.dbc.w + 1) >> 1);
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do_dma(cdc.dma_w, (cdc.dbc.w + 1) >> 1);
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//cdc.dma_w((cdc.dbc + 1) >> 1);
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do_dma(cdc.dma_w, (cdc.dbc + 1) >> 1);
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/* reset data byte counter (DBCH bits 4-7 should be set to 1) */
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cdc.dbc.w = 0xf000;
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cdc.dbc = 0xf000;
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/* clear !DTEN and !DTBSY */
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cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
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@ -363,7 +363,7 @@ void cdc_dma_update(void)
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5)
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DTE irq 5");
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@ -372,7 +372,7 @@ void cdc_dma_update(void)
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}
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/* clear DSR bit & set EDT bit (SCD register $04) */
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Pico_mcd->regs[0x04>>1].byte.h = (Pico_mcd->regs[0x04>>1].byte.h & 0x07) | 0x80;
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Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
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/* disable DMA transfer */
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cdc.dma_w = 0;
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@ -384,7 +384,7 @@ void cdc_dma_update(void)
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cdc.dma_w(DMA_BYTES_PER_LINE >> 1);
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/* decrement data byte counter */
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cdc.dbc.w -= length;
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cdc.dbc -= length;
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}
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#endif
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}
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@ -407,7 +407,7 @@ int cdc_decoder_update(uint8 header[4])
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if (cdc.ifctrl & BIT_DECIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5)
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DEC irq 5");
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@ -421,13 +421,13 @@ int cdc_decoder_update(uint8 header[4])
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uint16 offset;
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/* increment block pointer */
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cdc.pt.w += 2352;
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cdc.pt += 2352;
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/* increment write address */
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cdc.wa.w += 2352;
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cdc.wa += 2352;
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/* CDC buffer address */
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offset = cdc.pt.w & 0x3fff;
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offset = cdc.pt & 0x3fff;
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/* write CDD block header (4 bytes) */
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memcpy(cdc.ram + offset, header, 4);
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@ -454,9 +454,9 @@ int cdc_decoder_update(uint8 header[4])
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void cdc_reg_w(unsigned char data)
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{
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#ifdef LOG_CDC
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elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->regs[0x04>>1].byte.l & 0x0F, data);
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elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->s68k_regs[0x04+1] & 0x0F, data);
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#endif
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switch (Pico_mcd->regs[0x04>>1].byte.l & 0x0F)
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
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{
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case 0x01: /* IFCTRL */
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{
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@ -465,7 +465,7 @@ void cdc_reg_w(unsigned char data)
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((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI)))
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5)
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc pending irq 5");
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@ -486,28 +486,32 @@ void cdc_reg_w(unsigned char data)
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}
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cdc.ifctrl = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x02;
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Pico_mcd->s68k_regs[0x04+1] = 0x02;
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break;
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}
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case 0x02: /* DBCL */
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cdc.dbc.byte.l = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x03;
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cdc.dbc &= 0xff00;
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cdc.dbc |= data;
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Pico_mcd->s68k_regs[0x04+1] = 0x03;
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break;
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case 0x03: /* DBCH */
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cdc.dbc.byte.h = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x04;
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cdc.dbc &= 0x00ff;
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cdc.dbc |= data << 8;
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Pico_mcd->s68k_regs[0x04+1] = 0x04;
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break;
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case 0x04: /* DACL */
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cdc.dac.byte.l = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x05;
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cdc.dac &= 0xff00;
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cdc.dac |= data;
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Pico_mcd->s68k_regs[0x04+1] = 0x05;
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break;
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case 0x05: /* DACH */
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cdc.dac.byte.h = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x06;
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cdc.dac &= 0x00ff;
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cdc.dac |= data << 8;
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Pico_mcd->s68k_regs[0x04+1] = 0x06;
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break;
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case 0x06: /* DTRG */
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@ -519,15 +523,15 @@ void cdc_reg_w(unsigned char data)
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cdc.ifstat &= ~BIT_DTBSY;
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/* clear DBCH bits 4-7 */
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cdc.dbc.byte.h &= 0x0f;
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cdc.dbc &= 0x0fff;
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/* clear EDT & DSR bits (SCD register $04) */
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Pico_mcd->regs[0x04>>1].byte.h &= 0x07;
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Pico_mcd->s68k_regs[0x04+0] &= 0x07;
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cdc.dma_w = 0;
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/* setup data transfer destination */
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switch (Pico_mcd->regs[0x04>>1].byte.h & 0x07)
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switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
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{
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case 2: /* MAIN-CPU host read */
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case 3: /* SUB-CPU host read */
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@ -536,7 +540,7 @@ void cdc_reg_w(unsigned char data)
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cdc.ifstat &= ~BIT_DTEN;
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/* set DSR bit (register $04) */
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Pico_mcd->regs[0x04>>1].byte.h |= 0x40;
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Pico_mcd->s68k_regs[0x04+0] |= 0x40;
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break;
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}
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@ -555,10 +559,10 @@ void cdc_reg_w(unsigned char data)
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case 7: /* WORD-RAM DMA */
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{
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/* check memory mode */
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x04)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
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{
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/* 1M mode */
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x01)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
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{
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/* Word-RAM bank 0 is assigned to SUB-CPU */
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cdc.dma_w = word_ram_0_dma_w;
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@ -572,7 +576,7 @@ void cdc_reg_w(unsigned char data)
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else
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{
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/* 2M mode */
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if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x02)
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if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
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{
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/* only process DMA if Word-RAM is assigned to SUB-CPU */
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cdc.dma_w = word_ram_2M_dma_w;
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@ -584,16 +588,16 @@ void cdc_reg_w(unsigned char data)
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default: /* invalid */
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{
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elprintf(EL_ANOMALY, "invalid CDC tranfer destination (%d)",
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Pico_mcd->regs[0x04>>1].byte.h & 0x07);
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Pico_mcd->s68k_regs[0x04+0] & 0x07);
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break;
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}
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}
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if (cdc.dma_w)
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pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc.w / 2);
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pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc / 2);
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}
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Pico_mcd->regs[0x04>>1].byte.l = 0x07;
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Pico_mcd->s68k_regs[0x04+1] = 0x07;
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break;
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}
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@ -603,7 +607,7 @@ void cdc_reg_w(unsigned char data)
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cdc.ifstat |= BIT_DTEI;
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/* clear DBCH bits 4-7 */
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cdc.dbc.byte.h &= 0x0f;
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cdc.dbc &= 0x0fff;
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#if 0
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/* no pending decoder interrupt ? */
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@ -613,18 +617,20 @@ void cdc_reg_w(unsigned char data)
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SekInterruptClearS68k(5);
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}
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#endif
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Pico_mcd->regs[0x04>>1].byte.l = 0x08;
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Pico_mcd->s68k_regs[0x04+1] = 0x08;
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break;
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}
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case 0x08: /* WAL */
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cdc.wa.byte.l = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x09;
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cdc.wa &= 0xff00;
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cdc.wa |= data;
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Pico_mcd->s68k_regs[0x04+1] = 0x09;
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break;
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case 0x09: /* WAH */
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cdc.wa.byte.h = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x0a;
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cdc.wa &= 0x00ff;
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cdc.wa |= data << 8;
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Pico_mcd->s68k_regs[0x04+1] = 0x0a;
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break;
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case 0x0a: /* CTRL0 */
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@ -645,7 +651,7 @@ void cdc_reg_w(unsigned char data)
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}
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cdc.ctrl[0] = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x0b;
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Pico_mcd->s68k_regs[0x04+1] = 0x0b;
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break;
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}
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@ -664,22 +670,24 @@ void cdc_reg_w(unsigned char data)
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}
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cdc.ctrl[1] = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x0c;
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Pico_mcd->s68k_regs[0x04+1] = 0x0c;
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break;
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}
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case 0x0c: /* PTL */
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cdc.pt.byte.l = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x0d;
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cdc.pt &= 0xff00;
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cdc.pt |= data;
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Pico_mcd->s68k_regs[0x04+1] = 0x0d;
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break;
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case 0x0d: /* PTH */
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cdc.pt.byte.h = data;
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Pico_mcd->regs[0x04>>1].byte.l = 0x0e;
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cdc.pt &= 0x00ff;
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cdc.pt |= data << 8;
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Pico_mcd->s68k_regs[0x04+1] = 0x0e;
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break;
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case 0x0e: /* CTRL2 (unused) */
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Pico_mcd->regs[0x04>>1].byte.l = 0x0f;
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Pico_mcd->s68k_regs[0x04+1] = 0x0f;
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break;
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case 0x0f: /* RESET */
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@ -693,62 +701,62 @@ void cdc_reg_w(unsigned char data)
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unsigned char cdc_reg_r(void)
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{
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switch (Pico_mcd->regs[0x04>>1].byte.l & 0x0F)
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
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{
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case 0x01: /* IFSTAT */
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Pico_mcd->regs[0x04>>1].byte.l = 0x02;
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Pico_mcd->s68k_regs[0x04+1] = 0x02;
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return cdc.ifstat;
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case 0x02: /* DBCL */
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Pico_mcd->regs[0x04>>1].byte.l = 0x03;
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return cdc.dbc.byte.l;
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Pico_mcd->s68k_regs[0x04+1] = 0x03;
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return cdc.dbc & 0xff;
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case 0x03: /* DBCH */
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Pico_mcd->regs[0x04>>1].byte.l = 0x04;
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return cdc.dbc.byte.h;
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Pico_mcd->s68k_regs[0x04+1] = 0x04;
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return (cdc.dbc >> 8) & 0xff;
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case 0x04: /* HEAD0 */
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Pico_mcd->regs[0x04>>1].byte.l = 0x05;
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Pico_mcd->s68k_regs[0x04+1] = 0x05;
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return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0];
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case 0x05: /* HEAD1 */
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Pico_mcd->regs[0x04>>1].byte.l = 0x06;
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Pico_mcd->s68k_regs[0x04+1] = 0x06;
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return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1];
|
||||
|
||||
case 0x06: /* HEAD2 */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x07;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x07;
|
||||
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2];
|
||||
|
||||
case 0x07: /* HEAD3 */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x08;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x08;
|
||||
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3];
|
||||
|
||||
case 0x08: /* PTL */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x09;
|
||||
return cdc.pt.byte.l;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x09;
|
||||
return cdc.pt & 0xff;
|
||||
|
||||
case 0x09: /* PTH */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0a;
|
||||
return cdc.pt.byte.h;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0a;
|
||||
return (cdc.pt >> 8) & 0xff;
|
||||
|
||||
case 0x0a: /* WAL */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0b;
|
||||
return cdc.wa.byte.l;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0b;
|
||||
return cdc.wa & 0xff;
|
||||
|
||||
case 0x0b: /* WAH */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0c;
|
||||
return cdc.wa.byte.h;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0c;
|
||||
return (cdc.wa >> 8) & 0xff;
|
||||
|
||||
case 0x0c: /* STAT0 */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0d;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0d;
|
||||
return cdc.stat[0];
|
||||
|
||||
case 0x0d: /* STAT1 (always return 0) */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0e;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0e;
|
||||
return 0x00;
|
||||
|
||||
case 0x0e: /* STAT2 */
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x0f;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x0f;
|
||||
return cdc.stat[2];
|
||||
|
||||
case 0x0f: /* STAT3 */
|
||||
|
|
@ -770,7 +778,7 @@ unsigned char cdc_reg_r(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
Pico_mcd->regs[0x04>>1].byte.l = 0x00;
|
||||
Pico_mcd->s68k_regs[0x04+1] = 0x00;
|
||||
return data;
|
||||
}
|
||||
|
||||
|
|
@ -785,24 +793,24 @@ unsigned short cdc_host_r(void)
|
|||
if (!(cdc.ifstat & BIT_DTEN))
|
||||
{
|
||||
/* read data word from CDC RAM buffer */
|
||||
uint8 *datap = cdc.ram + (cdc.dac.w & 0x3ffe);
|
||||
uint8 *datap = cdc.ram + (cdc.dac & 0x3ffe);
|
||||
uint16 data = (datap[0] << 8) | datap[1];
|
||||
|
||||
#ifdef LOG_CDC
|
||||
error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac.w, data, cdc.dbc.w, s68k.pc);
|
||||
error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac, data, cdc.dbc, s68k.pc);
|
||||
#endif
|
||||
|
||||
/* increment data address counter */
|
||||
cdc.dac.w += 2;
|
||||
cdc.dac += 2;
|
||||
|
||||
/* decrement data byte counter */
|
||||
cdc.dbc.w -= 2;
|
||||
cdc.dbc -= 2;
|
||||
|
||||
/* end of transfer ? */
|
||||
if ((int16)cdc.dbc.w <= 0)
|
||||
if ((int16)cdc.dbc <= 0)
|
||||
{
|
||||
/* reset data byte counter (DBCH bits 4-7 should be set to 1) */
|
||||
cdc.dbc.w = 0xf000;
|
||||
cdc.dbc = 0xf000;
|
||||
|
||||
/* clear !DTEN and !DTBSY */
|
||||
cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
|
||||
|
|
@ -814,7 +822,7 @@ unsigned short cdc_host_r(void)
|
|||
if (cdc.ifctrl & BIT_DTEIEN)
|
||||
{
|
||||
/* level 5 interrupt enabled ? */
|
||||
if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5)
|
||||
if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
|
||||
{
|
||||
/* update IRQ level */
|
||||
elprintf(EL_INTS, "cdc DTE irq 5");
|
||||
|
|
@ -823,7 +831,7 @@ unsigned short cdc_host_r(void)
|
|||
}
|
||||
|
||||
/* clear DSR bit & set EDT bit (SCD register $04) */
|
||||
Pico_mcd->regs[0x04>>1].byte.h = (Pico_mcd->regs[0x04>>1].byte.h & 0x07) | 0x80;
|
||||
Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
|
||||
}
|
||||
|
||||
return data;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue