mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: drc: new smc handling, write handlers adjusted.
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@820 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
2b2b46b05d
commit
f4bb5d6b2c
9 changed files with 389 additions and 150 deletions
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@ -5,7 +5,7 @@
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#include "cmn.h"
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u32 __attribute__((aligned(4096))) tcache[DRC_TCACHE_SIZE/4];
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u8 __attribute__((aligned(4096))) tcache[DRC_TCACHE_SIZE];
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void drc_cmn_init(void)
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@ -4,7 +4,7 @@ typedef unsigned int u32;
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#define DRC_TCACHE_SIZE (512*1024)
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extern u32 tcache[DRC_TCACHE_SIZE/4];
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extern u8 tcache[DRC_TCACHE_SIZE];
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void drc_cmn_init(void);
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void drc_cmn_cleanup(void);
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@ -7,6 +7,8 @@
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#define COUNT_OP
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#endif
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enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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// TODO: move
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static int reg_map_g2h[] = {
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-1, -1, -1, -1,
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@ -17,14 +19,14 @@ static int reg_map_g2h[] = {
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-1, -1, -1, -1,
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};
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enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define CONTEXT_REG xBP
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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#define EMIT(val, type) { \
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EMIT_PTR(tcache_ptr, val, type); \
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tcache_ptr = (char *)tcache_ptr + sizeof(type); \
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tcache_ptr += sizeof(type); \
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}
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#define EMIT_OP(op) { \
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@ -99,32 +101,29 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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}
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#define EMIT_CONDITIONAL(code, is_nonzero) { \
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char *ptr = tcache_ptr; \
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tcache_ptr = (char *)tcache_ptr + 2; \
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u8 *ptr = tcache_ptr; \
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tcache_ptr = tcache_ptr + 2; \
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code; \
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EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \
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EMIT_PTR(ptr + 1, ((char *)tcache_ptr - (ptr + 2)), u8); \
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EMIT_PTR(ptr + 1, (tcache_ptr - (ptr + 2)), u8); \
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}
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static void emith_pass_arg(int count, ...)
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{
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va_list vl;
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int i;
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va_start(vl, count);
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for (i = 0; i < count; i++) {
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long av = va_arg(vl, long);
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int r = 7;
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switch (i) {
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case 0: r = xAX; break;
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case 1: r = xDX; break;
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case 2: r = xCX; break;
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}
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emith_move_r_imm(r, av);
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#define arg2reg(rd, arg) \
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switch (arg) { \
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case 0: rd = xAX; break; \
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case 1: rd = xDX; break; \
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case 2: rd = xCX; break; \
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}
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va_end(vl);
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#define emith_pass_arg_r(arg, reg) { \
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int rd = 7; \
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arg2reg(rd, arg); \
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emith_move_r_r(rd, reg); \
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}
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#define emith_pass_arg_imm(arg, imm) { \
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int rd = 7; \
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arg2reg(rd, arg); \
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emith_move_r_imm(rd, imm); \
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}
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@ -5,6 +5,7 @@
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#include <stdlib.h>
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#include <assert.h>
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#include "../../pico/pico_int.h"
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#include "sh2.h"
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#include "compiler.h"
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#include "../drc/cmn.h"
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@ -13,19 +14,43 @@
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#define DRC_DEBUG 0
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#endif
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#define dbg(l,...) { \
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if ((l) & DRC_DEBUG) \
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elprintf(EL_STATUS, ##__VA_ARGS__); \
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}
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#if DRC_DEBUG
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#include "mame/sh2dasm.h"
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#include <platform/linux/host_dasm.h>
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static int insns_compiled, hash_collisions, host_insn_count;
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#endif
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#if (DRC_DEBUG & 2)
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static void *tcache_dsm_ptr = tcache;
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static u8 *tcache_dsm_ptrs[3];
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static char sh2dasm_buff[64];
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#define do_host_disasm(tcid) \
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host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
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tcache_dsm_ptrs[tcid] = tcache_ptr
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#else
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#define do_host_disasm(x)
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#endif
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#define BLOCK_CYCLE_LIMIT 100
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#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
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static void *tcache_ptr;
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// we have 3 translation cache buffers, split from one drc/cmn buffer.
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// BIOS shares tcache with data array because it's only used for init
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// and can be discarded early
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static const int tcache_sizes[3] = {
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DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
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DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
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DRC_TCACHE_SIZE / 8, // ... slave
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};
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static u8 *tcache_bases[3];
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static u8 *tcache_ptrs[3];
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// ptr for code emiters
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static u8 *tcache_ptr;
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#include "../drc/emit_x86.c"
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@ -37,16 +62,26 @@ typedef enum {
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typedef struct block_desc_ {
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u32 addr; // SH2 PC address
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u32 end_addr; // TODO rm?
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void *tcache_ptr; // translated block for above PC
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struct block_desc_ *next; // next block with the same PC hash
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struct block_desc_ *next; // next block with the same PC hash
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#if (DRC_DEBUG & 1)
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int refcount;
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#endif
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} block_desc;
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#define MAX_BLOCK_COUNT (4*1024)
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static block_desc *block_table;
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static int block_count;
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static const int block_max_counts[3] = {
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4*1024,
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256,
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256,
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};
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static block_desc *block_tables[3];
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static int block_counts[3];
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// ROM hash table
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#define MAX_HASH_ENTRIES 1024
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#define HASH_MASK (MAX_HASH_ENTRIES - 1)
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static void **hash_table;
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extern void sh2_drc_entry(SH2 *sh2, void *block);
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extern void sh2_drc_exit(void);
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@ -55,6 +90,25 @@ extern void sh2_drc_exit(void);
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extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode);
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static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2);
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static void flush_tcache(int tcid)
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{
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printf("tcache #%d flush! (%d/%d, bds %d/%d)\n", tcid,
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tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
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block_counts[tcid], block_max_counts[tcid]);
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block_counts[tcid] = 0;
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tcache_ptrs[tcid] = tcache_bases[tcid];
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if (tcid == 0) { // ROM, RAM
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memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
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memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
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}
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else
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memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
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#if (DRC_DEBUG & 2)
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tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
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#endif
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}
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static void *dr_find_block(block_desc *tab, u32 addr)
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{
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for (tab = tab->next; tab != NULL; tab = tab->next)
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@ -68,20 +122,19 @@ static void *dr_find_block(block_desc *tab, u32 addr)
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return NULL;
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}
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static block_desc *dr_add_block(u32 addr, void *tcache_ptr)
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static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
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{
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int *bcount = &block_counts[tcache_id];
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block_desc *bd;
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if (block_count == MAX_BLOCK_COUNT) {
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// FIXME: flush cache instead
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printf("block descriptor overflow\n");
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exit(1);
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}
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if (*bcount >= block_max_counts[tcache_id])
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return NULL;
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bd = &block_table[block_count];
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bd = &block_tables[tcache_id][*bcount];
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bd->addr = addr;
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bd->tcache_ptr = tcache_ptr;
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block_count++;
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*blk_id = *bcount;
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(*bcount)++;
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return bd;
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}
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@ -162,22 +215,46 @@ static int sh2_translate_op4(int op)
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static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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{
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void *block_entry = tcache_ptr;
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void *block_entry;
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block_desc *this_block;
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unsigned int pc = sh2->pc;
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int op, delayed_op = 0, test_irq = 0;
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int tcache_id = 0, blkid = 0;
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int cycles = 0;
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u32 tmp, tmp2;
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this_block = dr_add_block(pc, block_entry);
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if (other_block != NULL)
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this_block->next = other_block;
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// validate PC
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tmp = sh2->pc >> 29;
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if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) {
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printf("invalid PC, aborting: %08x\n", sh2->pc);
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// FIXME: be less destructive
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exit(1);
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}
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HASH_FUNC(sh2->pc_hashtab, pc) = this_block;
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if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
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// data_array, BIOS have separate tcache (shared)
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tcache_id = 1 + sh2->is_slave;
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}
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tcache_ptr = tcache_ptrs[tcache_id];
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this_block = dr_add_block(pc, tcache_id, &blkid);
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tmp = tcache_ptr - tcache_bases[tcache_id];
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if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) {
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flush_tcache(tcache_id);
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tcache_ptr = tcache_ptrs[tcache_id];
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other_block = NULL; // also gone too due to flush
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this_block = dr_add_block(pc, tcache_id, &blkid);
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}
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this_block->next = other_block;
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if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
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HASH_FUNC(hash_table, pc) = this_block;
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block_entry = tcache_ptr;
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#if (DRC_DEBUG & 1)
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printf("== %csh2 block #%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
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block_count, pc, block_entry);
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printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
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tcache_id, block_counts[tcache_id], pc, block_entry);
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if (other_block != NULL) {
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printf(" hash collision with %08x\n", other_block->addr);
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hash_collisions++;
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@ -231,7 +308,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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// RTE 0000000000101011
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//emit_move_r_r(SHR_PC, SHR_PR);
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emit_move_r_imm32(SHR_PC, pc - 2);
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emith_pass_arg(2, sh2, op);
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_pass_arg_imm(1, op);
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emith_call(sh2_do_op);
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emit_move_r_r(SHR_PPC, SHR_PC);
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test_irq = 1;
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@ -312,7 +390,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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default:
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default_:
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emit_move_r_imm32(SHR_PC, pc - 2);
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emith_pass_arg(2, sh2, op);
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_pass_arg_imm(1, op);
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emith_call(sh2_do_op);
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break;
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}
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@ -322,24 +401,41 @@ end_op:
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emit_move_r_r(SHR_PC, SHR_PPC);
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if (test_irq && delayed_op != 2) {
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emith_pass_arg(1, sh2);
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_call(sh2_test_irq);
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break;
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}
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if (delayed_op == 1)
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break;
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#if (DRC_DEBUG & 2)
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host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
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tcache_dsm_ptr = tcache_ptr;
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#endif
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do_host_disasm(tcache_id);
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}
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end_block:
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if ((char *)tcache_ptr - (char *)tcache > DRC_TCACHE_SIZE) {
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printf("tcache overflow!\n");
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fflush(stdout);
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exit(1);
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this_block->end_addr = pc;
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// mark memory blocks as containing compiled code
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if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
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// data array, BIOS
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u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
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tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
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tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
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Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1;
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for (++tmp; tmp < tmp2; tmp++) {
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if (drcblk[tmp])
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break; // dont overwrite overlay block
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drcblk[tmp] = blkid << 1;
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}
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}
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else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
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tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
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tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
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Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1;
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for (++tmp; tmp < tmp2; tmp++) {
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if (Pico32xMem->drcblk_ram[tmp])
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break;
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Pico32xMem->drcblk_ram[tmp] = blkid << 1;
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}
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}
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if (reg_map_g2h[SHR_SR] == -1) {
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@ -347,26 +443,22 @@ end_block:
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} else
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emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12);
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emith_jump(sh2_drc_exit);
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tcache_ptrs[tcache_id] = tcache_ptr;
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#if (DRC_DEBUG & 2)
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host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
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tcache_dsm_ptr = tcache_ptr;
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#endif
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#if (DRC_DEBUG & 1)
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printf(" tcache %d/%d, hash collisions %d/%d, insns %d -> %d %.3f\n",
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(char *)tcache_ptr - (char *)tcache, DRC_TCACHE_SIZE,
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hash_collisions, block_count, insns_compiled, host_insn_count,
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(double)host_insn_count / insns_compiled);
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#endif
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do_host_disasm(tcache_id);
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dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
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tcache_id, block_counts[tcache_id],
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tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
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insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
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if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
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dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
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return block_entry;
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/*
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unimplemented:
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// last op
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#if (DRC_DEBUG & 2)
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host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
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tcache_dsm_ptr = tcache_ptr;
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#endif
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do_host_disasm(tcache_id);
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exit(1);
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*/
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}
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void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
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@ -374,30 +466,95 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
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while (((signed int)sh2->sr >> 12) > 0)
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{
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void *block = NULL;
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block_desc *bd;
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block_desc *bd = NULL;
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// FIXME: must avoid doing it so often..
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sh2_test_irq(sh2);
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bd = HASH_FUNC(sh2->pc_hashtab, sh2->pc);
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if (bd != NULL) {
|
||||
if (bd->addr == sh2->pc)
|
||||
// we have full block id tables for data_array and RAM
|
||||
// BIOS goes to data_array table too
|
||||
if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
|
||||
int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
|
||||
if (blkid & 1) {
|
||||
bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
|
||||
block = bd->tcache_ptr;
|
||||
else
|
||||
block = dr_find_block(bd, sh2->pc);
|
||||
}
|
||||
}
|
||||
// RAM
|
||||
else if ((sh2->pc & 0xc6000000) == 0x06000000) {
|
||||
int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
|
||||
if (blkid & 1) {
|
||||
bd = &block_tables[0][blkid >> 1];
|
||||
block = bd->tcache_ptr;
|
||||
}
|
||||
}
|
||||
// ROM
|
||||
else if ((sh2->pc & 0xc6000000) == 0x02000000) {
|
||||
bd = HASH_FUNC(hash_table, sh2->pc);
|
||||
|
||||
if (bd != NULL) {
|
||||
if (bd->addr == sh2->pc)
|
||||
block = bd->tcache_ptr;
|
||||
else
|
||||
block = dr_find_block(bd, sh2->pc);
|
||||
}
|
||||
}
|
||||
|
||||
if (block == NULL)
|
||||
block = sh2_translate(sh2, bd);
|
||||
|
||||
#if (DRC_DEBUG & 4)
|
||||
printf("= %csh2 enter %08x %p\n", sh2->is_slave ? 's' : 'm', sh2->pc, block);
|
||||
dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
|
||||
sh2->pc, block, (signed int)sh2->sr >> 12);
|
||||
#if (DRC_DEBUG & 1)
|
||||
if (bd != NULL)
|
||||
bd->refcount++;
|
||||
#endif
|
||||
sh2_drc_entry(sh2, block);
|
||||
}
|
||||
}
|
||||
|
||||
static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
|
||||
{
|
||||
u16 id = *p >> 1;
|
||||
block_desc *bd = btab + id;
|
||||
|
||||
dbg(1, " killing block %08x", bd->addr);
|
||||
bd->addr = bd->end_addr = 0;
|
||||
|
||||
while (p > drcblk && (p[-1] >> 1) == id)
|
||||
p--;
|
||||
|
||||
// check for possible overlay block
|
||||
if (p > 0 && p[-1] != 0) {
|
||||
bd = btab + (p[-1] >> 1);
|
||||
if (bd->addr <= a && a < bd->end_addr)
|
||||
sh2_smc_rm_block(drcblk, p - 1, btab, a);
|
||||
}
|
||||
|
||||
do {
|
||||
*p++ = 0;
|
||||
}
|
||||
while ((*p >> 1) == id);
|
||||
}
|
||||
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
|
||||
{
|
||||
u16 *drcblk = Pico32xMem->drcblk_ram;
|
||||
u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
|
||||
|
||||
dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
|
||||
sh2_smc_rm_block(drcblk, p, block_tables[0], a);
|
||||
}
|
||||
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
|
||||
{
|
||||
u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
|
||||
u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
|
||||
|
||||
dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
|
||||
sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
|
||||
}
|
||||
|
||||
void sh2_execute(SH2 *sh2, int cycles)
|
||||
{
|
||||
sh2->cycles_aim += cycles;
|
||||
|
|
@ -425,35 +582,84 @@ static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2)
|
|||
}
|
||||
}
|
||||
|
||||
#if (DRC_DEBUG & 1)
|
||||
static void block_stats(void)
|
||||
{
|
||||
int c, b, i, total = 0;
|
||||
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++)
|
||||
for (i = 0; i < block_counts[b]; i++)
|
||||
if (block_tables[b][i].addr != 0)
|
||||
total += block_tables[b][i].refcount;
|
||||
|
||||
for (c = 0; c < 10; c++) {
|
||||
block_desc *blk, *maxb = NULL;
|
||||
int max = 0;
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
for (i = 0; i < block_counts[b]; i++) {
|
||||
blk = &block_tables[b][i];
|
||||
if (blk->addr != 0 && blk->refcount > max) {
|
||||
max = blk->refcount;
|
||||
maxb = blk;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (maxb == NULL)
|
||||
break;
|
||||
printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
|
||||
(double)maxb->refcount / total * 100.0);
|
||||
maxb->refcount = 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int sh2_drc_init(SH2 *sh2)
|
||||
{
|
||||
if (block_table == NULL) {
|
||||
block_count = 0;
|
||||
block_table = calloc(MAX_BLOCK_COUNT, sizeof(*block_table));
|
||||
if (block_table == NULL)
|
||||
if (block_tables[0] == NULL) {
|
||||
int i, cnt;
|
||||
cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
|
||||
block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
|
||||
if (block_tables[0] == NULL)
|
||||
return -1;
|
||||
|
||||
tcache_ptr = tcache;
|
||||
memset(block_counts, 0, sizeof(block_counts));
|
||||
tcache_bases[0] = tcache_ptrs[0] = tcache;
|
||||
|
||||
for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
|
||||
block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
|
||||
tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
|
||||
}
|
||||
|
||||
#if (DRC_DEBUG & 2)
|
||||
for (i = 0; i < ARRAY_SIZE(block_tables); i++)
|
||||
tcache_dsm_ptrs[i] = tcache_bases[i];
|
||||
#endif
|
||||
#if (DRC_DEBUG & 1)
|
||||
hash_collisions = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
//assert(sh2->pc_hashtab == NULL);
|
||||
sh2->pc_hashtab = calloc(sizeof(sh2->pc_hashtab[0]), MAX_HASH_ENTRIES);
|
||||
if (sh2->pc_hashtab == NULL)
|
||||
return -1;
|
||||
if (hash_table == NULL) {
|
||||
hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
|
||||
if (hash_table == NULL)
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sh2_drc_finish(SH2 *sh2)
|
||||
{
|
||||
if (block_table != NULL) {
|
||||
free(block_table);
|
||||
block_table = NULL;
|
||||
if (block_tables[0] != NULL) {
|
||||
#if (DRC_DEBUG & 1)
|
||||
block_stats();
|
||||
#endif
|
||||
free(block_tables[0]);
|
||||
memset(block_tables, 0, sizeof(block_tables));
|
||||
}
|
||||
|
||||
free(sh2->pc_hashtab);
|
||||
sh2->pc_hashtab = NULL;
|
||||
if (hash_table != NULL) {
|
||||
free(hash_table);
|
||||
hash_table = NULL;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
int sh2_drc_init(SH2 *sh2);
|
||||
void sh2_drc_finish(SH2 *sh2);
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid);
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid);
|
||||
|
||||
|
|
|
|||
|
|
@ -18,13 +18,13 @@ typedef struct
|
|||
unsigned int test_irq;
|
||||
|
||||
// common
|
||||
void *read8_map; // 70
|
||||
void *read16_map;
|
||||
void *write8_map;
|
||||
void *write16_map;
|
||||
const void *read8_map; // 70
|
||||
const void *read16_map;
|
||||
const void **write8_tab;
|
||||
const void **write16_tab;
|
||||
|
||||
// drc stuff
|
||||
void **pc_hashtab; // 80
|
||||
//void **pc_hashtab; // 80
|
||||
|
||||
int pending_level; // MAX(pending_irl, pending_int_irq)
|
||||
int pending_irl;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue