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sh2: sync sh2 core with latest mame

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This commit is contained in:
notaz 2013-07-13 02:44:16 +03:00
parent 009ef50c60
commit f4c0720c24
7 changed files with 594 additions and 576 deletions
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1
cpu/sh2/compiler.c
View file

@ -2991,7 +2991,6 @@ void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
int sh2_execute(SH2 *sh2c, int cycles) int sh2_execute(SH2 *sh2c, int cycles)
{ {
int ret_cycles; int ret_cycles;
sh2 = sh2c; // XXX
sh2c->cycles_timeslice = cycles; sh2c->cycles_timeslice = cycles;

1035
cpu/sh2/mame/sh2.c
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File diff suppressed because it is too large Load diff

90
cpu/sh2/mame/sh2pico.c
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@ -8,12 +8,12 @@ typedef unsigned int UINT32;
typedef unsigned short UINT16; typedef unsigned short UINT16;
typedef unsigned char UINT8; typedef unsigned char UINT8;
#define RB(a) p32x_sh2_read8(a,sh2) #define RB(sh2, a) p32x_sh2_read8(a,sh2)
#define RW(a) p32x_sh2_read16(a,sh2) #define RW(sh2, a) p32x_sh2_read16(a,sh2)
#define RL(a) p32x_sh2_read32(a,sh2) #define RL(sh2, a) p32x_sh2_read32(a,sh2)
#define WB(a,d) p32x_sh2_write8(a,d,sh2) #define WB(sh2, a, d) p32x_sh2_write8(a,d,sh2)
#define WW(a,d) p32x_sh2_write16(a,d,sh2) #define WW(sh2, a, d) p32x_sh2_write16(a,d,sh2)
#define WL(a,d) p32x_sh2_write32(a,d,sh2) #define WL(sh2, a, d) p32x_sh2_write32(a,d,sh2)
// some stuff from sh2comn.h // some stuff from sh2comn.h
#define T 0x00000001 #define T 0x00000001
@ -29,7 +29,10 @@ typedef unsigned char UINT8;
#define Rn ((opcode>>8)&15) #define Rn ((opcode>>8)&15)
#define Rm ((opcode>>4)&15) #define Rm ((opcode>>4)&15)
#define sh2_icount sh2->icount #define sh2_state SH2
extern void lprintf(const char *fmt, ...);
#define logerror lprintf
#ifdef SH2_STATS #ifdef SH2_STATS
static SH2 sh2_stats; static SH2 sh2_stats;
@ -61,7 +64,7 @@ static unsigned int op_refs[0x10000];
#ifndef DRC_SH2 #ifndef DRC_SH2
int sh2_execute(SH2 *sh2_, int cycles) int sh2_execute(SH2 *sh2, int cycles)
{ {
sh2 = sh2_; sh2 = sh2_;
sh2->icount = cycles; sh2->icount = cycles;
@ -78,13 +81,13 @@ int sh2_execute(SH2 *sh2_, int cycles)
if (sh2->delay) if (sh2->delay)
{ {
sh2->ppc = sh2->delay; sh2->ppc = sh2->delay;
opcode = RW(sh2->delay); opcode = RW(sh2, sh2->delay);
sh2->pc -= 2; sh2->pc -= 2;
} }
else else
{ {
sh2->ppc = sh2->pc; sh2->ppc = sh2->pc;
opcode = RW(sh2->pc); opcode = RW(sh2, sh2->pc);
} }
sh2->delay = 0; sh2->delay = 0;
@ -92,22 +95,22 @@ int sh2_execute(SH2 *sh2_, int cycles)
switch (opcode & ( 15 << 12)) switch (opcode & ( 15 << 12))
{ {
case 0<<12: op0000(opcode); break; case 0<<12: op0000(sh2, opcode); break;
case 1<<12: op0001(opcode); break; case 1<<12: op0001(sh2, opcode); break;
case 2<<12: op0010(opcode); break; case 2<<12: op0010(sh2, opcode); break;
case 3<<12: op0011(opcode); break; case 3<<12: op0011(sh2, opcode); break;
case 4<<12: op0100(opcode); break; case 4<<12: op0100(sh2, opcode); break;
case 5<<12: op0101(opcode); break; case 5<<12: op0101(sh2, opcode); break;
case 6<<12: op0110(opcode); break; case 6<<12: op0110(sh2, opcode); break;
case 7<<12: op0111(opcode); break; case 7<<12: op0111(sh2, opcode); break;
case 8<<12: op1000(opcode); break; case 8<<12: op1000(sh2, opcode); break;
case 9<<12: op1001(opcode); break; case 9<<12: op1001(sh2, opcode); break;
case 10<<12: op1010(opcode); break; case 10<<12: op1010(sh2, opcode); break;
case 11<<12: op1011(opcode); break; case 11<<12: op1011(sh2, opcode); break;
case 12<<12: op1100(opcode); break; case 12<<12: op1100(sh2, opcode); break;
case 13<<12: op1101(opcode); break; case 13<<12: op1101(sh2, opcode); break;
case 14<<12: op1110(opcode); break; case 14<<12: op1110(sh2, opcode); break;
default: op1111(opcode); break; default: op1111(sh2, opcode); break;
} }
sh2->icount--; sh2->icount--;
@ -135,29 +138,28 @@ int sh2_execute(SH2 *sh2_, int cycles)
#endif #endif
// drc debug // drc debug
void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode) void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode)
{ {
sh2 = sh2_;
sh2->pc += 2; sh2->pc += 2;
switch (opcode & ( 15 << 12)) switch (opcode & ( 15 << 12))
{ {
case 0<<12: op0000(opcode); break; case 0<<12: op0000(sh2, opcode); break;
case 1<<12: op0001(opcode); break; case 1<<12: op0001(sh2, opcode); break;
case 2<<12: op0010(opcode); break; case 2<<12: op0010(sh2, opcode); break;
case 3<<12: op0011(opcode); break; case 3<<12: op0011(sh2, opcode); break;
case 4<<12: op0100(opcode); break; case 4<<12: op0100(sh2, opcode); break;
case 5<<12: op0101(opcode); break; case 5<<12: op0101(sh2, opcode); break;
case 6<<12: op0110(opcode); break; case 6<<12: op0110(sh2, opcode); break;
case 7<<12: op0111(opcode); break; case 7<<12: op0111(sh2, opcode); break;
case 8<<12: op1000(opcode); break; case 8<<12: op1000(sh2, opcode); break;
case 9<<12: op1001(opcode); break; case 9<<12: op1001(sh2, opcode); break;
case 10<<12: op1010(opcode); break; case 10<<12: op1010(sh2, opcode); break;
case 11<<12: op1011(opcode); break; case 11<<12: op1011(sh2, opcode); break;
case 12<<12: op1100(opcode); break; case 12<<12: op1100(sh2, opcode); break;
case 13<<12: op1101(opcode); break; case 13<<12: op1101(sh2, opcode); break;
case 14<<12: op1110(opcode); break; case 14<<12: op1110(sh2, opcode); break;
default: op1111(opcode); break; default: op1111(sh2, opcode); break;
} }
} }

2
cpu/sh2/sh2.c
View file

@ -14,8 +14,6 @@
#define I 0xf0 #define I 0xf0
SH2 *sh2; // active sh2
int sh2_init(SH2 *sh2, int is_slave) int sh2_init(SH2 *sh2, int is_slave)
{ {
int ret = 0; int ret = 0;

2
cpu/sh2/sh2.h
View file

@ -66,8 +66,6 @@ typedef struct SH2_
#define C_SH2_TO_M68K(xsh2, c) \ #define C_SH2_TO_M68K(xsh2, c) \
((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT) ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
extern SH2 *sh2; // active sh2. XXX: consider removing
int sh2_init(SH2 *sh2, int is_slave); int sh2_init(SH2 *sh2, int is_slave);
void sh2_finish(SH2 *sh2); void sh2_finish(SH2 *sh2);
void sh2_reset(SH2 *sh2); void sh2_reset(SH2 *sh2);

18
pico/32x/memory.c
View file

@ -454,8 +454,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
case 0x00: // adapter/irq ctl case 0x00: // adapter/irq ctl
return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
case 0x04: // H count (often as comm too) case 0x04: // H count (often as comm too)
if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
ash2_end_run(8); ash2_end_run(&sh2s[cpuid], 8);
return Pico32x.sh2_regs[4 / 2]; return Pico32x.sh2_regs[4 / 2];
case 0x10: // DREQ len case 0x10: // DREQ len
return r[a / 2]; return r[a / 2];
@ -469,8 +469,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
int comreg = 1 << (a & 0x0f) / 2; int comreg = 1 << (a & 0x0f) / 2;
if (Pico32x.comm_dirty_68k & comreg) if (Pico32x.comm_dirty_68k & comreg)
Pico32x.comm_dirty_68k &= ~comreg; Pico32x.comm_dirty_68k &= ~comreg;
else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
ash2_end_run(8); ash2_end_run(&sh2s[cpuid], 8);
return r[a / 2]; return r[a / 2];
} }
if ((a & 0x30) == 0x30) { if ((a & 0x30) == 0x30) {
@ -695,7 +695,7 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
dmac0->tcr0 &= 0xffffff; dmac0->tcr0 &= 0xffffff;
// HACK: assume 68k starts writing soon and end the timeslice // HACK: assume 68k starts writing soon and end the timeslice
ash2_end_run(16); ash2_end_run(&sh2s[id], 16);
// DREQ is only sent after first 4 words are written. // DREQ is only sent after first 4 words are written.
// we do multiple of 4 words to avoid messing up alignment // we do multiple of 4 words to avoid messing up alignment
@ -1016,8 +1016,8 @@ static u32 sh2_read8_cs0(u32 a, int id)
if ((a & 0x3ff00) == 0x4100) { if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a); d = p32x_vdp_read16(a);
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
ash2_end_run(8); ash2_end_run(&sh2s[id], 8);
goto out_16to8; goto out_16to8;
} }
@ -1071,8 +1071,8 @@ static u32 sh2_read16_cs0(u32 a, int id)
if ((a & 0x3ff00) == 0x4100) { if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a); d = p32x_vdp_read16(a);
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
ash2_end_run(8); ash2_end_run(&sh2s[id], 8);
goto out; goto out;
} }

22
pico/pico_int.h
View file

@ -237,23 +237,23 @@ extern SH2 sh2s[2];
#define ssh2 sh2s[1] #define ssh2 sh2s[1]
#ifndef DRC_SH2 #ifndef DRC_SH2
# define ash2_end_run(after) do { \ # define ash2_end_run(sh2, after) do { \
if (sh2->icount > (after)) { \ if ((sh2)->icount > (after)) { \
sh2->cycles_timeslice -= sh2->icount; \ (sh2)->cycles_timeslice -= (sh2)->icount; \
sh2->icount = after; \ (sh2)->icount = after; \
} \ } \
} while (0) } while (0)
# define ash2_cycles_done() (sh2->cycles_timeslice - sh2->icount) # define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - (sh2)->icount)
#else #else
# define ash2_end_run(after) do { \ # define ash2_end_run(sh2, after) do { \
int left = sh2->sr >> 12; \ int left = (sh2)->sr >> 12; \
if (left > (after)) { \ if (left > (after)) { \
sh2->cycles_timeslice -= left; \ (sh2)->cycles_timeslice -= left; \
sh2->sr &= 0xfff; \ (sh2)->sr &= 0xfff; \
sh2->sr |= (after) << 12; \ (sh2)->sr |= (after) << 12; \
} \ } \
} while (0) } while (0)
# define ash2_cycles_done() (sh2->cycles_timeslice - (sh2->sr >> 12)) # define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - ((sh2)->sr >> 12))
#endif #endif
//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc //#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc