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sh2: sync sh2 core with latest mame
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notaz
parent
009ef50c60
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f4c0720c24
7 changed files with 594 additions and 576 deletions
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@ -2991,7 +2991,6 @@ void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
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int sh2_execute(SH2 *sh2c, int cycles)
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{
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int ret_cycles;
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sh2 = sh2c; // XXX
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sh2c->cycles_timeslice = cycles;
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1035
cpu/sh2/mame/sh2.c
1035
cpu/sh2/mame/sh2.c
File diff suppressed because it is too large
Load diff
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@ -8,12 +8,12 @@ typedef unsigned int UINT32;
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typedef unsigned short UINT16;
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typedef unsigned char UINT8;
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#define RB(a) p32x_sh2_read8(a,sh2)
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#define RW(a) p32x_sh2_read16(a,sh2)
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#define RL(a) p32x_sh2_read32(a,sh2)
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#define WB(a,d) p32x_sh2_write8(a,d,sh2)
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#define WW(a,d) p32x_sh2_write16(a,d,sh2)
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#define WL(a,d) p32x_sh2_write32(a,d,sh2)
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#define RB(sh2, a) p32x_sh2_read8(a,sh2)
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#define RW(sh2, a) p32x_sh2_read16(a,sh2)
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#define RL(sh2, a) p32x_sh2_read32(a,sh2)
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#define WB(sh2, a, d) p32x_sh2_write8(a,d,sh2)
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#define WW(sh2, a, d) p32x_sh2_write16(a,d,sh2)
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#define WL(sh2, a, d) p32x_sh2_write32(a,d,sh2)
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// some stuff from sh2comn.h
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#define T 0x00000001
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@ -29,7 +29,10 @@ typedef unsigned char UINT8;
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#define Rn ((opcode>>8)&15)
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#define Rm ((opcode>>4)&15)
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#define sh2_icount sh2->icount
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#define sh2_state SH2
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extern void lprintf(const char *fmt, ...);
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#define logerror lprintf
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#ifdef SH2_STATS
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static SH2 sh2_stats;
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@ -61,7 +64,7 @@ static unsigned int op_refs[0x10000];
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#ifndef DRC_SH2
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int sh2_execute(SH2 *sh2_, int cycles)
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int sh2_execute(SH2 *sh2, int cycles)
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{
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sh2 = sh2_;
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sh2->icount = cycles;
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@ -78,13 +81,13 @@ int sh2_execute(SH2 *sh2_, int cycles)
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if (sh2->delay)
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{
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sh2->ppc = sh2->delay;
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opcode = RW(sh2->delay);
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opcode = RW(sh2, sh2->delay);
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sh2->pc -= 2;
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}
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else
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{
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sh2->ppc = sh2->pc;
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opcode = RW(sh2->pc);
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opcode = RW(sh2, sh2->pc);
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}
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sh2->delay = 0;
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@ -92,22 +95,22 @@ int sh2_execute(SH2 *sh2_, int cycles)
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switch (opcode & ( 15 << 12))
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{
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case 0<<12: op0000(opcode); break;
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case 1<<12: op0001(opcode); break;
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case 2<<12: op0010(opcode); break;
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case 3<<12: op0011(opcode); break;
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case 4<<12: op0100(opcode); break;
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case 5<<12: op0101(opcode); break;
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case 6<<12: op0110(opcode); break;
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case 7<<12: op0111(opcode); break;
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case 8<<12: op1000(opcode); break;
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case 9<<12: op1001(opcode); break;
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case 10<<12: op1010(opcode); break;
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case 11<<12: op1011(opcode); break;
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case 12<<12: op1100(opcode); break;
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case 13<<12: op1101(opcode); break;
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case 14<<12: op1110(opcode); break;
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default: op1111(opcode); break;
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case 0<<12: op0000(sh2, opcode); break;
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case 1<<12: op0001(sh2, opcode); break;
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case 2<<12: op0010(sh2, opcode); break;
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case 3<<12: op0011(sh2, opcode); break;
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case 4<<12: op0100(sh2, opcode); break;
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case 5<<12: op0101(sh2, opcode); break;
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case 6<<12: op0110(sh2, opcode); break;
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case 7<<12: op0111(sh2, opcode); break;
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case 8<<12: op1000(sh2, opcode); break;
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case 9<<12: op1001(sh2, opcode); break;
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case 10<<12: op1010(sh2, opcode); break;
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case 11<<12: op1011(sh2, opcode); break;
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case 12<<12: op1100(sh2, opcode); break;
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case 13<<12: op1101(sh2, opcode); break;
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case 14<<12: op1110(sh2, opcode); break;
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default: op1111(sh2, opcode); break;
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}
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sh2->icount--;
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@ -135,29 +138,28 @@ int sh2_execute(SH2 *sh2_, int cycles)
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#endif
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// drc debug
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void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
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void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode)
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{
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sh2 = sh2_;
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sh2->pc += 2;
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switch (opcode & ( 15 << 12))
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{
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case 0<<12: op0000(opcode); break;
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case 1<<12: op0001(opcode); break;
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case 2<<12: op0010(opcode); break;
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case 3<<12: op0011(opcode); break;
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case 4<<12: op0100(opcode); break;
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case 5<<12: op0101(opcode); break;
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case 6<<12: op0110(opcode); break;
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case 7<<12: op0111(opcode); break;
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case 8<<12: op1000(opcode); break;
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case 9<<12: op1001(opcode); break;
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case 10<<12: op1010(opcode); break;
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case 11<<12: op1011(opcode); break;
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case 12<<12: op1100(opcode); break;
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case 13<<12: op1101(opcode); break;
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case 14<<12: op1110(opcode); break;
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default: op1111(opcode); break;
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case 0<<12: op0000(sh2, opcode); break;
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case 1<<12: op0001(sh2, opcode); break;
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case 2<<12: op0010(sh2, opcode); break;
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case 3<<12: op0011(sh2, opcode); break;
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case 4<<12: op0100(sh2, opcode); break;
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case 5<<12: op0101(sh2, opcode); break;
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case 6<<12: op0110(sh2, opcode); break;
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case 7<<12: op0111(sh2, opcode); break;
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case 8<<12: op1000(sh2, opcode); break;
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case 9<<12: op1001(sh2, opcode); break;
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case 10<<12: op1010(sh2, opcode); break;
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case 11<<12: op1011(sh2, opcode); break;
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case 12<<12: op1100(sh2, opcode); break;
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case 13<<12: op1101(sh2, opcode); break;
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case 14<<12: op1110(sh2, opcode); break;
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default: op1111(sh2, opcode); break;
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}
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}
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@ -14,8 +14,6 @@
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#define I 0xf0
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SH2 *sh2; // active sh2
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int sh2_init(SH2 *sh2, int is_slave)
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{
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int ret = 0;
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@ -66,8 +66,6 @@ typedef struct SH2_
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#define C_SH2_TO_M68K(xsh2, c) \
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((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
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extern SH2 *sh2; // active sh2. XXX: consider removing
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int sh2_init(SH2 *sh2, int is_slave);
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void sh2_finish(SH2 *sh2);
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void sh2_reset(SH2 *sh2);
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@ -454,8 +454,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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case 0x00: // adapter/irq ctl
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return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
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case 0x04: // H count (often as comm too)
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if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
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ash2_end_run(8);
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if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
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ash2_end_run(&sh2s[cpuid], 8);
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return Pico32x.sh2_regs[4 / 2];
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case 0x10: // DREQ len
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return r[a / 2];
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@ -469,8 +469,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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int comreg = 1 << (a & 0x0f) / 2;
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if (Pico32x.comm_dirty_68k & comreg)
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Pico32x.comm_dirty_68k &= ~comreg;
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else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
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ash2_end_run(8);
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else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
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ash2_end_run(&sh2s[cpuid], 8);
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return r[a / 2];
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}
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if ((a & 0x30) == 0x30) {
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@ -695,7 +695,7 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
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dmac0->tcr0 &= 0xffffff;
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// HACK: assume 68k starts writing soon and end the timeslice
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ash2_end_run(16);
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ash2_end_run(&sh2s[id], 16);
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// DREQ is only sent after first 4 words are written.
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// we do multiple of 4 words to avoid messing up alignment
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@ -1016,8 +1016,8 @@ static u32 sh2_read8_cs0(u32 a, int id)
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if ((a & 0x3ff00) == 0x4100) {
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d = p32x_vdp_read16(a);
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if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
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ash2_end_run(8);
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if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
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ash2_end_run(&sh2s[id], 8);
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goto out_16to8;
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}
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@ -1071,8 +1071,8 @@ static u32 sh2_read16_cs0(u32 a, int id)
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if ((a & 0x3ff00) == 0x4100) {
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d = p32x_vdp_read16(a);
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if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
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ash2_end_run(8);
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if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
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ash2_end_run(&sh2s[id], 8);
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goto out;
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}
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@ -237,23 +237,23 @@ extern SH2 sh2s[2];
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#define ssh2 sh2s[1]
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#ifndef DRC_SH2
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# define ash2_end_run(after) do { \
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if (sh2->icount > (after)) { \
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sh2->cycles_timeslice -= sh2->icount; \
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sh2->icount = after; \
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# define ash2_end_run(sh2, after) do { \
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if ((sh2)->icount > (after)) { \
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(sh2)->cycles_timeslice -= (sh2)->icount; \
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(sh2)->icount = after; \
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} \
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} while (0)
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# define ash2_cycles_done() (sh2->cycles_timeslice - sh2->icount)
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# define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - (sh2)->icount)
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#else
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# define ash2_end_run(after) do { \
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int left = sh2->sr >> 12; \
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# define ash2_end_run(sh2, after) do { \
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int left = (sh2)->sr >> 12; \
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if (left > (after)) { \
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sh2->cycles_timeslice -= left; \
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sh2->sr &= 0xfff; \
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sh2->sr |= (after) << 12; \
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(sh2)->cycles_timeslice -= left; \
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(sh2)->sr &= 0xfff; \
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(sh2)->sr |= (after) << 12; \
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} \
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} while (0)
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# define ash2_cycles_done() (sh2->cycles_timeslice - (sh2->sr >> 12))
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# define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - ((sh2)->sr >> 12))
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#endif
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//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc
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