mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
various smallish optimizations, cleanups, and bug fixes
This commit is contained in:
kub
parent
fe344bd3d8
commit
f53e166cf4
8 changed files with 109 additions and 35 deletions
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@ -36,6 +36,47 @@
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#define M5(x,y,z,a,b) (M4(x,y,z,a)|M1(b))
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#define M10(a,b,c,d,e,f,g,h,i,j) (M5(a,b,c,d,e)|M5(f,g,h,i,j))
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// sys_cacheflush always flushes whole pages, and it's rather expensive on ARMs
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// hold a list of pending cache updates and merge requests to reduce cacheflush
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static struct { void *base, *end; } pageflush[4];
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static unsigned pagesize = 4096;
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static void emith_update_cache(void)
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{
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int i;
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for (i = 0; i < 4 && pageflush[i].base; i++) {
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cache_flush_d_inval_i(pageflush[i].base, pageflush[i].end + pagesize-1);
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pageflush[i].base = NULL;
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}
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}
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static inline void emith_update_add(void *base, void *end)
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{
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void *p_base = (void *)((uintptr_t)(base) & ~(pagesize-1));
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void *p_end = (void *)((uintptr_t)(end ) & ~(pagesize-1));
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int i;
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for (i = 0; i < 4 && pageflush[i].base; i++) {
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if (p_base <= pageflush[i].end+pagesize && p_end >= pageflush[i].end) {
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if (p_base < pageflush[i].base) pageflush[i].base = p_base;
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pageflush[i].end = p_end;
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return;
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}
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if (p_base <= pageflush[i].base && p_end >= pageflush[i].base-pagesize) {
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if (p_end > pageflush[i].end) pageflush[i].end = p_end;
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pageflush[i].base = p_base;
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return;
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}
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}
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if (i == 4) {
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/* list full and not mergeable -> flush list */
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emith_update_cache();
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i = 0;
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}
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pageflush[i].base = p_base, pageflush[i].end = p_end;
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}
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// peephole optimizer. ATM only tries to reduce interlock
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#define EMIT_CACHE_SIZE 3
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struct emit_op {
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@ -48,8 +89,8 @@ static struct emit_op emit_cache[EMIT_CACHE_SIZE+3];
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static int emit_index;
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#define emith_insn_ptr() (u8 *)((u32 *)tcache_ptr-emit_index)
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static int emith_pool_index(int tcache_offs);
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static void emith_pool_adjust(int pool_index, int move_offs);
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static inline int emith_pool_index(int tcache_offs);
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static inline void emith_pool_adjust(int pool_index, int move_offs);
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static NOINLINE void EMIT(u32 op, u32 dst, u32 src)
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{
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@ -1106,6 +1147,7 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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(u8 *)ptr; \
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})
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#define emith_jump_cond_inrange(target) !0
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#define emith_jump_patch_size() 4
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#define emith_jump_at(ptr, target) do { \
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@ -1170,7 +1212,7 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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} while (0)
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#define host_instructions_updated(base, end) \
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cache_flush_d_inval_i(base, end)
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emith_update_add(base, end)
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#define host_arg2reg(rd, arg) \
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rd = arg
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@ -1038,6 +1038,9 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
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#define emith_jump_cond_patchable(cond, target) \
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emith_bcond(tcache_ptr, 1, cond, target)
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#define emith_jump_cond_inrange(target) \
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!(((u8 *)target - (u8 *)tcache_ptr + 0x100000) >> 22)
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#define emith_jump_patch(ptr, target) ({ \
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u32 *ptr_ = (u32 *)ptr; \
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u32 disp_ = (u8 *)(target) - (u8 *)(ptr_); \
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@ -1116,6 +1119,7 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
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#define emith_insn_ptr() ((u8 *)tcache_ptr)
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#define emith_flush() /**/
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#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
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#define emith_update_cache() /**/
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#define emith_jump_patch_size() 8
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#define emith_rw_offs_max() 0xff
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@ -209,20 +209,25 @@ enum { RT_BLTZ=000, RT_BGEZ, RT_BLTZAL=020, RT_BGEZAL, RT_SYNCI=037 };
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// FIFO for 2 instructions, for delay slot handling
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u32 emith_last_insns[2] = { -1,-1 };
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int emith_last_idx;
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int emith_last_idx, emith_last_cnt;
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#define EMIT_PUSHOP() \
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do { \
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emith_last_idx ^= 1; \
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if (emith_last_insns[emith_last_idx] != -1) \
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EMIT_PTR(tcache_ptr, emith_last_insns[emith_last_idx]);\
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if (emith_last_insns[emith_last_idx] != -1) { \
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u32 *p = (u32 *)tcache_ptr - emith_last_cnt; \
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EMIT_PTR(p, emith_last_insns[emith_last_idx]);\
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emith_last_cnt --; \
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} \
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emith_last_insns[emith_last_idx] = -1; \
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} while (0)
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#define EMIT(op) \
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do { \
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EMIT_PUSHOP(); \
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tcache_ptr = (void *)((u32 *)tcache_ptr + 1); \
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emith_last_insns[emith_last_idx] = op; \
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emith_last_cnt ++; \
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COUNT_OP; \
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} while (0)
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@ -231,8 +236,7 @@ int emith_last_idx;
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int i; for (i = 0; i < 2; i++) EMIT_PUSHOP(); \
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} while (0)
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#define emith_insn_ptr() (u8 *)((u32 *)tcache_ptr + \
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(emith_last_insns[0] != -1) + (emith_last_insns[1] != -1))
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#define emith_insn_ptr() (u8 *)((u32 *)tcache_ptr - emith_last_cnt)
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// delay slot stuff
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static int emith_is_j(u32 op) // J, JAL
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@ -305,12 +309,14 @@ static void *emith_branch(u32 op)
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}
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if (bop) { // can swap
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tcache_ptr = (void *)((u32 *)tcache_ptr - emith_last_cnt);
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if (emith_last_insns[idx^1] != -1)
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EMIT_PTR(tcache_ptr, emith_last_insns[idx^1]);
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bp = tcache_ptr;
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EMIT_PTR(tcache_ptr, bop); COUNT_OP;
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EMIT_PTR(tcache_ptr, emith_last_insns[idx]);
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emith_last_insns[0] = emith_last_insns[1] = -1;
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emith_last_cnt = 0;
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} else { // can't swap
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emith_flush();
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bp = tcache_ptr;
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@ -325,13 +331,13 @@ static void *emith_branch(u32 op)
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ptr = emith_branch(MIPS_BCONDZ(cond_m, cond_r, 0));
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#define JMP_EMIT(cond, ptr) { \
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u32 val_ = emith_insn_ptr() - (u8 *)(ptr) - 4; \
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u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr) - 4; \
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EMIT_PTR(ptr, MIPS_BCONDZ(cond_m, cond_r, val_ & 0x0003ffff)); \
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emith_flush(); /* NO delay slot handling across jump targets */ \
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}
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#define JMP_EMIT_NC(ptr) { \
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u32 val_ = emith_insn_ptr() - (u8 *)(ptr) - 4; \
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u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr) - 4; \
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EMIT_PTR(ptr, MIPS_B(val_ & 0x0003ffff)); \
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emith_flush(); \
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}
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@ -881,14 +887,14 @@ static u8 *last_lohi;
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static void emith_lohi_nops(void)
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{
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u32 d;
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while ((d = emith_insn_ptr() - last_lohi) < 8 && d >= 0) EMIT(MIPS_NOP);
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while ((d = (u8 *)tcache_ptr - last_lohi) < 8 && d >= 0) EMIT(MIPS_NOP);
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}
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#define emith_mul(d, s1, s2) do { \
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emith_lohi_nops(); \
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EMIT(MIPS_MULTU(s1, s2)); \
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EMIT(MIPS_MFLO(d)); \
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last_lohi = emith_insn_ptr(); \
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last_lohi = (u8 *)tcache_ptr; \
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} while (0)
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#define emith_mul_u64(dlo, dhi, s1, s2) do { \
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@ -896,7 +902,7 @@ static void emith_lohi_nops(void)
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EMIT(MIPS_MULTU(s1, s2)); \
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EMIT(MIPS_MFLO(dlo)); \
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EMIT(MIPS_MFHI(dhi)); \
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last_lohi = emith_insn_ptr(); \
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last_lohi = (u8 *)tcache_ptr; \
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} while (0)
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#define emith_mul_s64(dlo, dhi, s1, s2) do { \
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@ -904,7 +910,7 @@ static void emith_lohi_nops(void)
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EMIT(MIPS_MULT(s1, s2)); \
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EMIT(MIPS_MFLO(dlo)); \
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EMIT(MIPS_MFHI(dhi)); \
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last_lohi = emith_insn_ptr(); \
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last_lohi = (u8 *)tcache_ptr; \
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} while (0)
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#define emith_mula_s64(dlo, dhi, s1, s2) do { \
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@ -915,7 +921,7 @@ static void emith_lohi_nops(void)
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emith_add_r_r(dlo, AT); \
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EMIT(MIPS_SLTU_REG(t_, dlo, AT)); \
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EMIT(MIPS_MFHI(AT)); \
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last_lohi = emith_insn_ptr(); \
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last_lohi = (u8 *)tcache_ptr; \
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emith_add_r_r(dhi, AT); \
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emith_add_r_r(dhi, t_); \
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rcache_free_tmp(t_); \
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@ -1174,14 +1180,14 @@ static int emith_cond_check(int cond, int *r)
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// NB: MIPS conditional branches have only +/- 128KB range
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#define emith_jump_cond(cond, target) do { \
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int r_, mcond_ = emith_cond_check(cond, &r_); \
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u32 disp_ = (u8 *)target - emith_insn_ptr() - 4; \
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u32 disp_ = (u8 *)target - (u8 *)tcache_ptr - 4; \
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if (disp_ >= 0xfffe0000 || disp_ <= 0x0001ffff) { /* can use near B */ \
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emith_branch(MIPS_BCONDZ(mcond_,r_,disp_ & 0x0003ffff)); \
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} else { /* far branch if near branch isn't possible */ \
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mcond_ = emith_invert_branch(mcond_); \
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u8 *bp = emith_branch(MIPS_BCONDZ(mcond_, r_, 0)); \
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emith_branch(MIPS_J((uintptr_t)target & 0x0fffffff)); \
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EMIT_PTR(bp, MIPS_BCONDZ(mcond_, r_, emith_insn_ptr()-bp-4)); \
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EMIT_PTR(bp, MIPS_BCONDZ(mcond_, r_, (u8 *)tcache_ptr-bp-4)); \
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} \
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} while (0)
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@ -1190,9 +1196,12 @@ static int emith_cond_check(int cond, int *r)
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mcond_ = emith_invert_branch(mcond_); \
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u8 *bp = emith_branch(MIPS_BCONDZ(mcond_, r_, 0));\
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emith_branch(MIPS_J((uintptr_t)target & 0x0fffffff)); \
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EMIT_PTR(bp, MIPS_BCONDZ(mcond_, r_, emith_insn_ptr()-bp-4)); \
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EMIT_PTR(bp, MIPS_BCONDZ(mcond_, r_, (u8 *)tcache_ptr-bp-4)); \
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} while (0)
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#define emith_jump_cond_inrange(target) \
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!(((u8 *)target - (u8 *)tcache_ptr + 0x10000) >> 18)
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// NB: returns position of patch for cache maintenance
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#define emith_jump_patch(ptr, target) ({ \
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u32 *ptr_ = (u32 *)ptr-1; /* must skip condition check code */ \
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@ -1261,6 +1270,7 @@ static int emith_cond_check(int cond, int *r)
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#define emith_pool_commit(j) /**/
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// NB: mips32r2 has SYNCI
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#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
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#define emith_update_cache() /**/
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#define emith_jump_patch_size() 4
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#define emith_rw_offs_max() 0x7fff
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@ -877,6 +877,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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ptr; \
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})
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#define emith_jump_cond_inrange(ptr) !0
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#define emith_jump_patch_size() 6
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#define emith_jump_at(ptr, target) do { \
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@ -986,6 +987,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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} while (0)
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#define host_instructions_updated(base, end)
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#define emith_update_cache() /**/
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#define emith_rw_offs_max() 0xffffffff
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@ -993,7 +995,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#define HOST_REGS 16
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#define PTR_SCALE 3
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#define NA_TMP_REG xAX // non-arg tmp from reg_temp[]
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#define EMIT_XREX_IF(w, r, rm, rs) do { \
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int xr_ = (r) > 7 ? 1 : 0; \
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@ -1078,7 +1079,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#define HOST_REGS 8
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#define PTR_SCALE 2
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#define NA_TMP_REG xBX // non-arg tmp from reg_temp[]
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#define EMIT_REX_IF(w, r, rm) do { \
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assert((u32)(r) < 8u); \
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@ -2920,6 +2920,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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// mark memory for overwrite detection
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dr_mark_memory(1, block, tcache_id, 0);
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block->active = 1;
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emith_update_cache();
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return block->entryp[0].tcache_ptr;
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}
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@ -3113,8 +3114,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp = rcache_get_tmp_arg(0);
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sr = rcache_get_reg(SHR_SR, RC_GR_READ, NULL);
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emith_cmp_r_imm(sr, 0);
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emith_move_r_imm_c(DCOND_LE, tmp, pc);
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emith_jump_cond(DCOND_LE, sh2_drc_exit);
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if (emith_jump_cond_inrange(sh2_drc_exit)) {
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emith_move_r_imm_c(DCOND_LE, tmp, pc);
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emith_jump_cond(DCOND_LE, sh2_drc_exit);
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} else {
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EMITH_JMP_START(DCOND_GT);
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emith_move_r_imm(tmp, pc);
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emith_jump(sh2_drc_exit);
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EMITH_JMP_END(DCOND_GT);
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}
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rcache_free_tmp(tmp);
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#if (DRC_DEBUG & 32)
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@ -3249,7 +3257,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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}
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}
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rcache_set_usage_now(opd[0].source); // current insn
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rcache_set_usage_soon(late); // insns 1-3
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rcache_set_usage_soon(soon); // insns 1-3
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rcache_set_usage_late(late & ~soon); // insns 4-9
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rcache_set_usage_discard(write & ~(late|soon) & ~opd[0].source);
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@ -4442,12 +4450,16 @@ end_op:
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fflush(stdout);
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#endif
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emith_update_cache();
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return block_entry_ptr;
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}
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static void sh2_generate_utils(void)
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{
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int arg0, arg1, arg2, arg3, sr, tmp, tmp2;
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#if DRC_DEBUG
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int hic = host_insn_count; // don't count utils for insn statistics
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#endif
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host_arg2reg(arg0, 0);
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host_arg2reg(arg1, 1);
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@ -4794,6 +4806,10 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_read16_poll);
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host_dasm_new_symbol(sh2_drc_read32_poll);
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#endif
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#if DRC_DEBUG
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host_insn_count = hic;
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#endif
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}
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static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 nolit, int free)
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@ -4847,6 +4863,7 @@ static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 nol
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bd->addr = bd->size = bd->addr_lit = bd->size_lit = 0;
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bd->entry_count = 0;
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}
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emith_update_cache();
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}
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static void sh2_smc_rm_blocks(u32 a, int tcache_id, u32 shift)
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@ -5197,6 +5214,7 @@ int sh2_drc_init(SH2 *sh2)
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tcache_ptr = tcache;
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sh2_generate_utils();
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host_instructions_updated(tcache, tcache_ptr);
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emith_update_cache();
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||||
tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
|
||||
tcache_limit[0] = tcache_bases[0] + tcache_sizes[0] - (tcache_ptr-tcache);
|
||||
|
|
|
|||
|
|
@ -33,26 +33,24 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
|
|||
|
||||
#if defined(DRC_SH2)
|
||||
// direct access to some host CPU registers used by the DRC
|
||||
// XXX MUST match definitions in cpu/sh2/compiler.c
|
||||
// XXX MUST match definitions for SHR_SR in cpu/sh2/compiler.c
|
||||
#if defined(__arm__)
|
||||
#define DRC_SR_REG r10
|
||||
#define DRC_SR_REG "r10"
|
||||
#elif defined(__aarch64__)
|
||||
#define DRC_SR_REG r22
|
||||
#define DRC_SR_REG "r22"
|
||||
#elif defined(__mips__)
|
||||
#define DRC_SR_REG s6
|
||||
#define DRC_SR_REG "s6"
|
||||
#elif defined(__i386__)
|
||||
#define DRC_SR_REG edi
|
||||
#define DRC_SR_REG "edi"
|
||||
#elif defined(__x86_64__)
|
||||
#define DRC_SR_REG ebx
|
||||
#define DRC_SR_REG "ebx"
|
||||
#else
|
||||
#warning "direct DRC register access not available for this host"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef DRC_SR_REG
|
||||
#define __DRC_DECLARE_SR(SR) register int sh2_sr asm(#SR)
|
||||
#define _DRC_DECLARE_SR(SR) __DRC_DECLARE_SR(SR)
|
||||
#define DRC_DECLARE_SR _DRC_DECLARE_SR(DRC_SR_REG)
|
||||
#define DRC_DECLARE_SR register int sh2_sr asm(DRC_SR_REG)
|
||||
#define DRC_SAVE_SR(sh2) \
|
||||
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
|
||||
sh2->sr = sh2_sr;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue