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sh2 drc, fix powerpc cache handling

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This commit is contained in:
kub 2021-04-21 21:16:42 +02:00
parent 448b634ccc
commit f7615fc283
3 changed files with 5 additions and 4 deletions
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5
cpu/drc/emit_ppc.c
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@ -1559,10 +1559,11 @@ static int emith_cond_check(int cond)
static NOINLINE void host_instructions_updated(void *base, void *end, int force)
{
int step = 32, lgstep = 5;
char *_base = base, *_end = end;
int count = (_end - _base + step-1) >> lgstep;
char *_base = (char *)((uptr)base & ~(step-1));
int count = (((char *)end - _base) >> lgstep) + 1;
if (count <= 0) count = 1; // make sure count is positive
base = _base;
asm volatile(
" mtctr %1;"

2
cpu/sh2/compiler.h
View file

@ -47,7 +47,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc,
#elif defined(__riscv__) || defined(__riscv)
#define DRC_SR_REG "s11"
#define DRC_REG_LL 0 // no ABI for (__ILP32__ && __riscv_xlen != 32)
#elif defined(__powerpc__)
#elif defined(__powerpc__) || defined(__ppc__)
#define DRC_SR_REG "r28"
#define DRC_REG_LL 0 // no ABI for __ILP32__
#elif defined(__i386__)

2
platform/linux/emu.c
View file

@ -32,7 +32,7 @@ void pemu_prep_defconfig(void)
void pemu_validate_config(void)
{
#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv__) && !defined(__riscv) && !defined(__powerpc__) && !defined(__i386__) && !defined(__x86_64__)
#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv__) && !defined(__riscv) && !defined(__powerpc__) && !defined(__ppc__) && !defined(__i386__) && !defined(__x86_64__)
PicoIn.opt &= ~POPT_EN_DRC;
#endif
}