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32x: memhandler improvements

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- use consistent read tables (with write)
- use sh2 ptr instead of id
- place data_array/peri_regs in sh2 struct
This commit is contained in:
notaz 2013-08-07 03:26:02 +03:00
parent c1931173ab
commit f81107f590
11 changed files with 224 additions and 223 deletions
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2
cpu/drc/emit_arm.c
View file

@ -739,7 +739,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_sh2_wcall(a, tab) { \
emith_lsr(12, a, SH2_WRITE_SHIFT); \
EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
emith_ctx_read(2, offsetof(SH2, is_slave)); \
emith_move_r_r(2, CONTEXT_REG); \
emith_jump_reg(12); \
}

2
cpu/drc/emit_x86.c
View file

@ -635,7 +635,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
emith_move_r_r(arg2_, CONTEXT_REG); \
emith_jump_reg(xBX); \
}

7
cpu/sh2/compiler.c
View file

@ -349,7 +349,7 @@ static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
// address space stuff
static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
@ -363,6 +363,7 @@ static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
}
else if ((a & 0xfffff000) == 0xc0000000) {
// data array
// FIXME: access sh2->data_array instead
poffs = offsetof(SH2, p_da);
*mask = 0xfff;
}
@ -3159,7 +3160,7 @@ void sh2_drc_mem_setup(SH2 *sh2)
{
// fill the convenience pointers
sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
sh2->p_da = sh2->data_array;
sh2->p_sdram = Pico32xMem->sdram;
sh2->p_rom = Pico.rom;
}
@ -3277,7 +3278,7 @@ static void *dr_get_pc_base(u32 pc, int is_slave)
}
else if ((pc & 0xfffff000) == 0xc0000000) {
// data array
ret = Pico32xMem->data_array[is_slave];
ret = sh2s[is_slave].data_array;
mask = 0xfff;
}
else if ((pc & 0xc6000000) == 0x06000000) {

11
cpu/sh2/sh2.c
View file

@ -14,12 +14,13 @@
#define I 0xf0
int sh2_init(SH2 *sh2, int is_slave)
int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2)
{
int ret = 0;
memset(sh2, 0, offsetof(SH2, mult_m68k_to_sh2));
sh2->is_slave = is_slave;
sh2->other_sh2 = other_sh2;
pdb_register_cpu(sh2, PDBCT_SH2, is_slave ? "ssh2" : "msh2");
#ifdef DRC_SH2
ret = sh2_drc_init(sh2);
@ -145,16 +146,13 @@ enum ctl_byte {
CTL_CYCLES = 0x85,
};
#define SH2MAP_ADDR2OFFS_R(a) \
((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
static unsigned int local_read32(SH2 *sh2, u32 a)
{
const sh2_memmap *sh2_map = sh2->read16_map;
u16 *pd;
uptr p;
sh2_map += SH2MAP_ADDR2OFFS_R(a);
sh2_map += (a >> 25);
p = sh2_map->addr;
if (!map_flag_set(p)) {
pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
@ -163,8 +161,7 @@ static unsigned int local_read32(SH2 *sh2, u32 a)
if ((a & 0xfffff000) == 0xc0000000) {
// data array
pd = (u16 *)Pico32xMem->data_array[sh2->is_slave]
+ (a & 0xfff) / 2;
pd = (u16 *)sh2->data_array + (a & 0xfff) / 2;
return (pd[0] << 16) | pd[1];
}
if ((a & 0xdfffffc0) == 0x4000) {

13
cpu/sh2/sh2.h
View file

@ -63,10 +63,15 @@ typedef struct SH2_
unsigned int cycles_timeslice;
struct SH2_ *other_sh2;
// we use 68k reference cycles for easier sync
unsigned int m68krcycles_done;
unsigned int mult_m68k_to_sh2;
unsigned int mult_sh2_to_m68k;
unsigned char data_array[0x1000]; // cache (can be used as RAM)
unsigned int peri_regs[0x200/4]; // periphereal regs
} SH2;
#define CYCLE_MULT_SHIFT 10
@ -75,7 +80,7 @@ typedef struct SH2_
#define C_SH2_TO_M68K(xsh2, c) \
((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
int sh2_init(SH2 *sh2, int is_slave);
int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
void sh2_finish(SH2 *sh2);
void sh2_reset(SH2 *sh2);
int sh2_irl_irq(SH2 *sh2, int level, int nested_call);
@ -94,9 +99,9 @@ int sh2_execute(SH2 *sh2, int cycles);
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
// debug
#ifdef DRC_CMP