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https://github.com/RaySollium99/picodrive.git
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handle 32x+cd
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notaz
parent
87650acd75
commit
fa8fb75445
11 changed files with 191 additions and 103 deletions
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@ -786,8 +786,12 @@ static u32 PicoRead8_32x_on(u32 a)
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goto out_16to8;
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}
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if ((a & 0xfc00) != 0x5000)
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return PicoRead8_io(a);
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if ((a & 0xfc00) != 0x5000) {
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if (PicoAHW & PAHW_MCD)
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return PicoRead8_mcd_io(a);
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else
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return PicoRead8_io(a);
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}
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if ((a & 0xfff0) == 0x5180) { // a15180
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d = p32x_vdp_read16(a);
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@ -826,8 +830,12 @@ static u32 PicoRead16_32x_on(u32 a)
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goto out;
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}
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if ((a & 0xfc00) != 0x5000)
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return PicoRead16_io(a);
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if ((a & 0xfc00) != 0x5000) {
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if (PicoAHW & PAHW_MCD)
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return PicoRead16_mcd_io(a);
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else
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return PicoRead16_io(a);
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}
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if ((a & 0xfff0) == 0x5180) { // a15180
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d = p32x_vdp_read16(a);
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@ -863,7 +871,10 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
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}
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if ((a & 0xfc00) != 0x5000) {
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PicoWrite8_io(a, d);
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if (PicoAHW & PAHW_MCD)
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PicoWrite8_mcd_io(a, d);
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else
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PicoWrite8_io(a, d);
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if (a == 0xa130f1)
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bank_switch(Pico32x.regs[4 / 2]);
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return;
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@ -898,7 +909,10 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
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}
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if ((a & 0xfc00) != 0x5000) {
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PicoWrite16_io(a, d);
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if (PicoAHW & PAHW_MCD)
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PicoWrite16_mcd_io(a, d);
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else
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PicoWrite16_io(a, d);
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if (a == 0xa130f0)
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bank_switch(Pico32x.regs[4 / 2]);
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return;
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@ -1141,6 +1155,9 @@ static void bank_switch(int b)
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{
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unsigned int rs, bank;
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if (Pico.m.ncart_in)
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return;
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bank = b << 20;
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if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
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bank_map_handler();
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@ -1536,42 +1553,94 @@ static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
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static const u16 msh2_code[] = {
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// trap instructions
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0xaffe, // bra <self>
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0x0009, // nop
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0xaffe, // 200 bra <self>
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0x0009, // 202 nop
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// have to wait a bit until m68k initial program finishes clearing stuff
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// to avoid races with game SH2 code, like in Tempo
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0xd004, // mov.l @(_m_ok,pc), r0
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0xd105, // mov.l @(_cnt,pc), r1
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0xd205, // mov.l @(_start,pc), r2
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0x71ff, // add #-1, r1
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0x4115, // cmp/pl r1
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0x89fc, // bt -2
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0xc208, // mov.l r0, @(h'20,gbr)
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0x6822, // mov.l @r2, r8
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0x482b, // jmp @r8
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0x0009, // nop
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('M'<<8)|'_', ('O'<<8)|'K',
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0x0001, 0x0000,
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0x2200, 0x03e0 // master start pointer in ROM
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0xd406, // 204 mov.l @(_m_ok,pc), r4
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0xc400, // 206 mov.b @(h'0,gbr),r0
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0xc801, // 208 tst #1, r0
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0x8b0f, // 20a bf cd_start
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0xd105, // 20c mov.l @(_cnt,pc), r1
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0xd206, // 20e mov.l @(_start,pc), r2
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0x71ff, // 210 add #-1, r1
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0x4115, // 212 cmp/pl r1
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0x89fc, // 214 bt -2
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0x6043, // 216 mov r4, r0
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0xc208, // 218 mov.l r0, @(h'20,gbr)
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0x6822, // 21a mov.l @r2, r8
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0x482b, // 21c jmp @r8
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0x0009, // 21e nop
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('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
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0x0001, 0x0000, // 224 _cnt
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0x2200, 0x03e0, // master start pointer in ROM
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// cd_start:
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0xd20d, // 22c mov.l @(__cd_,pc), r2
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0xc608, // 22e mov.l @(h'20,gbr), r0
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0x3200, // 230 cmp/eq r0, r2
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0x8bfc, // 232 bf #-2
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0xe000, // 234 mov #0, r0
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0xcf80, // 236 or.b #0x80,@(r0,gbr)
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0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
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0xd30c, // 23a mov.l @(_max_len,pc), r3
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0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
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0x5a82, // 23e mov.l @(8,r8), r10 // entry
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0x5081, // 240 mov.l @(4,r8), r0 // len
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0x5980, // 242 mov.l @(0,r8), r9 // dst
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0x3036, // 244 cmp/hi r3,r0
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0x8b00, // 246 bf #1
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0x6033, // 248 mov r3,r0
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0x7820, // 24a add #0x20, r8
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// ipl_copy:
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0x6286, // 24c mov.l @r8+, r2
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0x2922, // 24e mov.l r2, @r9
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0x7904, // 250 add #4, r9
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0x70fc, // 252 add #-4, r0
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0x8800, // 254 cmp/eq #0, r0
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0x8bf9, // 256 bf #-5
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//
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0x4b2e, // 258 ldc r11, vbr
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0x6043, // 25a mov r4, r0 // M_OK
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0xc208, // 25c mov.l r0, @(h'20,gbr)
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0x4a2b, // 25e jmp @r10
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0x0009, // 260 nop
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0x0009, // 262 nop // pad
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('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
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0x2400, 0x0018, // 268 _start_cd
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0x0001, 0xffe0, // 26c _max_len
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};
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static const u16 ssh2_code[] = {
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0xaffe, // bra <self>
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0x0009, // nop
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0xaffe, // 200 bra <self>
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0x0009, // 202 nop
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// code to wait for master, in case authentic master BIOS is used
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0xd104, // mov.l @(_m_ok,pc), r1
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0xd206, // mov.l @(_start,pc), r2
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0xc608, // mov.l @(h'20,gbr), r0
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0x3100, // cmp/eq r0, r1
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0x8bfc, // bf #-2
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0xd003, // mov.l @(_s_ok,pc), r0
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0xc209, // mov.l r0, @(h'24,gbr)
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0x6822, // mov.l @r2, r8
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0x482b, // jmp @r8
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0x0009, // nop
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('M'<<8)|'_', ('O'<<8)|'K',
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('S'<<8)|'_', ('O'<<8)|'K',
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0x2200, 0x03e4 // slave start pointer in ROM
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0xd106, // 204 mov.l @(_m_ok,pc), r1
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0xd208, // 206 mov.l @(_start,pc), r2
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0xc608, // 208 mov.l @(h'20,gbr), r0
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0x3100, // 20a cmp/eq r0, r1
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0x8bfc, // 20c bf #-2
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0xc400, // 20e mov.b @(h'0,gbr),r0
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0xc801, // 210 tst #1, r0
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0xd004, // 212 mov.l @(_s_ok,pc), r0
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0x8b0a, // 214 bf cd_start
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0xc209, // 216 mov.l r0, @(h'24,gbr)
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0x6822, // 218 mov.l @r2, r8
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0x482b, // 21a jmp @r8
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0x0009, // 21c nop
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0x0009, // 21e nop
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('M'<<8)|'_', ('O'<<8)|'K', // 220
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('S'<<8)|'_', ('O'<<8)|'K', // 224
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0x2200, 0x03e4, // slave start pointer in ROM
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// cd_start:
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0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
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0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
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0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
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0x4b2e, // 232 ldc r11, vbr
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0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
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0x4a2b, // 236 jmp @r10
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0x0009, // 238 nop
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0x0009, // 23a nop
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0x2400, 0x0018, // 23c _start_cd
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};
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#define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
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@ -1622,13 +1691,13 @@ static void get_bios(void)
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for (i = 0; i < 128; i++)
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pl[i] = HWSWAP(0x200);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x6040000);
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// start
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pl[0] = pl[2] = HWSWAP(0x204);
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x6040000);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
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}
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// SSH2
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@ -1643,13 +1712,13 @@ static void get_bios(void)
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for (i = 0; i < 128; i++)
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pl[i] = HWSWAP(0x200);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x603f800);
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// start
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pl[0] = pl[2] = HWSWAP(0x204);
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x603f800);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
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}
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}
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@ -1697,32 +1766,34 @@ void PicoMemSetup32x(void)
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// so that we can avoid handling the RV bit.
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// m68k_map_unmap(0x000000, 0x3fffff);
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// MD ROM area
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rs = sizeof(Pico32xMem->m68k_rom_bank);
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cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
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cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
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cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
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cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
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if (!Pico.m.ncart_in) {
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// MD ROM area
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rs = sizeof(Pico32xMem->m68k_rom_bank);
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cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
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cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
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cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
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cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
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// 32X ROM (unbanked, XXX: consider mirroring?)
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rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
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if (rs > 0x80000)
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rs = 0x80000;
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cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
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cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
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// 32X ROM (unbanked, XXX: consider mirroring?)
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rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
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if (rs > 0x80000)
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rs = 0x80000;
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cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
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cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
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#ifdef EMU_F68K
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// setup FAME fetchmap
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PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
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for (rs = 0x88; rs < 0x90; rs++)
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PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
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// setup FAME fetchmap
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PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
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for (rs = 0x88; rs < 0x90; rs++)
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PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
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#endif
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// 32X ROM (banked)
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bank_switch(0);
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cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
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cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
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// 32X ROM (banked)
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bank_switch(0);
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cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
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cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
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}
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// SYS regs
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cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
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