mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-06 07:38:05 -04:00
cleanup and microoptimizations in SH2 hw handling
This commit is contained in:
kub
parent
f740428b81
commit
fe344bd3d8
12 changed files with 308 additions and 247 deletions
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@ -220,7 +220,7 @@ static NOINLINE void sh2_poll_write(u32 a, u32 d, unsigned int cycles, SH2 *sh2)
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{
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int hix = (a >> 1) % PFIFO_CNT;
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struct sh2_poll_fifo *fifo = sh2_poll_fifo[hix];
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struct sh2_poll_fifo *q = &fifo[(sh2_poll_wr[hix]-1) % PFIFO_SZ];
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struct sh2_poll_fifo *q;
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int cpu = sh2 ? sh2->is_slave : -1;
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unsigned rd = sh2_poll_rd[hix], wr = sh2_poll_wr[hix];
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unsigned idx, nrd;
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@ -230,8 +230,9 @@ static NOINLINE void sh2_poll_write(u32 a, u32 d, unsigned int cycles, SH2 *sh2)
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// throw out any values written by other cpus, plus heading cancelled stuff
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for (idx = nrd = wr; idx != rd; ) {
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idx = (idx-1) % PFIFO_SZ;
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if (fifo[idx].a == a && fifo[idx].cpu != cpu) { fifo[idx].a = -1; }
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if (fifo[idx].a != -1) { nrd = idx; }
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q = &fifo[idx];
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if (q->cpu != cpu && q->a == a) { q->a = -1; }
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if (q->a != -1) { nrd = idx; }
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}
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rd = nrd;
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@ -239,7 +240,8 @@ static NOINLINE void sh2_poll_write(u32 a, u32 d, unsigned int cycles, SH2 *sh2)
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// intermediate values that may cause synchronisation problems.
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// NB this can take an eternity on m68k: mov.b <addr1.l>,<addr2.l> needs
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// 28 m68k-cycles (~80 sh2-cycles) to complete (observed in Metal Head)
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if (q->a == a && rd != wr && !CYCLES_GT(cycles,q->cycles+30)) {
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q = &fifo[(sh2_poll_wr[hix]-1) % PFIFO_SZ];
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if (rd != wr && q->a == a && !CYCLES_GT(cycles,q->cycles+30)) {
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q->d = d;
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} else {
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// store write to poll address in fifo
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@ -493,6 +495,35 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 0x1d:
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case 0x1e:
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case 0x1f:
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return;
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case 0x20: // comm port
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case 0x21:
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case 0x22:
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case 0x23:
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case 0x24:
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case 0x25:
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case 0x26:
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case 0x27:
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case 0x28:
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case 0x29:
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case 0x2a:
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case 0x2b:
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case 0x2c:
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case 0x2d:
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case 0x2e:
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case 0x2f:
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if (REG8IN16(r, a) != d) {
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int cycles = SekCyclesDone();
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if (cycles - (int)msh2.m68krcycles_done > 30)
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p32x_sync_sh2s(cycles);
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REG8IN16(r, a) = d;
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a & ~1, r[a / 2], cycles, NULL);
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}
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return;
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case 0x30:
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return;
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case 0x31: // PWM control
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@ -532,22 +563,6 @@ static void p32x_reg_write8(u32 a, u32 d)
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p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
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return;
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}
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if ((a & 0x30) == 0x20) {
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int cycles = SekCyclesDone();
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if (REG8IN16(r, a) == d)
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return;
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if (cycles - (int)msh2.m68krcycles_done > 30)
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p32x_sync_sh2s(cycles);
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REG8IN16(r, a) = d;
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a & ~1, r[a / 2], cycles, NULL);
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return;
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}
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}
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static void p32x_reg_write16(u32 a, u32 d)
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@ -558,61 +573,68 @@ static void p32x_reg_write16(u32 a, u32 d)
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// for things like bset on comm port
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m68k_poll.cnt = 0;
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switch (a) {
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case 0x00: // adapter ctl
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switch (a/2) {
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case 0x00/2: // adapter ctl
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if ((d ^ r[0]) & d & P32XS_nRES)
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p32x_reset_sh2s();
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r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
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r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
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return;
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case 0x08: // DREQ src
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case 0x08/2: // DREQ src
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r[a / 2] = d & 0xff;
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return;
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case 0x0a:
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case 0x0a/2:
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r[a / 2] = d & ~1;
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return;
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case 0x0c: // DREQ dest
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case 0x0c/2: // DREQ dest
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r[a / 2] = d & 0xff;
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return;
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case 0x0e:
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case 0x0e/2:
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r[a / 2] = d;
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return;
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case 0x10: // DREQ len
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case 0x10/2: // DREQ len
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r[a / 2] = d & ~3;
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return;
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case 0x12: // FIFO reg
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case 0x12/2: // FIFO reg
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dreq0_write(r, d);
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return;
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case 0x1a: // TV + mystery bit
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case 0x1a/2: // TV + mystery bit
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r[a / 2] = d & 0x0101;
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return;
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case 0x30: // PWM control
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case 0x20/2: // comm port
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case 0x22/2:
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case 0x24/2:
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case 0x26/2:
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case 0x28/2:
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case 0x2a/2:
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case 0x2c/2:
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case 0x2e/2:
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if (r[a / 2] != d) {
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int cycles = SekCyclesDone();
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if (cycles - (int)msh2.m68krcycles_done > 30)
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p32x_sync_sh2s(cycles);
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r[a / 2] = d;
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a, (u16)d, cycles, NULL);
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}
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return;
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case 0x30/2: // PWM control
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d = (r[a / 2] & ~0x0f) | (d & 0x0f);
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r[a / 2] = d;
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p32x_pwm_write16(a, d, NULL, SekCyclesDone());
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return;
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}
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// comm port
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if ((a & 0x30) == 0x20) {
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int cycles = SekCyclesDone();
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if (r[a / 2] == d)
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return;
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if (cycles - (int)msh2.m68krcycles_done > 30)
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p32x_sync_sh2s(cycles);
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r[a / 2] = d;
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a, (u16)d, cycles, NULL);
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return;
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}
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// PWM
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else if ((a & 0x30) == 0x30) {
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p32x_pwm_write16(a, d, NULL, SekCyclesDone());
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return;
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case 0x32/2:
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case 0x34/2:
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case 0x36/2:
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case 0x38/2:
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case 0x3a/2:
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case 0x3c/2:
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case 0x3e/2:
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p32x_pwm_write16(a, d, NULL, SekCyclesDone());
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return;
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}
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p32x_reg_write8(a + 1, d);
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@ -709,23 +731,23 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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u16 *r = Pico32x.regs;
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a &= 0x3e;
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switch (a) {
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case 0x00: // adapter/irq ctl
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switch (a/2) {
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case 0x00/2: // adapter/irq ctl
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return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
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| Pico32x.sh2irq_mask[sh2->is_slave];
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case 0x04: // H count (often as comm too)
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case 0x04/2: // H count (often as comm too)
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 9);
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sh2s_sync_on_read(sh2);
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return sh2_poll_read(a, Pico32x.sh2_regs[4 / 2], sh2_cycles_done_m68k(sh2), sh2);
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case 0x06:
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case 0x06/2:
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return (r[a / 2] & ~P32XS_FULL) | 0x4000;
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case 0x08: // DREQ src
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case 0x0a:
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case 0x0c: // DREQ dst
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case 0x0e:
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case 0x10: // DREQ len
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case 0x08/2: // DREQ src
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case 0x0a/2:
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case 0x0c/2: // DREQ dst
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case 0x0e/2:
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case 0x10/2: // DREQ len
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return r[a / 2];
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case 0x12: // DREQ FIFO - does this work on hw?
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case 0x12/2: // DREQ FIFO - does this work on hw?
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if (Pico32x.dmac0_fifo_ptr > 0) {
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Pico32x.dmac0_fifo_ptr--;
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r[a / 2] = Pico32x.dmac_fifo[0];
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@ -733,23 +755,34 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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Pico32x.dmac0_fifo_ptr * 2);
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}
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return r[a / 2];
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case 0x14:
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case 0x16:
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case 0x18:
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case 0x1a:
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case 0x1c:
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case 0x14/2:
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case 0x16/2:
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case 0x18/2:
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case 0x1a/2:
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case 0x1c/2:
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return 0; // ?
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case 0x20/2: // comm port
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case 0x22/2:
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case 0x24/2:
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case 0x26/2:
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case 0x28/2:
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case 0x2a/2:
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case 0x2c/2:
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case 0x2e/2:
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 9);
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sh2s_sync_on_read(sh2);
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return sh2_poll_read(a, r[a / 2], sh2_cycles_done_m68k(sh2), sh2);
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case 0x30/2: // PWM
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case 0x32/2:
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case 0x34/2:
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case 0x36/2:
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case 0x38/2:
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case 0x3a/2:
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case 0x3c/2:
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case 0x3e/2:
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return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
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}
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// comm port
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if ((a & 0x30) == 0x20) {
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 9);
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sh2s_sync_on_read(sh2);
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return sh2_poll_read(a, r[a / 2], sh2_cycles_done_m68k(sh2), sh2);
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}
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if ((a & 0x30) == 0x30)
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return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
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elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
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"unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
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return 0;
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@ -796,6 +829,32 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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sh2_poll_write(a & ~1, d, cycles, sh2);
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}
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return;
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case 0x20: // comm port
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case 0x21:
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case 0x22:
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case 0x23:
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case 0x24:
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case 0x25:
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case 0x26:
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case 0x27:
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case 0x28:
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case 0x29:
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case 0x2a:
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case 0x2b:
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case 0x2c:
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case 0x2d:
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case 0x2e:
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case 0x2f:
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if (REG8IN16(r, a) != d) {
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unsigned int cycles = sh2_cycles_done_m68k(sh2);
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REG8IN16(r, a) = d;
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a & ~1, r[a / 2], cycles, sh2);
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}
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return;
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case 0x30:
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REG8IN16(r, a) = d & 0x0f;
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d = r[0x30 / 2];
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@ -837,20 +896,6 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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return;
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}
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if ((a & 0x30) == 0x20) {
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unsigned int cycles;
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if (REG8IN16(r, a) == d)
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return;
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REG8IN16(r, a) = d;
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cycles = sh2_cycles_done_m68k(sh2);
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a & ~1, r[a / 2], cycles, sh2);
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return;
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}
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elprintf(EL_32X|EL_ANOMALY,
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"unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
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}
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@ -861,49 +906,57 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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sh2->poll_cnt = 0;
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// comm
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if ((a & 0x30) == 0x20) {
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unsigned int cycles;
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if (Pico32x.regs[a / 2] == d)
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return;
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Pico32x.regs[a / 2] = d;
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cycles = sh2_cycles_done_m68k(sh2);
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a, d, cycles, sh2);
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return;
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}
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// PWM
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else if ((a & 0x30) == 0x30) {
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p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
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return;
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}
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switch (a) {
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case 0: // FM
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switch (a/2) {
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case 0x00/2: // FM
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Pico32x.regs[0] &= ~P32XS_FM;
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Pico32x.regs[0] |= d & P32XS_FM;
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break;
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case 0x14:
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case 0x14/2:
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Pico32x.sh2irqs &= ~P32XI_VRES;
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goto irls;
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case 0x16:
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case 0x16/2:
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
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goto irls;
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case 0x18:
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case 0x18/2:
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
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goto irls;
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case 0x1a:
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case 0x1a/2:
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Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
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p32x_update_cmd_irq(sh2, 0);
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return;
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case 0x1c:
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case 0x1c/2:
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p32x_pwm_sync_to_sh2(sh2);
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
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p32x_pwm_schedule_sh2(sh2);
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goto irls;
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case 0x20/2: // comm port
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case 0x22/2:
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case 0x24/2:
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case 0x26/2:
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case 0x28/2:
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case 0x2a/2:
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case 0x2c/2:
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case 0x2e/2:
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if (Pico32x.regs[a / 2] != d) {
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unsigned int cycles = sh2_cycles_done_m68k(sh2);
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Pico32x.regs[a / 2] = d;
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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sh2_poll_write(a, d, cycles, sh2);
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}
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return;
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case 0x30/2: // PWM
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case 0x32/2:
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case 0x34/2:
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case 0x36/2:
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case 0x38/2:
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case 0x3a/2:
|
||||
case 0x3c/2:
|
||||
case 0x3e/2:
|
||||
p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
|
||||
return;
|
||||
}
|
||||
|
||||
p32x_sh2reg_write8(a | 1, d, sh2);
|
||||
|
|
@ -1391,7 +1444,7 @@ static u32 REGPARM(2) sh2_read8_cs0(u32 a, SH2 *sh2)
|
|||
|
||||
sh2_burn_cycles(sh2, 1*2);
|
||||
|
||||
// 0x3ffc0 is veridied
|
||||
// 0x3ffc0 is verified
|
||||
if ((a & 0x3ffc0) == 0x4000) {
|
||||
d = p32x_sh2reg_read16(a, sh2);
|
||||
goto out_16to8;
|
||||
|
|
@ -1573,6 +1626,11 @@ static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
|
|||
elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
|
||||
a, d & 0xff, sh2_pc(sh2));
|
||||
|
||||
if ((a & 0x3ffc0) == 0x4000) {
|
||||
p32x_sh2reg_write8(a, d, sh2);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (Pico32x.regs[0] & P32XS_FM) {
|
||||
if ((a & 0x3fff0) == 0x4100) {
|
||||
sh2->poll_cnt = 0;
|
||||
|
|
@ -1588,11 +1646,6 @@ static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
|
|||
}
|
||||
}
|
||||
|
||||
if ((a & 0x3ffc0) == 0x4000) {
|
||||
p32x_sh2reg_write8(a, d, sh2);
|
||||
goto out;
|
||||
}
|
||||
|
||||
sh2_write8_unmapped(a, d, sh2);
|
||||
out:
|
||||
DRC_RESTORE_SR(sh2);
|
||||
|
|
@ -1647,6 +1700,11 @@ static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
|
|||
elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
|
||||
a, d & 0xffff, sh2_pc(sh2));
|
||||
|
||||
if ((a & 0x3ffc0) == 0x4000) {
|
||||
p32x_sh2reg_write16(a, d, sh2);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (Pico32x.regs[0] & P32XS_FM) {
|
||||
if ((a & 0x3fff0) == 0x4100) {
|
||||
sh2->poll_cnt = 0;
|
||||
|
|
@ -1662,11 +1720,6 @@ static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
|
|||
}
|
||||
}
|
||||
|
||||
if ((a & 0x3ffc0) == 0x4000) {
|
||||
p32x_sh2reg_write16(a, d, sh2);
|
||||
goto out;
|
||||
}
|
||||
|
||||
sh2_write16_unmapped(a, d, sh2);
|
||||
out:
|
||||
DRC_RESTORE_SR(sh2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue