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move saving SH2 SR into memory access and do so only if needed

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This commit is contained in:
kub 2019-03-27 21:58:32 +01:00
parent 9031406131
commit ff0eaa11d9
4 changed files with 84 additions and 27 deletions
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14
cpu/sh2/compiler.c
View file

@ -1231,11 +1231,11 @@ static int emit_memhandler_read(int size)
rcache_clean();
#ifndef DCR_SR_REG
// must writeback cycles for poll detection stuff
// FIXME: rm
if (reg_map_g2h[SHR_SR] != -1)
emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
#endif
arg1 = rcache_get_tmp_arg(1);
emith_move_r_r_ptr(arg1, CONTEXT_REG);
switch (size) {
@ -1244,10 +1244,10 @@ static int emit_memhandler_read(int size)
case 2: emith_call(sh2_drc_read32); break; // 32
}
rcache_invalidate();
#ifndef DCR_SR_REG
if (reg_map_g2h[SHR_SR] != -1)
emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
#endif
return rcache_get_tmp_ret();
}
@ -1255,10 +1255,10 @@ static int emit_memhandler_read(int size)
static void emit_memhandler_write(int size)
{
int arg2;
#ifndef DCR_SR_REG
if (reg_map_g2h[SHR_SR] != -1)
emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
#endif
rcache_clean();
arg2 = rcache_get_tmp_arg(2);
@ -1270,8 +1270,10 @@ static void emit_memhandler_write(int size)
}
rcache_invalidate();
#ifndef DCR_SR_REG
if (reg_map_g2h[SHR_SR] != -1)
emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
#endif
}
// rd = @(Rs,#offs)

28
cpu/sh2/compiler.h
View file

@ -13,7 +13,7 @@ void sh2_drc_frame(void);
#define sh2_drc_frame()
#endif
#define BLOCK_INSN_LIMIT 128
#define BLOCK_INSN_LIMIT 1024
/* op_flags */
#define OF_DELAY_OP (1 << 0)
@ -25,3 +25,29 @@ void sh2_drc_frame(void);
void scan_block(unsigned int base_pc, int is_slave,
unsigned char *op_flags, unsigned int *end_pc,
unsigned int *end_literals);
#if defined(DRC_SH2)
// direct access to some host CPU registers used by the DRC
// XXX MUST match definitions in cpu/sh2/compiler.c
#if defined(_arm__)
#define DRC_SR_REG r10
#elif defined(__i386__)
#define DRC_SR_REG edi
#else
#warning "direct DRC register access not available for this host"
#endif
#ifdef DCR_SR_REG
#define DRC_DECLARE_SR register int sh2_sr asm(#DCR_SR_REG)
#define DRC_SAVE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_BUSY)) == SH2_STATE_RUN) \
sh2->sr = sh2_sr;
#define DRC_RESTORE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_BUSY)) == SH2_STATE_RUN) \
sh2_sr = sh2->sr;
#else
#define DRC_DECLARE_SR
#define DRC_SAVE_SR(sh2)
#define DRC_RESTORE_SR(sh2)
#endif
#endif