13 commits

Author	SHA1	Message	Date
kub	f2d19ddf2a	sh2 drc, small improvements and bug fixes for code emitters	2019-11-19 21:59:44 +01:00
kub	e7ee501075	sh2 drc: RISC-V (RV64IM) code emitter, some work on MIPS64	2019-11-13 21:56:11 +01:00
kub	aaea8e3ecd	sh2 drc: optimizations for MIPS code emitting	2019-11-09 10:30:57 +01:00
kub	9bd6706dca	sh2 drc: moved host register assignment to code emitters, minor bugfixing	2019-11-09 10:24:52 +01:00
kub	a6c0ab7d99	sh2 drc bugfix for aarch64/mips	2019-10-12 00:26:11 +02:00
kub	7869213d35	sh2 drc: speed optimization and bugfixing	2019-10-11 00:51:19 +02:00
kub	a0f5ba4067	sh2 drc: bug fixing and optimization in register cache and branch handling	2019-10-04 17:11:18 +02:00
kub	06bc3c0693	sh2 drc: drc exit, block linking and branch handling revised	2019-09-28 16:39:26 +02:00
kub	36614252d9	sh2 drc: improved RTS call stack cache	2019-09-19 22:14:28 +02:00
kub	f53e166cf4	various smallish optimizations, cleanups, and bug fixes	2019-09-17 23:05:35 +02:00
kub	fe344bd3d8	cleanup and microoptimizations in SH2 hw handling	2019-08-31 17:37:18 +02:00
kub	8284ab7107	various small fixes and optimsations	2019-08-16 15:14:41 +02:00
kub	d80a5fd2ab	sh2 drc: add mipsel backend for MIPS32 Release 1 (for JZ47xx)	2019-07-30 16:34:40 +02:00