mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
0b5e829689
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@381 be3aeb3a-fb24-0410-a615-afba39da0efa
2149 lines
50 KiB
C
2149 lines
50 KiB
C
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#include "../../PicoInt.h"
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#include "compiler.h"
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static unsigned int *block_table[0x5090/2];
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static unsigned int *block_table_iram[15][0x800/2];
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static unsigned int *tcache_ptr = NULL;
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static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x0c9a
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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#endif
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#define EMBED_INTERPRETER
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#define ssp1601_reset ssp1601_reset_local
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#define ssp1601_run ssp1601_run_local
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#define GET_PC() rPC
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#define GET_PPC_OFFS() (GET_PC()*2 - 2)
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#define SET_PC(d) { rPC = d; } /* must return to dispatcher after this */
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//#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
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//#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
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//#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
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#include "ssp16.c"
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#include "gen_arm.c"
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// -----------------------------------------------------
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// ld d, s
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static void op00(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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PC = ((unsigned short *)(void *)&op) + 1; /* FIXME: needed for interpreter */
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if (op == 0) return; // nop
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if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
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// not sure. MAME claims that only hi word is transfered.
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read_P(); // update P
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rA32 = rP.v;
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}
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else
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{
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tmpv = REG_READ(op & 0x0f);
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REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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}
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// ld d, (ri)
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static void op01(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ld (ri), s
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static void op02(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv);
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}
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// ldi d, imm
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static void op04(unsigned int op, unsigned int imm)
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{
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REG_WRITE((op & 0xf0) >> 4, imm);
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}
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// ld d, ((ri))
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static void op05(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ldi (ri), imm
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static void op06(unsigned int op, unsigned int imm)
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{
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ptr1_write(op, imm);
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}
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// ld adr, a
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static void op07(unsigned int op, unsigned int imm)
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{
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ssp->RAM[op & 0x1ff] = rA;
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}
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// ld d, ri
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static void op09(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ld ri, s
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static void op0a(unsigned int op, unsigned int imm)
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{
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rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4);
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}
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// ldi ri, simm (also op0d op0e op0f)
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static void op0c(unsigned int op, unsigned int imm)
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{
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rIJ[(op>>8)&7] = op;
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}
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// call cond, addr
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static void op24(unsigned int op, unsigned int imm)
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{
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int cond = 0;
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do {
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COND_CHECK
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if (cond) { int new_PC = imm; write_STACK(GET_PC()); SET_PC(new_PC); }
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}
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while (0);
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}
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// ld d, (a)
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static void op25(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// bra cond, addr
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static void op26(unsigned int op, unsigned int imm)
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{
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do
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{
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int cond = 0;
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COND_CHECK
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if (cond) SET_PC(imm);
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}
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while (0);
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}
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// mod cond, op
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static void op48(unsigned int op, unsigned int imm)
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{
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do
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{
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int cond = 0;
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COND_CHECK
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if (cond) {
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switch (op & 7) {
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case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
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case 3: rA32 <<= 1; break; // shl
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case 6: rA32 = -(signed int)rA32; break; // neg
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case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
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default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
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op&7, GET_PPC_OFFS());
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}
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UPD_ACC_ZN // ?
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}
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}
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while(0);
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}
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// mpys?
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static void op1b(unsigned int op, unsigned int imm)
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{
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read_P(); // update P
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rA32 -= rP.v; // maybe only upper word?
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UPD_ACC_ZN // there checking flags after this
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// mpya (rj), (ri), b
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static void op4b(unsigned int op, unsigned int imm)
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{
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read_P(); // update P
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rA32 += rP.v; // confirmed to be 32bit
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UPD_ACC_ZN // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// mld (rj), (ri), b
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static void op5b(unsigned int op, unsigned int imm)
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{
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rA32 = 0;
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rST &= 0x0fff; // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// OP a, s
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static void op10(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv);
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}
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while(0);
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}
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static void op30(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv);
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}
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while(0);
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}
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static void op40(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv);
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}
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while(0);
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}
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static void op50(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv);
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}
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while(0);
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}
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static void op60(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv);
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}
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while(0);
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}
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static void op70(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv);
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}
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while(0);
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}
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// OP a, (ri)
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static void op11(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_SUBA(tmpv);
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}
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static void op31(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_CMPA(tmpv);
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}
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static void op41(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ADDA(tmpv);
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}
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static void op51(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ANDA(tmpv);
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}
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static void op61(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ORA (tmpv);
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}
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static void op71(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_EORA(tmpv);
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}
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// OP a, adr
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static void op03(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv);
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}
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static void op13(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv);
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}
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static void op33(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv);
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}
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static void op43(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv);
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}
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static void op53(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv);
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}
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static void op63(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv);
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}
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static void op73(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv);
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}
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// OP a, imm
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static void op14(unsigned int op, unsigned int imm)
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{
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OP_SUBA(imm);
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}
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static void op34(unsigned int op, unsigned int imm)
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{
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OP_CMPA(imm);
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}
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static void op44(unsigned int op, unsigned int imm)
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{
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OP_ADDA(imm);
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}
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static void op54(unsigned int op, unsigned int imm)
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{
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OP_ANDA(imm);
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}
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static void op64(unsigned int op, unsigned int imm)
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{
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OP_ORA (imm);
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}
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static void op74(unsigned int op, unsigned int imm)
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{
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OP_EORA(imm);
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}
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// OP a, ((ri))
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static void op15(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_SUBA(tmpv);
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}
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static void op35(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_CMPA(tmpv);
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}
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static void op45(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ADDA(tmpv);
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}
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static void op55(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ANDA(tmpv);
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}
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static void op65(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ORA (tmpv);
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}
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static void op75(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_EORA(tmpv);
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}
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// OP a, ri
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static void op19(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_SUBA(tmpv);
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}
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static void op39(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_CMPA(tmpv);
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}
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static void op49(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ADDA(tmpv);
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}
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static void op59(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ANDA(tmpv);
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}
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static void op69(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ORA (tmpv);
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}
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static void op79(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_EORA(tmpv);
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}
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// OP simm
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static void op1c(unsigned int op, unsigned int imm)
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{
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OP_SUBA(op & 0xff);
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}
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static void op3c(unsigned int op, unsigned int imm)
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{
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OP_CMPA(op & 0xff);
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}
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static void op4c(unsigned int op, unsigned int imm)
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{
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OP_ADDA(op & 0xff);
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}
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static void op5c(unsigned int op, unsigned int imm)
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{
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OP_ANDA(op & 0xff);
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}
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static void op6c(unsigned int op, unsigned int imm)
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{
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OP_ORA (op & 0xff);
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}
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static void op7c(unsigned int op, unsigned int imm)
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{
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OP_EORA(op & 0xff);
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}
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typedef void (in_func)(unsigned int op, unsigned int imm);
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static in_func *in_funcs[0x80] =
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{
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op00, op01, op02, op03, op04, op05, op06, op07,
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NULL, op09, op0a, NULL, op0c, op0c, op0c, op0c,
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op10, op11, NULL, op13, op14, op15, NULL, NULL,
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NULL, op19, NULL, op1b, op1c, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, op24, op25, op26, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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op30, op31, NULL, op33, op34, op35, NULL, NULL,
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NULL, op39, NULL, NULL, op3c, NULL, NULL, NULL,
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op40, op41, NULL, op43, op44, op45, NULL, NULL,
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op48, op49, NULL, op4b, op4c, NULL, NULL, NULL,
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op50, op51, NULL, op53, op54, op55, NULL, NULL,
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NULL, op59, NULL, op5b, op5c, NULL, NULL, NULL,
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op60, op61, NULL, op63, op64, op65, NULL, NULL,
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NULL, op69, NULL, NULL, op6c, NULL, NULL, NULL,
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op70, op71, NULL, op73, op74, op75, NULL, NULL,
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NULL, op79, NULL, NULL, op7c, NULL, NULL, NULL,
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};
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static u32 ssp_pm_read(int reg)
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{
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u32 d = 0, mode;
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if (ssp->emu_status & SSP_PMC_SET)
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{
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ssp->pmac_read[reg] = rPMC.v;
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ssp->emu_status &= ~SSP_PMC_SET;
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return 0;
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}
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// just in case
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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mode = ssp->pmac_read[reg]>>16;
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if ((mode & 0xfff0) == 0x0800) // ROM
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{
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d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
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ssp->pmac_read[reg] += 1;
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}
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else if ((mode & 0x47ff) == 0x0018) // DRAM
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{
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unsigned short *dram = (unsigned short *)svp->dram;
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int inc = get_inc(mode);
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d = dram[ssp->pmac_read[reg]&0xffff];
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ssp->pmac_read[reg] += inc;
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}
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// PMC value corresponds to last PMR accessed
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rPMC.v = ssp->pmac_read[reg];
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return d;
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}
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static void ssp_pm_write(u32 d, int reg)
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{
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unsigned short *dram;
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int mode, addr;
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if (ssp->emu_status & SSP_PMC_SET)
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{
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|
ssp->pmac_write[reg] = rPMC.v;
|
|
ssp->emu_status &= ~SSP_PMC_SET;
|
|
return;
|
|
}
|
|
|
|
// just in case
|
|
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
|
|
|
|
dram = (unsigned short *)svp->dram;
|
|
mode = ssp->pmac_write[reg]>>16;
|
|
addr = ssp->pmac_write[reg]&0xffff;
|
|
if ((mode & 0x43ff) == 0x0018) // DRAM
|
|
{
|
|
int inc = get_inc(mode);
|
|
if (mode & 0x0400) {
|
|
overwrite_write(dram[addr], d);
|
|
} else dram[addr] = d;
|
|
ssp->pmac_write[reg] += inc;
|
|
}
|
|
else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
|
|
{
|
|
if (mode & 0x0400) {
|
|
overwrite_write(dram[addr], d);
|
|
} else dram[addr] = d;
|
|
ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
|
|
}
|
|
else if ((mode & 0x47ff) == 0x001c) // IRAM
|
|
{
|
|
int inc = get_inc(mode);
|
|
((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
|
|
ssp->pmac_write[reg] += inc;
|
|
ssp->drc.iram_dirty = 1;
|
|
}
|
|
|
|
rPMC.v = ssp->pmac_write[reg];
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------
|
|
|
|
// 14 IRAM blocks
|
|
static unsigned char iram_context_map[] =
|
|
{
|
|
0, 0, 0, 0, 1, 0, 0, 0, // 04
|
|
0, 0, 0, 0, 0, 0, 2, 0, // 0e
|
|
0, 0, 0, 0, 0, 3, 0, 4, // 15 17
|
|
5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
|
|
8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
|
|
0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0,11, 0, 0,12, 0, 0, // 32 35
|
|
13,14, 0, 0, 0, 0, 0, 0 // 38 39
|
|
};
|
|
|
|
static int get_iram_context(void)
|
|
{
|
|
unsigned char *ir = (unsigned char *)svp->iram_rom;
|
|
int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
|
|
val1 = iram_context_map[(val>>1)&0x3f];
|
|
|
|
if (val1 == 0) {
|
|
printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
|
|
//debug_dump2file(name, svp->iram_rom, 0x800);
|
|
exit(1);
|
|
}
|
|
// elprintf(EL_ANOMALY, "iram_context: %02i", val1);
|
|
return val1;
|
|
}
|
|
|
|
// -----------------------------------------------------
|
|
|
|
/* regs with known values */
|
|
static struct
|
|
{
|
|
ssp_reg_t gr[8];
|
|
unsigned char r[8];
|
|
unsigned int pmac_read[5];
|
|
unsigned int pmac_write[5];
|
|
ssp_reg_t pmc;
|
|
unsigned int emu_status;
|
|
} known_regs;
|
|
|
|
#define KRREG_X (1 << SSP_X)
|
|
#define KRREG_Y (1 << SSP_Y)
|
|
#define KRREG_A (1 << SSP_A) /* AH only */
|
|
#define KRREG_ST (1 << SSP_ST)
|
|
#define KRREG_STACK (1 << SSP_STACK)
|
|
#define KRREG_PC (1 << SSP_PC)
|
|
#define KRREG_P (1 << SSP_P)
|
|
#define KRREG_PR0 (1 << 8)
|
|
#define KRREG_PR4 (1 << 12)
|
|
#define KRREG_AL (1 << 16)
|
|
#define KRREG_PMCM (1 << 18) /* only mode word of PMC */
|
|
#define KRREG_PMC (1 << 19)
|
|
#define KRREG_PM0R (1 << 20)
|
|
#define KRREG_PM1R (1 << 21)
|
|
#define KRREG_PM2R (1 << 22)
|
|
#define KRREG_PM3R (1 << 23)
|
|
#define KRREG_PM4R (1 << 24)
|
|
#define KRREG_PM0W (1 << 25)
|
|
#define KRREG_PM1W (1 << 26)
|
|
#define KRREG_PM2W (1 << 27)
|
|
#define KRREG_PM3W (1 << 28)
|
|
#define KRREG_PM4W (1 << 29)
|
|
|
|
/* bitfield of known register values */
|
|
static u32 known_regb = 0;
|
|
|
|
/* known vals, which need to be flushed
|
|
* (only ST, P, r0-r7, PMCx, PMxR, PMxW)
|
|
* ST means flags are being held in ARM PSR
|
|
* P means that it needs to be recalculated
|
|
*/
|
|
static u32 dirty_regb = 0;
|
|
|
|
/* known values of host regs.
|
|
* -1 - unknown
|
|
* 000000-00ffff - 16bit value
|
|
* 100000-10ffff - base reg (r7) + 16bit val
|
|
* 0r0000 - means reg (low) eq gr[r].h, r != AL
|
|
*/
|
|
static int hostreg_r[4];
|
|
|
|
static void hostreg_clear(void)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 4; i++)
|
|
hostreg_r[i] = -1;
|
|
}
|
|
|
|
static void hostreg_sspreg_changed(int sspreg)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 4; i++)
|
|
if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
|
|
}
|
|
|
|
|
|
#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
|
|
#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
|
|
|
|
static void tr_unhandled(void)
|
|
{
|
|
FILE *f = fopen("tcache.bin", "wb");
|
|
fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
|
|
fclose(f);
|
|
printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
|
|
exit(1);
|
|
}
|
|
|
|
/* update P, if needed. Trashes r0 */
|
|
static void tr_flush_dirty_P(void)
|
|
{
|
|
// TODO: const regs
|
|
if (!(dirty_regb & KRREG_P)) return;
|
|
EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
|
|
EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
|
|
EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
|
|
EOP_MUL(10, 0, 10); // mul r10, r0, r10
|
|
dirty_regb &= ~KRREG_P;
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
/* write dirty pr to host reg. Nothing is trashed */
|
|
static void tr_flush_dirty_pr(int r)
|
|
{
|
|
int ror = 0, reg;
|
|
|
|
if (!(dirty_regb & (1 << (r+8)))) return;
|
|
|
|
switch (r&3) {
|
|
case 0: ror = 0; break;
|
|
case 1: ror = 24/2; break;
|
|
case 2: ror = 16/2; break;
|
|
}
|
|
reg = (r < 4) ? 8 : 9;
|
|
EOP_BIC_IMM(reg,reg,ror,0xff);
|
|
if (known_regs.r[r] != 0)
|
|
EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
|
|
dirty_regb &= ~(1 << (r+8));
|
|
}
|
|
|
|
/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
|
|
static void tr_flush_dirty_prs(void)
|
|
{
|
|
int i, ror = 0, reg;
|
|
int dirty = dirty_regb >> 8;
|
|
/* r0-r7 */
|
|
for (i = 0; dirty && i < 8; i++, dirty >>= 1)
|
|
{
|
|
if (!(dirty&1)) continue;
|
|
switch (i&3) {
|
|
case 0: ror = 0; break;
|
|
case 1: ror = 24/2; break;
|
|
case 2: ror = 16/2; break;
|
|
}
|
|
reg = (i < 4) ? 8 : 9;
|
|
EOP_BIC_IMM(reg,reg,ror,0xff);
|
|
if (known_regs.r[i] != 0)
|
|
EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
|
|
}
|
|
dirty_regb &= ~0xff00;
|
|
}
|
|
|
|
/* write dirty pr and "forget" it. Nothing is trashed. */
|
|
static void tr_release_pr(int r)
|
|
{
|
|
tr_flush_dirty_pr(r);
|
|
known_regb &= ~(1 << (r+8));
|
|
}
|
|
|
|
/* fush ARM PSR to r6. Trashes r1 */
|
|
static void tr_flush_dirty_ST(void)
|
|
{
|
|
if (!(dirty_regb & KRREG_ST)) return;
|
|
EOP_BIC_IMM(6,6,0,0x0f);
|
|
EOP_MRS(1);
|
|
EOP_ORR_REG_LSR(6,6,1,28);
|
|
dirty_regb &= ~KRREG_ST;
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
/* inverse of above. Trashes r1 */
|
|
static void tr_make_dirty_ST(void)
|
|
{
|
|
if (dirty_regb & KRREG_ST) return;
|
|
if (known_regb & KRREG_ST) {
|
|
int flags = 0;
|
|
if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
|
|
if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
|
|
EOP_MSR_IMM(4/2, flags);
|
|
} else {
|
|
EOP_MOV_REG_LSL(1, 6, 28);
|
|
EOP_MSR_REG(1);
|
|
hostreg_r[1] = -1;
|
|
}
|
|
dirty_regb |= KRREG_ST;
|
|
}
|
|
|
|
/* load 16bit val into host reg r0-r3. Nothing is trashed */
|
|
static void tr_mov16(int r, int val)
|
|
{
|
|
if (hostreg_r[r] != val) {
|
|
emit_mov_const(A_COND_AL, r, val);
|
|
hostreg_r[r] = val;
|
|
}
|
|
}
|
|
|
|
static void tr_mov16_cond(int cond, int r, int val)
|
|
{
|
|
emit_mov_const(cond, r, val);
|
|
hostreg_r[r] = -1;
|
|
}
|
|
|
|
/* trashes r0 */
|
|
static void tr_flush_dirty_pmcrs(void)
|
|
{
|
|
u32 i, val = (u32)-1;
|
|
if (!(dirty_regb & 0x3ff80000)) return;
|
|
|
|
if (dirty_regb & KRREG_PMC) {
|
|
val = known_regs.pmc.v;
|
|
emit_mov_const(A_COND_AL, 1, val);
|
|
EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
|
|
|
|
if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
|
|
printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
|
|
tr_unhandled();
|
|
}
|
|
}
|
|
for (i = 0; i < 5; i++)
|
|
{
|
|
if (dirty_regb & (1 << (20+i))) {
|
|
if (val != known_regs.pmac_read[i]) {
|
|
val = known_regs.pmac_read[i];
|
|
emit_mov_const(A_COND_AL, 1, val);
|
|
}
|
|
EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
|
|
}
|
|
if (dirty_regb & (1 << (25+i))) {
|
|
if (val != known_regs.pmac_write[i]) {
|
|
val = known_regs.pmac_write[i];
|
|
emit_mov_const(A_COND_AL, 1, val);
|
|
}
|
|
EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
|
|
}
|
|
}
|
|
dirty_regb &= ~0x3ff80000;
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
/* read bank word to r0 (upper bits zero). Thrashes r1. */
|
|
static void tr_bank_read(int addr) /* word addr 0-0x1ff */
|
|
{
|
|
int breg = 7;
|
|
if (addr > 0x7f) {
|
|
if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
|
|
EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
|
|
hostreg_r[1] = 0x100000|((addr&0x180)<<1);
|
|
}
|
|
breg = 1;
|
|
}
|
|
EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
/* write r0 to bank. Trashes r1. */
|
|
static void tr_bank_write(int addr)
|
|
{
|
|
int breg = 7;
|
|
if (addr > 0x7f) {
|
|
if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
|
|
EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
|
|
hostreg_r[1] = 0x100000|((addr&0x180)<<1);
|
|
}
|
|
breg = 1;
|
|
}
|
|
EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
|
|
}
|
|
|
|
/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
|
|
static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
|
|
{
|
|
int modulo_shift = -1; /* unknown */
|
|
|
|
if (mod == 0) return;
|
|
|
|
if (!need_modulo || mod == 1) // +!
|
|
modulo_shift = 8;
|
|
else if (need_modulo && (known_regb & KRREG_ST)) {
|
|
modulo_shift = known_regs.gr[SSP_ST].h & 7;
|
|
if (modulo_shift == 0) modulo_shift = 8;
|
|
}
|
|
|
|
if (modulo_shift == -1)
|
|
{
|
|
int reg = (r < 4) ? 8 : 9;
|
|
tr_release_pr(r);
|
|
if (dirty_regb & KRREG_ST) {
|
|
// avoid flushing ARM flags
|
|
EOP_AND_IMM(1, 6, 0, 0x70);
|
|
EOP_SUB_IMM(1, 1, 0, 0x10);
|
|
EOP_AND_IMM(1, 1, 0, 0x70);
|
|
EOP_ADD_IMM(1, 1, 0, 0x10);
|
|
} else {
|
|
EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
|
|
}
|
|
EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
|
|
EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
|
|
EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
|
|
if (r&3)
|
|
EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
|
|
EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
|
|
if (mod == 2)
|
|
EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
|
|
else EOP_ADD_REG2_LSL(reg,reg,3,2);
|
|
EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
|
|
EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
|
|
hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
|
|
}
|
|
else if (known_regb & (1 << (r + 8)))
|
|
{
|
|
int modulo = (1 << modulo_shift) - 1;
|
|
if (mod == 2)
|
|
known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
|
|
else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
|
|
}
|
|
else
|
|
{
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
|
|
EOP_MOV_REG_ROR(reg,reg,ror);
|
|
// {add|sub} reg, reg, #1<<shift
|
|
EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
|
|
EOP_MOV_REG_ROR(reg,reg,32-ror);
|
|
}
|
|
}
|
|
|
|
/* handle writes r0 to (rX). Trashes r1.
|
|
* fortunately we can ignore modulo increment modes for writes. */
|
|
static void tr_rX_write(int op)
|
|
{
|
|
if ((op&3) == 3)
|
|
{
|
|
int mod = (op>>2) & 3; // direct addressing
|
|
tr_bank_write((op & 0x100) + mod);
|
|
}
|
|
else
|
|
{
|
|
int r = (op&3) | ((op>>6)&4);
|
|
if (known_regb & (1 << (r + 8))) {
|
|
tr_bank_write((op&0x100) | known_regs.r[r]);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((4 - (r&3))*8) & 0x1f;
|
|
EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
|
|
if (r >= 4)
|
|
EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
|
|
if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
|
|
else EOP_ADD_REG_LSL(1,7,1,1);
|
|
EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
|
|
hostreg_r[1] = -1;
|
|
}
|
|
tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
|
|
}
|
|
}
|
|
|
|
/* read (rX) to r0. Trashes r1-r3. */
|
|
static void tr_rX_read(int r, int mod)
|
|
{
|
|
if ((r&3) == 3)
|
|
{
|
|
tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
|
|
}
|
|
else
|
|
{
|
|
if (known_regb & (1 << (r + 8))) {
|
|
tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((4 - (r&3))*8) & 0x1f;
|
|
EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
|
|
if (r >= 4)
|
|
EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
|
|
if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
|
|
else EOP_ADD_REG_LSL(1,7,1,1);
|
|
EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
}
|
|
tr_ptrr_mod(r, mod, 1, 1);
|
|
}
|
|
}
|
|
|
|
/* read ((rX)) to r0. Trashes r1,r2. */
|
|
static void tr_rX_read2(int op)
|
|
{
|
|
int r = (op&3) | ((op>>6)&4); // src
|
|
|
|
if ((r&3) == 3) {
|
|
tr_bank_read((op&0x100) | ((op>>2)&3));
|
|
} else if (known_regb & (1 << (r+8))) {
|
|
tr_bank_read((op&0x100) | known_regs.r[r]);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((4 - (r&3))*8) & 0x1f;
|
|
EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
|
|
if (r >= 4)
|
|
EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
|
|
if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
|
|
else EOP_ADD_REG_LSL(1,7,1,1);
|
|
EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
|
|
}
|
|
EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
|
|
EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
|
|
EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
|
|
if ((r&3) == 3) {
|
|
tr_bank_write((op&0x100) | ((op>>2)&3));
|
|
} else if (known_regb & (1 << (r+8))) {
|
|
tr_bank_write((op&0x100) | known_regs.r[r]);
|
|
} else {
|
|
EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
|
|
hostreg_r[1] = -1;
|
|
}
|
|
EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
|
|
hostreg_r[0] = hostreg_r[2] = -1;
|
|
}
|
|
|
|
/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
|
|
static int tr_cond_check(int op)
|
|
{
|
|
int f = (op & 0x100) >> 8;
|
|
switch (op&0xf0) {
|
|
case 0x00: return A_COND_AL; /* always true */
|
|
case 0x50: /* Z matches f(?) bit */
|
|
if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
|
|
EOP_TST_IMM(6, 0, 4);
|
|
return f ? A_COND_NE : A_COND_EQ;
|
|
case 0x70: /* N matches f(?) bit */
|
|
if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
|
|
EOP_TST_IMM(6, 0, 8);
|
|
return f ? A_COND_NE : A_COND_EQ;
|
|
default:
|
|
printf("unimplemented cond?\n");
|
|
tr_unhandled();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int tr_neg_cond(int cond)
|
|
{
|
|
switch (cond) {
|
|
case A_COND_AL: printf("neg for AL?\n"); exit(1);
|
|
case A_COND_EQ: return A_COND_NE;
|
|
case A_COND_NE: return A_COND_EQ;
|
|
case A_COND_MI: return A_COND_PL;
|
|
case A_COND_PL: return A_COND_MI;
|
|
default: printf("bad cond for neg\n"); exit(1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int tr_aop_ssp2arm(int op)
|
|
{
|
|
switch (op) {
|
|
case 1: return A_OP_SUB;
|
|
case 3: return A_OP_CMP;
|
|
case 4: return A_OP_ADD;
|
|
case 5: return A_OP_AND;
|
|
case 6: return A_OP_ORR;
|
|
case 7: return A_OP_EOR;
|
|
}
|
|
|
|
tr_unhandled();
|
|
return 0;
|
|
}
|
|
|
|
// -----------------------------------------------------
|
|
|
|
//@ r4: XXYY
|
|
//@ r5: A
|
|
//@ r6: STACK and emu flags
|
|
//@ r7: SSP context
|
|
//@ r10: P
|
|
|
|
// read general reg to r0. Trashes r1
|
|
static void tr_GR0_to_r0(int op)
|
|
{
|
|
tr_mov16(0, 0xffff);
|
|
}
|
|
|
|
static void tr_X_to_r0(int op)
|
|
{
|
|
if (hostreg_r[0] != (SSP_X<<16)) {
|
|
EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
|
|
hostreg_r[0] = SSP_X<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_Y_to_r0(int op)
|
|
{
|
|
if (hostreg_r[0] != (SSP_Y<<16)) {
|
|
EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
|
|
hostreg_r[0] = SSP_Y<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_A_to_r0(int op)
|
|
{
|
|
if (hostreg_r[0] != (SSP_A<<16)) {
|
|
EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
|
|
hostreg_r[0] = SSP_A<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_ST_to_r0(int op)
|
|
{
|
|
// VR doesn't need much accuracy here..
|
|
EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
|
|
EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
static void tr_STACK_to_r0(int op)
|
|
{
|
|
// 448
|
|
EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
|
|
EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
|
|
EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
|
|
EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
|
|
EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_PC_to_r0(int op)
|
|
{
|
|
tr_mov16(0, known_regs.gr[SSP_PC].h);
|
|
}
|
|
|
|
static void tr_P_to_r0(int op)
|
|
{
|
|
tr_flush_dirty_P();
|
|
EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
static void tr_AL_to_r0(int op)
|
|
{
|
|
if (op == 0x000f) {
|
|
if (known_regb & KRREG_PMC) {
|
|
known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
|
|
} else {
|
|
EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
|
|
EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
|
|
EOP_STR_IMM(0,7,0x484);
|
|
}
|
|
}
|
|
|
|
if (hostreg_r[0] != (SSP_AL<<16)) {
|
|
EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
|
|
hostreg_r[0] = SSP_AL<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_PMX_to_r0(int reg)
|
|
{
|
|
if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
|
|
{
|
|
known_regs.pmac_read[reg] = known_regs.pmc.v;
|
|
known_regs.emu_status &= ~SSP_PMC_SET;
|
|
known_regb |= 1 << (20+reg);
|
|
dirty_regb |= 1 << (20+reg);
|
|
return;
|
|
}
|
|
|
|
if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
|
|
{
|
|
u32 pmcv = known_regs.pmac_read[reg];
|
|
int mode = pmcv>>16;
|
|
known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
|
|
|
|
if ((mode & 0xfff0) == 0x0800)
|
|
{
|
|
EOP_LDR_IMM(1,7,0x488); // rom_ptr
|
|
emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
|
|
EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
|
|
known_regs.pmac_read[reg] += 1;
|
|
}
|
|
else if ((mode & 0x47ff) == 0x0018) // DRAM
|
|
{
|
|
int inc = get_inc(mode);
|
|
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
|
emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
|
|
EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
|
|
if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
|
|
{
|
|
int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
|
|
tr_flush_dirty_ST();
|
|
EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
|
|
EOP_TST_REG_SIMPLE(0,0);
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // addeq r11, r11, #1024
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
|
|
EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
|
|
}
|
|
known_regs.pmac_read[reg] += inc;
|
|
}
|
|
else
|
|
{
|
|
tr_unhandled();
|
|
}
|
|
known_regs.pmc.v = known_regs.pmac_read[reg];
|
|
//known_regb |= KRREG_PMC;
|
|
dirty_regb |= KRREG_PMC;
|
|
dirty_regb |= 1 << (20+reg);
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
return;
|
|
}
|
|
|
|
known_regb &= ~KRREG_PMC;
|
|
dirty_regb &= ~KRREG_PMC;
|
|
known_regb &= ~(1 << (20+reg));
|
|
dirty_regb &= ~(1 << (20+reg));
|
|
|
|
// call the C code to handle this
|
|
tr_flush_dirty_ST();
|
|
//tr_flush_dirty_pmcrs();
|
|
tr_mov16(0, reg);
|
|
emit_call(ssp_pm_read);
|
|
hostreg_clear();
|
|
}
|
|
|
|
static void tr_PM0_to_r0(int op)
|
|
{
|
|
tr_PMX_to_r0(0);
|
|
}
|
|
|
|
static void tr_PM1_to_r0(int op)
|
|
{
|
|
tr_PMX_to_r0(1);
|
|
}
|
|
|
|
static void tr_PM2_to_r0(int op)
|
|
{
|
|
tr_PMX_to_r0(2);
|
|
}
|
|
|
|
static void tr_XST_to_r0(int op)
|
|
{
|
|
EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
|
|
EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
|
|
}
|
|
|
|
static void tr_PM4_to_r0(int op)
|
|
{
|
|
tr_PMX_to_r0(4);
|
|
}
|
|
|
|
static void tr_PMC_to_r0(int op)
|
|
{
|
|
if (known_regb & KRREG_PMC)
|
|
{
|
|
if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
|
|
known_regs.emu_status |= SSP_PMC_SET;
|
|
known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
|
|
// do nothing - this is handled elsewhere
|
|
} else {
|
|
tr_mov16(0, known_regs.pmc.l);
|
|
known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
|
|
tr_flush_dirty_ST();
|
|
if (op != 0x000e)
|
|
EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
|
|
EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
|
|
EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
|
|
EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
|
|
EOP_STR_IMM(1,7,0x484);
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
}
|
|
}
|
|
|
|
|
|
typedef void (tr_read_func)(int op);
|
|
|
|
static tr_read_func *tr_read_funcs[16] =
|
|
{
|
|
tr_GR0_to_r0,
|
|
tr_X_to_r0,
|
|
tr_Y_to_r0,
|
|
tr_A_to_r0,
|
|
tr_ST_to_r0,
|
|
tr_STACK_to_r0,
|
|
tr_PC_to_r0,
|
|
tr_P_to_r0,
|
|
tr_PM0_to_r0,
|
|
tr_PM1_to_r0,
|
|
tr_PM2_to_r0,
|
|
tr_XST_to_r0,
|
|
tr_PM4_to_r0,
|
|
(tr_read_func *)tr_unhandled,
|
|
tr_PMC_to_r0,
|
|
tr_AL_to_r0
|
|
};
|
|
|
|
|
|
// write r0 to general reg handlers. Trashes r1
|
|
#define TR_WRITE_R0_TO_REG(reg) \
|
|
{ \
|
|
hostreg_sspreg_changed(reg); \
|
|
hostreg_r[0] = (reg)<<16; \
|
|
if (const_val != -1) { \
|
|
known_regs.gr[reg].h = const_val; \
|
|
known_regb |= 1 << (reg); \
|
|
} else { \
|
|
known_regb &= ~(1 << (reg)); \
|
|
} \
|
|
}
|
|
|
|
static void tr_r0_to_GR0(int const_val)
|
|
{
|
|
// do nothing
|
|
}
|
|
|
|
static void tr_r0_to_X(int const_val)
|
|
{
|
|
EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
|
|
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
|
|
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
|
|
dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
|
|
TR_WRITE_R0_TO_REG(SSP_X);
|
|
}
|
|
|
|
static void tr_r0_to_Y(int const_val)
|
|
{
|
|
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
|
|
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
|
|
EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
|
|
dirty_regb |= KRREG_P;
|
|
TR_WRITE_R0_TO_REG(SSP_Y);
|
|
}
|
|
|
|
static void tr_r0_to_A(int const_val)
|
|
{
|
|
EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
|
|
EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
|
|
EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
|
|
TR_WRITE_R0_TO_REG(SSP_A);
|
|
}
|
|
|
|
static void tr_r0_to_ST(int const_val)
|
|
{
|
|
// VR doesn't need much accuracy here..
|
|
EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
|
|
EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
|
|
EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
|
|
TR_WRITE_R0_TO_REG(SSP_ST);
|
|
hostreg_r[1] = -1;
|
|
dirty_regb &= ~KRREG_ST;
|
|
}
|
|
|
|
static void tr_r0_to_STACK(int const_val)
|
|
{
|
|
// 448
|
|
EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
|
|
EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
|
|
EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
|
|
EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
|
|
EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_r0_to_PC(int const_val)
|
|
{
|
|
EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
|
|
EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_r0_to_AL(int const_val)
|
|
{
|
|
EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
|
|
EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
|
|
EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
|
|
hostreg_sspreg_changed(SSP_AL);
|
|
if (const_val != -1) {
|
|
known_regs.gr[SSP_A].l = const_val;
|
|
known_regb |= 1 << SSP_AL;
|
|
} else
|
|
known_regb &= ~(1 << SSP_AL);
|
|
}
|
|
|
|
static void tr_r0_to_PMX(int reg)
|
|
{
|
|
if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
|
|
{
|
|
known_regs.pmac_write[reg] = known_regs.pmc.v;
|
|
known_regs.emu_status &= ~SSP_PMC_SET;
|
|
known_regb |= 1 << (25+reg);
|
|
dirty_regb |= 1 << (25+reg);
|
|
return;
|
|
}
|
|
|
|
if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
|
|
{
|
|
int mode, addr;
|
|
|
|
known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
|
|
|
|
mode = known_regs.pmac_write[reg]>>16;
|
|
addr = known_regs.pmac_write[reg]&0xffff;
|
|
if ((mode & 0x43ff) == 0x0018) // DRAM
|
|
{
|
|
int inc = get_inc(mode);
|
|
if (mode & 0x0400) tr_unhandled();
|
|
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
|
emit_mov_const(A_COND_AL, 2, addr<<1);
|
|
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
|
known_regs.pmac_write[reg] += inc;
|
|
}
|
|
else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
|
|
{
|
|
if (mode & 0x0400) tr_unhandled();
|
|
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
|
emit_mov_const(A_COND_AL, 2, addr<<1);
|
|
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
|
known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
|
|
}
|
|
else if ((mode & 0x47ff) == 0x001c) // IRAM
|
|
{
|
|
int inc = get_inc(mode);
|
|
EOP_LDR_IMM(1,7,0x48c); // iram_ptr
|
|
emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
|
|
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
|
EOP_MOV_IMM(1,0,1);
|
|
EOP_STR_IMM(1,7,0x494); // iram_dirty
|
|
known_regs.pmac_write[reg] += inc;
|
|
}
|
|
else
|
|
tr_unhandled();
|
|
|
|
known_regs.pmc.v = known_regs.pmac_write[reg];
|
|
//known_regb |= KRREG_PMC;
|
|
dirty_regb |= KRREG_PMC;
|
|
dirty_regb |= 1 << (25+reg);
|
|
hostreg_r[1] = hostreg_r[2] = -1;
|
|
return;
|
|
}
|
|
|
|
known_regb &= ~KRREG_PMC;
|
|
dirty_regb &= ~KRREG_PMC;
|
|
known_regb &= ~(1 << (25+reg));
|
|
dirty_regb &= ~(1 << (25+reg));
|
|
|
|
// call the C code to handle this
|
|
tr_flush_dirty_ST();
|
|
//tr_flush_dirty_pmcrs();
|
|
tr_mov16(1, reg);
|
|
emit_call(ssp_pm_write);
|
|
hostreg_clear();
|
|
}
|
|
|
|
static void tr_r0_to_PM0(int const_val)
|
|
{
|
|
tr_r0_to_PMX(0);
|
|
}
|
|
|
|
static void tr_r0_to_PM1(int const_val)
|
|
{
|
|
tr_r0_to_PMX(1);
|
|
}
|
|
|
|
static void tr_r0_to_PM2(int const_val)
|
|
{
|
|
tr_r0_to_PMX(2);
|
|
}
|
|
|
|
static void tr_r0_to_PM4(int const_val)
|
|
{
|
|
tr_r0_to_PMX(4);
|
|
}
|
|
|
|
static void tr_r0_to_PMC(int const_val)
|
|
{
|
|
if ((known_regb & KRREG_PMC) && const_val != -1)
|
|
{
|
|
if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
|
|
known_regs.emu_status |= SSP_PMC_SET;
|
|
known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
|
|
known_regs.pmc.h = const_val;
|
|
} else {
|
|
known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
|
|
known_regs.pmc.l = const_val;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tr_flush_dirty_ST();
|
|
if (known_regb & KRREG_PMC) {
|
|
emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
|
|
EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
|
|
known_regb &= ~KRREG_PMC;
|
|
dirty_regb &= ~KRREG_PMC;
|
|
}
|
|
EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
|
|
EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
|
|
EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
|
|
EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
|
|
EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
|
|
EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
|
|
EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
|
|
EOP_STR_IMM(1,7,0x484);
|
|
hostreg_r[1] = hostreg_r[2] = -1;
|
|
}
|
|
}
|
|
|
|
typedef void (tr_write_func)(int const_val);
|
|
|
|
static tr_write_func *tr_write_funcs[16] =
|
|
{
|
|
tr_r0_to_GR0,
|
|
tr_r0_to_X,
|
|
tr_r0_to_Y,
|
|
tr_r0_to_A,
|
|
tr_r0_to_ST,
|
|
tr_r0_to_STACK,
|
|
tr_r0_to_PC,
|
|
(tr_write_func *)tr_unhandled,
|
|
tr_r0_to_PM0,
|
|
tr_r0_to_PM1,
|
|
tr_r0_to_PM2,
|
|
(tr_write_func *)tr_unhandled,
|
|
tr_r0_to_PM4,
|
|
(tr_write_func *)tr_unhandled,
|
|
tr_r0_to_PMC,
|
|
tr_r0_to_AL
|
|
};
|
|
|
|
static void tr_mac_load_XY(int op)
|
|
{
|
|
tr_rX_read(op&3, (op>>2)&3); // X
|
|
EOP_MOV_REG_LSL(4, 0, 16);
|
|
tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
|
|
EOP_ORR_REG_SIMPLE(4, 0);
|
|
dirty_regb |= KRREG_P;
|
|
hostreg_sspreg_changed(SSP_X);
|
|
hostreg_sspreg_changed(SSP_Y);
|
|
known_regb &= ~KRREG_X;
|
|
known_regb &= ~KRREG_Y;
|
|
}
|
|
|
|
// -----------------------------------------------------
|
|
|
|
static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
|
|
{
|
|
u32 pmcv, tmpv;
|
|
if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
|
|
|
|
// programming PMC:
|
|
// ldi PMC, imm1
|
|
// ldi PMC, imm2
|
|
(*pc)++;
|
|
pmcv = imm | (PROGRAM((*pc)++) << 16);
|
|
known_regs.pmc.v = pmcv;
|
|
known_regb |= KRREG_PMC;
|
|
dirty_regb |= KRREG_PMC;
|
|
known_regs.emu_status |= SSP_PMC_SET;
|
|
|
|
// check for possible reg programming
|
|
tmpv = PROGRAM(*pc);
|
|
if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
|
|
{
|
|
int is_write = (tmpv & 0xff8f) == 0x80;
|
|
int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
|
|
if (reg > 4) tr_unhandled();
|
|
if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
|
|
known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
|
|
known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
|
|
dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
|
|
known_regs.emu_status &= ~SSP_PMC_SET;
|
|
(*pc)++;
|
|
return 5;
|
|
}
|
|
|
|
tr_unhandled();
|
|
return 4;
|
|
}
|
|
|
|
static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
|
|
|
|
static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
|
|
{
|
|
// ldi ST, 0
|
|
// ldi PM0, 0
|
|
// ldi PM0, 0
|
|
// ldi ST, 60h
|
|
unsigned short *pp;
|
|
if (op != 0x0840 || imm != 0) return 0;
|
|
pp = PROGRAM_P(*pc);
|
|
if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
|
|
|
|
EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
|
|
EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
|
|
hostreg_sspreg_changed(SSP_ST);
|
|
known_regs.gr[SSP_ST].h = 0x60;
|
|
known_regb |= 1 << SSP_ST;
|
|
dirty_regb &= ~KRREG_ST;
|
|
(*pc) += 3*2;
|
|
return 4*2;
|
|
}
|
|
|
|
static int tr_detect_rotate(unsigned int op, int *pc, int imm)
|
|
{
|
|
// @ 3DA2 and 426A
|
|
// ld PMC, (r3|00)
|
|
// ld (r3|00), PMC
|
|
// ld -, AL
|
|
if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
|
|
|
|
tr_bank_read(0);
|
|
EOP_MOV_REG_LSL(0, 0, 4);
|
|
EOP_ORR_REG_LSR(0, 0, 0, 16);
|
|
tr_bank_write(0);
|
|
(*pc) += 2;
|
|
return 3;
|
|
}
|
|
|
|
// -----------------------------------------------------
|
|
|
|
static int translate_op(unsigned int op, int *pc, int imm)
|
|
{
|
|
u32 tmpv, tmpv2, tmpv3;
|
|
int ret = 0;
|
|
known_regs.gr[SSP_PC].h = *pc;
|
|
|
|
switch (op >> 9)
|
|
{
|
|
// ld d, s
|
|
case 0x00:
|
|
if (op == 0) { ret++; break; } // nop
|
|
tmpv = op & 0xf; // src
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
|
|
tr_flush_dirty_P();
|
|
EOP_MOV_REG_SIMPLE(5, 10);
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL);
|
|
ret++; break;
|
|
}
|
|
tr_read_funcs[tmpv](op);
|
|
tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
|
|
if (tmpv2 == SSP_PC) ret |= 0x10000;
|
|
ret++; break;
|
|
|
|
// ld d, (ri)
|
|
case 0x01: {
|
|
int r = (op&3) | ((op>>6)&4);
|
|
int mod = (op>>2)&3;
|
|
tmpv = (op >> 4) & 0xf; // dst
|
|
ret = tr_detect_rotate(op, pc, imm);
|
|
if (ret > 0) break;
|
|
if (tmpv != 0)
|
|
tr_rX_read(r, mod);
|
|
else tr_ptrr_mod(r, mod, 1, 1);
|
|
tr_write_funcs[tmpv](-1);
|
|
if (tmpv == SSP_PC) ret |= 0x10000;
|
|
ret++; break;
|
|
}
|
|
|
|
// ld (ri), s
|
|
case 0x02:
|
|
tmpv = (op >> 4) & 0xf; // src
|
|
tr_read_funcs[tmpv](op);
|
|
tr_rX_write(op);
|
|
ret++; break;
|
|
|
|
// ld a, adr
|
|
case 0x03:
|
|
tr_bank_read(op&0x1ff);
|
|
tr_r0_to_A(-1);
|
|
ret++; break;
|
|
|
|
// ldi d, imm
|
|
case 0x04:
|
|
tmpv = (op & 0xf0) >> 4; // dst
|
|
ret = tr_detect_pm0_block(op, pc, imm);
|
|
if (ret > 0) break;
|
|
ret = tr_detect_set_pm(op, pc, imm);
|
|
if (ret > 0) break;
|
|
tr_mov16(0, imm);
|
|
tr_write_funcs[tmpv](imm);
|
|
if (tmpv == SSP_PC) ret |= 0x10000;
|
|
ret += 2; break;
|
|
|
|
// ld d, ((ri))
|
|
case 0x05:
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
tr_rX_read2(op);
|
|
tr_write_funcs[tmpv2](-1);
|
|
if (tmpv2 == SSP_PC) ret |= 0x10000;
|
|
ret += 3; break;
|
|
|
|
// ldi (ri), imm
|
|
case 0x06:
|
|
tr_mov16(0, imm);
|
|
tr_rX_write(op);
|
|
ret += 2; break;
|
|
|
|
// ld adr, a
|
|
case 0x07:
|
|
tr_A_to_r0(op);
|
|
tr_bank_write(op&0x1ff);
|
|
ret++; break;
|
|
|
|
// ld d, ri
|
|
case 0x09: {
|
|
int r;
|
|
r = (op&3) | ((op>>6)&4); // src
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
if ((r&3) == 3) tr_unhandled();
|
|
|
|
if (known_regb & (1 << (r+8))) {
|
|
tr_mov16(0, known_regs.r[r]);
|
|
tr_write_funcs[tmpv2](known_regs.r[r]);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
|
|
EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
|
|
hostreg_r[0] = -1;
|
|
tr_write_funcs[tmpv2](-1);
|
|
}
|
|
ret++; break;
|
|
}
|
|
|
|
// ld ri, s
|
|
case 0x0a: {
|
|
int r;
|
|
r = (op&3) | ((op>>6)&4); // dst
|
|
tmpv = (op >> 4) & 0xf; // src
|
|
if ((r&3) == 3) tr_unhandled();
|
|
|
|
if (known_regb & (1 << tmpv)) {
|
|
known_regs.r[r] = known_regs.gr[tmpv].h;
|
|
known_regb |= 1 << (r + 8);
|
|
dirty_regb |= 1 << (r + 8);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((4 - (r&3))*8) & 0x1f;
|
|
tr_read_funcs[tmpv](op);
|
|
EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
|
|
EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
|
|
EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
|
|
hostreg_r[0] = -1;
|
|
known_regb &= ~(1 << (r+8));
|
|
dirty_regb &= ~(1 << (r+8));
|
|
}
|
|
ret++; break;
|
|
}
|
|
|
|
// ldi ri, simm
|
|
case 0x0c ... 0x0f:
|
|
tmpv = (op>>8)&7;
|
|
known_regs.r[tmpv] = op;
|
|
known_regb |= 1 << (tmpv + 8);
|
|
dirty_regb |= 1 << (tmpv + 8);
|
|
ret++; break;
|
|
|
|
// call cond, addr
|
|
case 0x24: {
|
|
u32 *jump_op = NULL;
|
|
tmpv = tr_cond_check(op);
|
|
if (tmpv != A_COND_AL) {
|
|
jump_op = tcache_ptr;
|
|
EOP_MOV_IMM(0, 0, 0); // placeholder for branch
|
|
}
|
|
tr_mov16(0, *pc);
|
|
tr_r0_to_STACK(*pc);
|
|
if (tmpv != A_COND_AL) {
|
|
u32 *real_ptr = tcache_ptr;
|
|
tcache_ptr = jump_op;
|
|
EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
|
|
tcache_ptr = real_ptr;
|
|
}
|
|
tr_mov16_cond(tmpv, 0, imm);
|
|
if (tmpv != A_COND_AL) {
|
|
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
|
|
}
|
|
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
|
|
ret |= 0x10000;
|
|
ret += 2; break;
|
|
}
|
|
|
|
// ld d, (a)
|
|
case 0x25:
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
tr_A_to_r0(op);
|
|
EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
|
|
EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
|
|
EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
tr_write_funcs[tmpv2](-1);
|
|
if (tmpv2 == SSP_PC) ret |= 0x10000;
|
|
ret += 3; break;
|
|
|
|
// bra cond, addr
|
|
case 0x26:
|
|
tmpv = tr_cond_check(op);
|
|
tr_mov16_cond(tmpv, 0, imm);
|
|
if (tmpv != A_COND_AL) {
|
|
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
|
|
}
|
|
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
|
|
ret |= 0x10000;
|
|
ret += 2; break;
|
|
|
|
// mod cond, op
|
|
case 0x48: {
|
|
// check for repeats of this op
|
|
tmpv = 1; // count
|
|
while (PROGRAM(*pc) == op && (op & 7) != 6) {
|
|
(*pc)++; tmpv++;
|
|
}
|
|
if ((op&0xf0) != 0) // !always
|
|
tr_make_dirty_ST();
|
|
|
|
tmpv2 = tr_cond_check(op);
|
|
switch (op & 7) {
|
|
case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
|
|
case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
|
|
case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
|
|
case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
|
|
EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
|
|
hostreg_r[1] = -1; break; // abs
|
|
default: tr_unhandled();
|
|
}
|
|
|
|
hostreg_sspreg_changed(SSP_A);
|
|
dirty_regb |= KRREG_ST;
|
|
known_regb &= ~KRREG_ST;
|
|
known_regb &= ~(KRREG_A|KRREG_AL);
|
|
ret += tmpv; break;
|
|
}
|
|
|
|
// mpys?
|
|
case 0x1b:
|
|
tr_flush_dirty_P();
|
|
tr_mac_load_XY(op);
|
|
tr_make_dirty_ST();
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
|
|
// mpya (rj), (ri), b
|
|
case 0x4b:
|
|
tr_flush_dirty_P();
|
|
tr_mac_load_XY(op);
|
|
tr_make_dirty_ST();
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
|
|
// mld (rj), (ri), b
|
|
case 0x5b:
|
|
EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regs.gr[SSP_A].v = 0;
|
|
known_regb |= (KRREG_A|KRREG_AL);
|
|
dirty_regb |= KRREG_ST;
|
|
tr_mac_load_XY(op);
|
|
ret++; break;
|
|
|
|
// OP a, s
|
|
case 0x10:
|
|
case 0x30:
|
|
case 0x40:
|
|
case 0x50:
|
|
case 0x60:
|
|
case 0x70:
|
|
tmpv = op & 0xf; // src
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
if (tmpv == SSP_P) {
|
|
tr_flush_dirty_P();
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
|
|
} else if (tmpv == SSP_A) {
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
|
|
} else {
|
|
tr_read_funcs[tmpv](op);
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
|
|
}
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
|
|
// OP a, (ri)
|
|
case 0x11:
|
|
case 0x31:
|
|
case 0x41:
|
|
case 0x51:
|
|
case 0x61:
|
|
case 0x71:
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
|
|
// OP a, adr
|
|
case 0x13:
|
|
case 0x33:
|
|
case 0x43:
|
|
case 0x53:
|
|
case 0x63:
|
|
case 0x73:
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
tr_bank_read(op&0x1ff);
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
|
|
// OP a, imm
|
|
case 0x14:
|
|
case 0x34:
|
|
case 0x44:
|
|
case 0x54:
|
|
case 0x64:
|
|
case 0x74:
|
|
tmpv = (op & 0xf0) >> 4;
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
tr_mov16(0, imm);
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret += 2; break;
|
|
|
|
// OP a, ((ri))
|
|
case 0x15:
|
|
case 0x35:
|
|
case 0x45:
|
|
case 0x55:
|
|
case 0x65:
|
|
case 0x75:
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
tr_rX_read2(op);
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret += 3; break;
|
|
|
|
// OP a, ri
|
|
case 0x19:
|
|
case 0x39:
|
|
case 0x49:
|
|
case 0x59:
|
|
case 0x69:
|
|
case 0x79: {
|
|
int r;
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
r = (op&3) | ((op>>6)&4); // src
|
|
if ((r&3) == 3) tr_unhandled();
|
|
|
|
if (known_regb & (1 << (r+8))) {
|
|
EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
|
|
EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
|
|
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
|
hostreg_r[0] = -1;
|
|
}
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
}
|
|
|
|
// OP simm
|
|
case 0x1c:
|
|
case 0x3c:
|
|
case 0x4c:
|
|
case 0x5c:
|
|
case 0x6c:
|
|
case 0x7c:
|
|
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
|
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
|
EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
|
|
hostreg_sspreg_changed(SSP_A);
|
|
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
|
dirty_regb |= KRREG_ST;
|
|
ret++; break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void *translate_block(int pc)
|
|
{
|
|
unsigned int op, op1, imm, ccount = 0;
|
|
unsigned int *block_start;
|
|
int ret, ret_prev = -1, tpc;
|
|
|
|
printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
|
|
block_start = tcache_ptr;
|
|
known_regb = 0;
|
|
dirty_regb = KRREG_P;
|
|
known_regs.emu_status = 0;
|
|
hostreg_clear();
|
|
|
|
emit_block_prologue();
|
|
|
|
for (; ccount < 100;)
|
|
{
|
|
op = PROGRAM(pc++);
|
|
op1 = op >> 9;
|
|
imm = (u32)-1;
|
|
|
|
if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
|
|
imm = PROGRAM(pc++); // immediate
|
|
tpc = pc;
|
|
|
|
ret = translate_op(op, &pc, imm);
|
|
if (ret <= 0)
|
|
{
|
|
tr_flush_dirty_prs();
|
|
tr_flush_dirty_ST();
|
|
tr_flush_dirty_pmcrs();
|
|
known_regs.emu_status = 0;
|
|
|
|
emit_mov_const(A_COND_AL, 0, op);
|
|
|
|
// need immediate?
|
|
if (imm != (u32)-1)
|
|
emit_mov_const(A_COND_AL, 1, imm);
|
|
|
|
// dump PC
|
|
emit_pc_dump(pc);
|
|
|
|
if (ret_prev > 0) emit_call(regfile_store);
|
|
emit_call(in_funcs[op1]);
|
|
emit_call(regfile_load);
|
|
|
|
if (in_funcs[op1] == NULL) {
|
|
printf("NULL func! op=%08x (%02x)\n", op, op1);
|
|
exit(1);
|
|
}
|
|
ccount++;
|
|
hostreg_clear();
|
|
dirty_regb |= KRREG_P;
|
|
known_regb = 0;
|
|
}
|
|
else
|
|
{
|
|
ccount += ret & 0xffff;
|
|
if (ret & 0x10000) break;
|
|
}
|
|
|
|
ret_prev = ret;
|
|
}
|
|
|
|
if (ccount >= 100)
|
|
emit_pc_dump(pc);
|
|
|
|
tr_flush_dirty_prs();
|
|
tr_flush_dirty_ST();
|
|
tr_flush_dirty_pmcrs();
|
|
emit_block_epilogue(ccount + 1);
|
|
*tcache_ptr++ = 0xffffffff; // end of block
|
|
|
|
if (tcache_ptr - tcache > TCACHE_SIZE/4) {
|
|
printf("tcache overflow!\n");
|
|
fflush(stdout);
|
|
exit(1);
|
|
}
|
|
|
|
// stats
|
|
nblocks++;
|
|
printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
|
|
|
|
#ifdef DUMP_BLOCK
|
|
{
|
|
FILE *f = fopen("tcache.bin", "wb");
|
|
fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
|
|
fclose(f);
|
|
}
|
|
exit(0);
|
|
#endif
|
|
|
|
handle_caches();
|
|
|
|
return block_start;
|
|
}
|
|
|
|
|
|
|
|
// -----------------------------------------------------
|
|
|
|
int ssp1601_dyn_startup(void)
|
|
{
|
|
memset(tcache, 0, TCACHE_SIZE);
|
|
memset(block_table, 0, sizeof(block_table));
|
|
memset(block_table_iram, 0, sizeof(block_table_iram));
|
|
tcache_ptr = tcache;
|
|
*tcache_ptr++ = 0xffffffff;
|
|
|
|
#ifdef ARM
|
|
// hle'd blocks
|
|
block_table[0x400] = (void *) ssp_hle_800;
|
|
#endif
|
|
|
|
// TODO: rm
|
|
{
|
|
static unsigned short dummy = 0;
|
|
PC = &dummy;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
void ssp1601_dyn_reset(ssp1601_t *ssp)
|
|
{
|
|
ssp1601_reset_local(ssp);
|
|
ssp->drc.ptr_rom = (unsigned int) Pico.rom;
|
|
ssp->drc.ptr_iram_rom = (unsigned int) svp->iram_rom;
|
|
ssp->drc.ptr_dram = (unsigned int) svp->dram;
|
|
ssp->drc.iram_dirty = 0;
|
|
}
|
|
|
|
void ssp1601_dyn_run(int cycles)
|
|
{
|
|
if (ssp->emu_status & SSP_WAIT_MASK) return;
|
|
|
|
#ifdef DUMP_BLOCK
|
|
rPC = DUMP_BLOCK >> 1;
|
|
#endif
|
|
while (cycles > 0)
|
|
{
|
|
int (*trans_entry)(void);
|
|
if (rPC < 0x800/2)
|
|
{
|
|
if (ssp->drc.iram_dirty) {
|
|
iram_context = get_iram_context();
|
|
ssp->drc.iram_dirty--;
|
|
}
|
|
if (block_table_iram[iram_context][rPC] == NULL)
|
|
block_table_iram[iram_context][rPC] = translate_block(rPC);
|
|
trans_entry = (void *) block_table_iram[iram_context][rPC];
|
|
}
|
|
else
|
|
{
|
|
if (block_table[rPC] == NULL)
|
|
block_table[rPC] = translate_block(rPC);
|
|
trans_entry = (void *) block_table[rPC];
|
|
}
|
|
|
|
cycles -= trans_entry();
|
|
}
|
|
}
|
|
|