mirror of
https://github.com/RaySollium99/picodrive.git
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327 lines
8.3 KiB
ArmAsm
327 lines
8.3 KiB
ArmAsm
/*
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* PicoDrive
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* (C) notaz, 2006-2009
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* (C) kub, 2019
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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#include "arm_features.h"
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#include "pico_int_offs.h"
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.equ SRR_MAPPED, (1 << 0)
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.equ SRR_READONLY, (1 << 1)
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.equ SRF_EEPROM, (1 << 1)
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.equ POPT_EN_32X, (1 << 20)
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.text
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.align 4
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.global PicoRead8_sram
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.global PicoRead8_io
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.global PicoRead16_sram
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.global PicoRead16_io
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.global PicoWrite8_io
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.global PicoWrite16_io
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PIC_LDR_INIT()
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PicoRead8_sram: @ u32 a
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PIC_LDR(r3, r1, Pico)
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ldr r1, [r3, #OFS_Pico_sv_end]
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cmp r0, r1
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bgt m_read8_nosram
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ldr r2, [r3, #OFS_Pico_sv_start]
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cmp r0, r2
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blt m_read8_nosram
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ldrb r1, [r3, #OFS_Pico_m_sram_reg]
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tst r1, #SRR_MAPPED
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beq m_read8_nosram
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ldr r1, [r3, #OFS_Pico_sv_flags]
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tst r1, #SRF_EEPROM
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bne m_read8_eeprom
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ldr r1, [r3, #OFS_Pico_sv_data]
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sub r0, r0, r2
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ldrb r0, [r0, r1]
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bx lr
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m_read8_nosram:
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ldr r1, [r3, #OFS_Pico_romsize]
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cmp r0, r1
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movgt r0, #0
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bxgt lr @ bad location
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@ XXX: banking unfriendly
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ldr r1, [r3, #OFS_Pico_rom]
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eor r0, r0, #1
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ldrb r0, [r1, r0]
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bx lr
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m_read8_eeprom:
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stmfd sp!,{r0,lr}
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bl EEPROM_read
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ldmfd sp!,{r1,lr}
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tst r1, #1
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moveq r0, r0, lsr #8
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and r0, r0, #0xff
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bx lr
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PicoRead8_io: @ u32 a
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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beq io_ports_read
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m_read8_not_io:
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and r2, r0, #0xfc00
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cmp r2, #0x1000
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bne PicoRead8_32x
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PIC_LDR(r3, r1, Pico)
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mov r1, r0
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ldr r0, [r3, #OFS_Pico_m_rotate]
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add r0, r0, #1
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strb r0, [r3, #OFS_Pico_m_rotate]
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eor r0, r0, r0, lsl #6
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tst r1, #1
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bxne lr @ odd addr -> open bus
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bic r0, r0, #1 @ bit0 defined in this area
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and r2, r1, #0xff00
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cmp r2, #0x1100
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bxne lr @ not busreq
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ldrb r1, [r3, #OFS_Pico_m_z80Run]
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ldrb r2, [r3, #OFS_Pico_m_z80_reset]
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orr r0, r0, r1
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orr r0, r0, r2
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoRead16_sram: @ u32 a, u32 d
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PIC_LDR(r3, r1, Pico)
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ldr r1, [r3, #OFS_Pico_sv_end]
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cmp r0, r1
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bgt m_read16_nosram
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ldr r2, [r3, #OFS_Pico_sv_start]
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cmp r0, r2
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blt m_read16_nosram
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ldrb r1, [r3, #OFS_Pico_m_sram_reg]
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tst r1, #SRR_MAPPED
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beq m_read16_nosram
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ldr r1, [r3, #OFS_Pico_sv_flags]
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tst r1, #SRF_EEPROM
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bne EEPROM_read
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ldr r1, [r3, #OFS_Pico_sv_data]
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sub r0, r0, r2
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ldrb r1, [r0, r1]!
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ldrb r0, [r0, #1]
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orr r0, r0, r1, lsl #8
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bx lr
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m_read16_nosram:
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ldr r1, [r3, #OFS_Pico_romsize]
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cmp r0, r1
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movgt r0, #0
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bxgt lr @ bad location
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@ XXX: banking unfriendly
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ldr r1, [r3, #OFS_Pico_rom]
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ldrh r0, [r1, r0]
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bx lr
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PicoRead16_io: @ u32 a, u32 d
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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bne m_read16_not_io
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stmfd sp!,{lr}
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bl io_ports_read @ same as read8
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orr r0, r0, r0, lsl #8 @ only has bytes mirrored
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ldmfd sp!,{pc}
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m_read16_not_io:
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and r2, r0, #0xfc00
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cmp r2, #0x1000
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bne PicoRead16_32x
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PIC_LDR(r3, r2, Pico)
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and r2, r0, #0xff00
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ldr r0, [r3, #OFS_Pico_m_rotate]
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add r0, r0, #1
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strb r0, [r3, #OFS_Pico_m_rotate]
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eor r0, r0, r0, lsl #5
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eor r0, r0, r0, lsl #8
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bic r0, r0, #0x100 @ bit8 defined in this area
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cmp r2, #0x1100
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bxne lr @ not busreq
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ldrb r1, [r3, #OFS_Pico_m_z80Run]
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ldrb r2, [r3, #OFS_Pico_m_z80_reset]
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orr r0, r0, r1, lsl #8
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orr r0, r0, r2, lsl #8
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoWrite8_io: @ u32 a, u32 d
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bic r2, r0, #0x1e @ most commonly we get i/o port write,
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eor r2, r2, #0xa10000 @ so check for it first
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eors r2, r2, #1
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beq io_ports_write
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m_write8_not_io:
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tst r0, #1
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bne m_write8_not_z80ctl @ even addrs only
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and r2, r0, #0xff00
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cmp r2, #0x1100
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moveq r0, r1
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beq ctl_write_z80busreq
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cmp r2, #0x1200
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moveq r0, r1
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beq ctl_write_z80reset
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m_write8_not_z80ctl:
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@ unlikely
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eor r2, r0, #0xa10000
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eor r2, r2, #0x003000
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eors r2, r2, #0x0000f1
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bne PicoWrite8_32x
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PIC_LDR(r3, r2, Pico)
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ldrb r2, [r3, #OFS_Pico_m_sram_reg]
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and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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orr r2, r2, r1
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strb r2, [r3, #OFS_Pico_m_sram_reg]
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoWrite16_io: @ u32 a, u32 d
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bic r2, r0, #0x1f @ most commonly we get i/o port write,
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cmp r2, #0xa10000 @ so check for it first
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beq io_ports_write
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m_write16_not_io:
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and r2, r0, #0xff00
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cmp r2, #0x1100
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moveq r0, r1, lsr #8
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beq ctl_write_z80busreq
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cmp r2, #0x1200
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moveq r0, r1, lsr #8
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beq ctl_write_z80reset
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m_write16_not_z80ctl:
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@ unlikely
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eor r2, r0, #0xa10000
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eor r2, r2, #0x003000
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eors r2, r2, #0x0000f0
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bne PicoWrite16_32x
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PIC_LDR(r3, r2, Pico)
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ldrb r2, [r3, #OFS_Pico_m_sram_reg]
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and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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orr r2, r2, r1
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strb r2, [r3, #OFS_Pico_m_sram_reg]
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bx lr
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.global m68k_read8
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.global m68k_read16
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.global m68k_read32
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.global m68k_write8
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.global m68k_write16
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.global m68k_write32
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m68k_read8:
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PIC_LDR(r3, r2, m68k_read8_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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eor r2, r0, #1
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movs r3, r3, lsl #1
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ldrccb r0, [r3, r2]
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bxcc lr
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bx r3
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m68k_read16:
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PIC_LDR(r3, r2, m68k_read16_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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bic r0, r0, #1
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movs r3, r3, lsl #1
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ldrcch r0, [r3, r0]
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bxcc lr
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bx r3
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m68k_read32:
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PIC_LDR(r3, r2, m68k_read16_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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bic r0, r0, #1
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movs r3, r3, lsl #1
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ldrcch r1, [r3, r0]!
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ldrcch r0, [r3, #2]
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orrcc r0, r0, r1, lsl #16
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bxcc lr
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stmfd sp!, {r0, r3, r4, lr}
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mov lr, pc
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bx r3
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ldmfd sp!, {r1, r3}
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str r0, [sp]
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add r0, r1, #2
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mov lr, pc
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bx r3
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ldmfd sp!, {r1, lr}
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mov r0, r0, lsl #16
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mov r1, r1, lsl #16
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orr r0, r1, r0, lsr #16
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bx lr
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m68k_write8:
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PIC_LDR(r3, r2, m68k_write8_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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eor r2, r0, #1
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movs r3, r3, lsl #1
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strccb r1, [r3, r2]
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bxcc lr
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bx r3
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m68k_write16:
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PIC_LDR(r3, r2, m68k_write16_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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bic r0, r0, #1
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movs r3, r3, lsl #1
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strcch r1, [r3, r0]
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bxcc lr
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bx r3
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m68k_write32:
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PIC_LDR(r3, r2, m68k_write16_map)
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bic r0, r0, #0xff000000
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mov r2, r0, lsr #16
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ldr r3, [r3, r2, lsl #2]
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bic r0, r0, #1
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movs r3, r3, lsl #1
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movcc r2, r1, lsr #16
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strcch r2, [r3, r0]!
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strcch r1, [r3, #2]
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bxcc lr
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stmfd sp!, {r0, r1, r3, lr}
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mov r1, r1, lsr #16
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mov lr, pc
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bx r3
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ldmfd sp!, {r0, r1, r3, lr}
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add r0, r0, #2
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bx r3
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.pool
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@ vim:filetype=armasm
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