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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@242 be3aeb3a-fb24-0410-a615-afba39da0efa
171 lines
6.7 KiB
C
171 lines
6.7 KiB
C
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/**
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* Cyclone 68000 configuration file
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**/
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/*
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* If this option is enabled, Microsoft ARMASM compatible output is generated
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* (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).
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*/
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#define USE_MS_SYNTAX 0
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/*
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* Enable this option if you are going to use Cyclone to emulate Genesis /
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* Mega Drive system. As VDP chip in these systems had control of the bus,
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* several instructions were acting differently, for example TAS did'n have
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* the write-back phase. That will be emulated, if this option is enabled.
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*/
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#define CYCLONE_FOR_GENESIS 0
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/*
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* This option compresses Cyclone's jumptable. Because of this the executable
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* will be smaller and load slightly faster and less relocations will be needed.
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* This also fixes the crash problem with 0xfffe and 0xffff opcodes.
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* Warning: if you enable this, you MUST call CycloneInit() before calling
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* CycloneRun(), or else it will crash.
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*/
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#define COMPRESS_JUMPTABLE 1
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/*
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* Address mask for memory hadlers. The bits set will be masked out of address
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* parameter, which is passed to r/w memory handlers.
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* Using 0xff000000 means that only 24 least significant bits should be used.
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* Set to 0 if you want to mask unused address bits in the memory handlers yourself.
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*/
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#define MEMHANDLERS_ADDR_MASK 0
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/*
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* Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle
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* counter in ARM registers instead of the context for performance reasons. If you for
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* any reason need to access them in your memory handlers, enable the options below,
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* otherwise disable them to improve performance.
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*
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* MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time
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* when memhandler was called (opcode address + 2-10 bytes).
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* MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed
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* opcode address + 2.
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* Note that .pc and .prev_pc values are always real pointers to memory, so you must
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* subtract .membase to get M68k PC value.
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*
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* Warning: updating PC in memhandlers is dangerous, as Cyclone may internally
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* increment the PC before fetching the next instruction and continue executing
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* at wrong location. It's better to wait until Cyclone CycloneRun() finishes.
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*
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* Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable
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* MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle
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* count and this will screw timing (if not cause a deadlock).
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*/
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#define MEMHANDLERS_NEED_PC 0
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#define MEMHANDLERS_NEED_PREV_PC 0
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#define MEMHANDLERS_NEED_FLAGS 0
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#define MEMHANDLERS_NEED_CYCLES 0
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#define MEMHANDLERS_CHANGE_PC 0
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#define MEMHANDLERS_CHANGE_FLAGS 0
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#define MEMHANDLERS_CHANGE_CYCLES 0
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/*
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* If enabled, Cyclone will call .IrqCallback routine from it's context whenever it
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* acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your
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* handler if needed.
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* This function must either return vector number to use for interrupt exception,
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* CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or
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* CYCLONE_INT_ACK_SPURIOUS (least common case).
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* If disabled, it simply uses appropriate autovector, clears the IRQ level and
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* continues execution.
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*/
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#define USE_INT_ACK_CALLBACK 0
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/*
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* Enable this if you need old PC, flags or cycles;
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* or you change cycles in your IrqCallback function.
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*/
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#define INT_ACK_NEEDS_STUFF 0
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#define INT_ACK_CHANGES_CYCLES 0
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/*
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* If enabled, .ResetCallback is called from the context, whenever RESET opcode is
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* encountered. All context members are valid and can be changed.
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* If disabled, RESET opcode acts as an NOP.
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*/
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#define USE_RESET_CALLBACK 0
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/*
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* If enabled, UnrecognizedCallback is called if an invalid opcode is
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* encountered. All context members are valid and can be changed. The handler
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* should return zero if you want Cyclone to gererate "Illegal Instruction"
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* exception after this, or nonzero if not. In the later case you should change
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* the PC by yourself, or else Cyclone will keep executing that opcode all over
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* again.
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* If disabled, "Illegal Instruction" exception is generated and execution is
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* continued.
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*/
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#define USE_UNRECOGNIZED_CALLBACK 0
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/*
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* This option will also call UnrecognizedCallback for a-line and f-line
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* (0xa*** and 0xf***) opcodes the same way as described above, only appropriate
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* exceptions will be generated.
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*/
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#define USE_AFLINE_CALLBACK 0
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/*
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* This makes Cyclone to call checkpc from it's context whenever it changes the PC
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* by a large value. It takes and should return the PC value in PC+membase form.
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* The flags and cycle counter are not valid in this function.
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*/
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#define USE_CHECKPC_CALLBACK 1
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/*
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* This determines if checkpc() should be called after jumps when 8 and 16 bit
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* displacement values were used.
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*/
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#define USE_CHECKPC_OFFSETBITS_16 1
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#define USE_CHECKPC_OFFSETBITS_8 0
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/*
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* Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to
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* 0.0087 never did that.
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*/
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#define USE_CHECKPC_DBRA 0
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/*
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* When this option is enabled Cyclone will do two word writes instead of one
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* long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,
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* as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).
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* Enable this if you are emulating a 16 bit system.
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*/
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#define SPLIT_MOVEL_PD 1
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/*
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* Enable emulation of trace mode. Shouldn't cause any performance decrease, so it
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* should be safe to keep this ON.
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*/
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#define EMULATE_TRACE 1
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/*
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* If enabled, address error exception will be generated if 68k code jumps to an
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* odd address. Causes very small performance hit (2 ARM instructions for every
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* emulated jump/return/exception in normal case).
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* Note: checkpc() must not clear least significant bit of rebased address
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* for this to work, as checks are performed after calling checkpc().
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*/
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#define EMULATE_ADDRESS_ERRORS_JUMP 1
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/*
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* If enabled, address error exception will be generated if 68k code tries to
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* access a word or longword at an odd address. The performance cost is also 2 ARM
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* instructions per access (for address error checks).
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*/
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#define EMULATE_ADDRESS_ERRORS_IO 0
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/*
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* If an address error happens during another address error processing,
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* the processor halts until it is reset (catastrophic system failure, as the manual
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* states). This option enables halt emulation.
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* Note that this might be not desired if it is known that emulated system should
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* never reach this state.
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*/
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#define EMULATE_HALT 0
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