mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
547045e3c6
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@189 be3aeb3a-fb24-0410-a615-afba39da0efa
489 lines
11 KiB
C++
489 lines
11 KiB
C++
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#include "app.h"
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static void CheckPc(int reg)
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{
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#if USE_CHECKPC_CALLBACK
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ot(";@ Check Memory Base+pc (r4)\n");
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if (reg != 0)
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ot(" mov r0,r%i\n", reg);
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ot(" mov lr,pc\n");
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ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
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ot(" mov r4,r0\n");
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#else
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ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors
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#endif
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ot("\n");
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}
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// Push 32-bit value in r1 - trashes r0-r3,r12,lr
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void OpPush32()
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{
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ot(";@ Push r1 onto stack\n");
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ot(" ldr r0,[r7,#0x3c]\n");
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ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
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ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(1,2);
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ot("\n");
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}
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// Push SR - trashes r0-r3,r12,lr
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void OpPushSr(int high)
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{
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ot(";@ Push SR:\n");
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OpFlagsToReg(high);
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ot(" ldr r0,[r7,#0x3c]\n");
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ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
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ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(1,1);
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ot("\n");
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}
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// Pop SR - trashes r0-r3
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static void PopSr(int high)
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{
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ot(";@ Pop SR:\n");
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ot(" ldr r0,[r7,#0x3c]\n");
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ot(" add r1,r0,#2 ;@ Postincrement A7\n");
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ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(0,1);
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ot("\n");
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OpRegToFlags(high);
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}
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// Pop PC - assumes r10=Memory Base - trashes r0-r3
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static void PopPc()
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{
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ot(";@ Pop PC:\n");
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ot(" ldr r0,[r7,#0x3c]\n");
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ot(" add r1,r0,#4 ;@ Postincrement A7\n");
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ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(0,2);
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ot(" add r0,r0,r10 ;@ Memory Base+PC\n");
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ot("\n");
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CheckPc(0);
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}
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int OpTrap(int op)
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{
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int use=0;
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use=op&~0xf;
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,0x10);
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ot(" and r0,r8,#0xf ;@ Get trap number\n");
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ot(" orr r0,r0,#0x20\n");
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ot(" mov r0,r0,asl #2\n");
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ot(" bl Exception\n");
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ot("\n");
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Cycles=38; OpEnd(0x10);
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return 0;
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}
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// --------------------- Opcodes 0x4e50+ ---------------------
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int OpLink(int op)
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{
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int use=0,reg;
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use=op&~7;
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reg=op&7;
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if (reg==7) use=op;
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,0x10);
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if(reg!=7) {
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ot(";@ Get An\n");
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EaCalc(10, 7, 8, 2, 1);
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EaRead(10, 1, 8, 2, 7, 1);
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}
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ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
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ot(" sub r0,r0,#4 ;@ A7-=4\n");
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ot(" mov r11,r0\n");
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if(reg==7) ot(" mov r1,r0\n");
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ot("\n");
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ot(";@ Write An to Stack\n");
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MemHandler(1,2);
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ot(";@ Save to An\n");
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if(reg!=7)
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EaWrite(10,11, 8, 2, 7, 1);
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ot(";@ Get offset:\n");
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EaCalc(0,0,0x3c,1);
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EaRead(0,0,0x3c,1,0);
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ot(" add r11,r11,r0 ;@ Add offset to A7\n");
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ot(" str r11,[r7,#0x3c]\n");
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ot("\n");
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Cycles=16;
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OpEnd(0x10);
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return 0;
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}
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// --------------------- Opcodes 0x4e58+ ---------------------
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int OpUnlk(int op)
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{
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int use=0;
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use=op&~7;
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,0x10);
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ot(";@ Get An\n");
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EaCalc(10, 0xf, 8, 2, 1);
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EaRead(10, 0, 8, 2, 0xf, 1);
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ot(" add r11,r0,#4 ;@ A7+=4\n");
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ot("\n");
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ot(";@ Pop An from stack:\n");
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MemHandler(0,2);
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ot("\n");
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ot(" str r11,[r7,#0x3c] ;@ Save A7\n");
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ot("\n");
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ot(";@ An = value from stack:\n");
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EaWrite(10, 0, 8, 2, 7, 1);
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Cycles=12;
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OpEnd(0x10);
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return 0;
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}
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// --------------------- Opcodes 0x4e70+ ---------------------
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// 01001110 01110ttt
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int Op4E70(int op)
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{
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int type=0;
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type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr
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switch (type)
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{
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case 1: // nop
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OpStart(op);
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Cycles=4;
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OpEnd();
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return 0;
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case 3: // rte
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OpStart(op,0x10); Cycles=20;
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SuperCheck(op);
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PopSr(1);
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ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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PopPc();
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SuperChange(op);
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CheckInterrupt(op);
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OpEnd(0x10);
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return 0;
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case 5: // rts
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OpStart(op,0x10); Cycles=16;
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ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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PopPc();
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OpEnd(0x10);
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return 0;
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case 6: // trapv
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OpStart(op,0x10); Cycles=4;
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ot(" tst r9,#0x10000000\n");
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ot(" subne r5,r5,#%i\n",34);
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ot(" movne r0,#0x1c ;@ TRAPV exception\n");
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ot(" blne Exception\n");
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OpEnd(0x10);
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return 0;
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case 7: // rtr
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OpStart(op,0x10); Cycles=20;
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PopSr(0);
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ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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PopPc();
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OpEnd(0x10);
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return 0;
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default:
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return 1;
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}
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}
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// --------------------- Opcodes 0x4e80+ ---------------------
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// Emit a Jsr/Jmp opcode, 01001110 1meeeeee
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int OpJsr(int op)
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{
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int use=0;
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int sea=0;
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sea=op&0x003f;
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// See if we can do this opcode:
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if (EaCanRead(sea,-1)==0) return 1;
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use=OpBase(op,0);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,(op&0x40)?0:0x10);
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ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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ot("\n");
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EaCalc(11,0x003f,sea,0);
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ot(";@ Jump - Get new PC from r0\n");
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if (op&0x40)
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{
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// Jmp - Get new PC from r11
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ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");
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ot("\n");
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}
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else
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{
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ot(";@ Jsr - Push old PC first\n");
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ot(" ldr r0,[r7,#0x3c]\n");
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ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
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// ot(" mov r1,r1,lsl #8\n");
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// ot(" mov r1,r1,asr #8\n");
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ot(";@ Push r1 onto stack\n");
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ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
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ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(1,2);
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ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");
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ot("\n");
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}
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CheckPc(0);
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Cycles=(op&0x40) ? 4 : 12;
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Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);
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OpEnd((op&0x40)?0:0x10);
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return 0;
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}
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// --------------------- Opcodes 0x50c8+ ---------------------
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// ARM version of 68000 condition codes:
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static char *Cond[16]=
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{
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"", "", "hi","ls","cc","cs","ne","eq",
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"vc","vs","pl","mi","ge","lt","gt","le"
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};
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// Emit a Dbra opcode, 0101cccc 11001nnn vv
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int OpDbra(int op)
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{
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int use=0;
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int cc=0;
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use=op&~7; // Use same handler
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cc=(op>>8)&15;
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op);
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switch (cc)
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{
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case 0: // T
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case 1: // F
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break;
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case 2: // hi
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ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
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ot(" beq DbraTrue\n\n");
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break;
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case 3: // ls
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ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
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ot(" bne DbraTrue\n\n");
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break;
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default:
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ot(";@ Is the condition true?\n");
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ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
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ot(";@ If so, don't dbra\n");
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ot(" b%s DbraTrue\n\n",Cond[cc]);
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break;
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}
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if (cc!=0)
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{
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ot(";@ Decrement Dn.w\n");
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ot(" and r1,r8,#0x0007\n");
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ot(" mov r1,r1,lsl #2\n");
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ot(" ldrsh r0,[r7,r1]\n");
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ot(" sub r0,r0,#1\n");
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ot(" strh r0,[r7,r1]\n");
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ot("\n");
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ot(";@ Check if Dn.w is -1\n");
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ot(" cmn r0,#1\n");
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#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
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ot(" beq DbraMin1\n");
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ot("\n");
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ot(";@ Get Branch offset:\n");
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ot(" ldrsh r0,[r4]\n");
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ot(" add r0,r4,r0 ;@ r4 = New PC\n");
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CheckPc(0);
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#else
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ot("\n");
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ot(";@ Get Branch offset:\n");
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ot(" ldrnesh r0,[r4]\n");
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ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");
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ot(" subeq r5,r5,#4 ;@ additional cycles\n");
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ot(" addne r4,r4,r0 ;@ r4 = New PC\n");
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ot(" bic r4,r4,#1\n"); // we do not emulate address errors
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ot("\n");
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#endif
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Cycles=12-2;
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OpEnd();
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}
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//if (cc==0||cc>=2)
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if (op==0x50c8)
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{
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ot(";@ condition true:\n");
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ot("DbraTrue%s\n", ms?"":":");
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ot(" add r4,r4,#2 ;@ Skip branch offset\n");
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ot("\n");
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Cycles=12;
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OpEnd();
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}
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#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
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if (op==0x51c8)
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{
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ot(";@ Dn.w is -1:\n");
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ot("DbraMin1%s\n", ms?"":":");
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ot(" add r4,r4,#2 ;@ Skip branch offset\n");
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ot("\n");
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Cycles=12+2;
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OpEnd();
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}
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#endif
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return 0;
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}
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// --------------------- Opcodes 0x6000+ ---------------------
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// Emit a Branch opcode 0110cccc nn (cccc=condition)
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int OpBranch(int op)
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{
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int size=0,use=0,checkpc=0;
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int offset=0;
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int cc=0;
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char *asr_r11="";
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offset=(char)(op&0xff);
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cc=(op>>8)&15;
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// Special offsets:
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if (offset==0) size=1;
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if (offset==-1) size=2;
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if (size==2) size=0; // 000 model does not support long displacement
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if (size) use=op; // 16-bit or 32-bit
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else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,size?0x10:0);
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Cycles=10; // Assume branch taken
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if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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switch (cc)
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{
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case 0: // T
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case 1: // F
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break;
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case 2: // hi
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ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
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ot(" bne BccDontBranch%i\n\n",8<<size);
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break;
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case 3: // ls
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ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
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ot(" beq BccDontBranch%i\n\n",8<<size);
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break;
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default:
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ot(";@ Is the condition true?\n");
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ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
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ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);
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break;
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}
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if (size)
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{
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if (size<2)
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{
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ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");
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}
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else
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{
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ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");
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ot(" ldrh r11,[r4,#2]\n");
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ot(" orr r11,r11,r2,lsl #16\n");
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}
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}
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else
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{
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ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
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asr_r11=",asr #24";
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}
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ot(";@ Branch taken - Add on r0 to PC\n");
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if (cc==1)
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{
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ot(";@ Bsr - remember old PC\n");
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ot(" ldr r2,[r7,#0x3c]\n");
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ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
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if (size) ot(" add r1,r1,#%d\n",1<<size);
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// ot(" mov r1,r1, lsl #8\n");
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// ot(" mov r1,r1, asr #8\n");
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ot("\n");
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ot(";@ Push r1 onto stack\n");
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ot(" sub r0,r2,#4 ;@ Predecrement A7\n");
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ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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MemHandler(1,2);
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ot("\n");
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Cycles=18; // always 18
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}
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ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
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#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
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if (offset!=0 && offset!=-1) checkpc=1;
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#endif
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#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16
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if (offset==0) checkpc=1;
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#endif
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#if USE_CHECKPC_CALLBACK
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if (offset==-1) checkpc=1;
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#endif
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if (checkpc)
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{
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CheckPc(0);
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}
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else
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{
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ot(" bic r4,r0,#1\n"); // we do not emulate address errors
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ot("\n");
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}
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OpEnd(size?0x10:0);
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// since all "DontBranch" code is same for every size, output only once
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if (cc>=2&&(op&0xff00)==0x6200)
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{
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ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");
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if (size) ot(" add r4,r4,#%d\n",1<<size);
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Cycles+=(size==1) ? 2 : -2; // Branch not taken
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OpEnd(0);
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}
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return 0;
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}
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