mirror of
https://github.com/RaySollium99/picodrive.git
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144 lines
4.1 KiB
C
144 lines
4.1 KiB
C
#ifndef __SH2_H__
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#define __SH2_H__
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#include "../../pico/pico_port.h"
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// registers - matches structure order
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typedef enum {
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SHR_R0 = 0, SHR_SP = 15,
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SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
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SH2_REGS // register set size
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} sh2_reg_e;
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#define SHR_R(n) (SHR_R0+(n))
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typedef struct SH2_
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{
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// registers. this MUST correlate with enum sh2_reg_e.
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uint32_t r[16] ALIGNED(32);
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uint32_t pc; // 40
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uint32_t ppc;
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uint32_t pr;
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uint32_t sr;
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uint32_t gbr, vbr; // 50
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uint32_t mach, macl; // 58
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// common
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const void *read8_map;
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const void *read16_map;
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const void *read32_map;
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const void **write8_tab;
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const void **write16_tab;
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const void **write32_tab;
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// drc stuff
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int drc_tmp;
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int irq_cycles;
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void *p_bios; // convenience pointers
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void *p_da;
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void *p_sdram;
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void *p_rom;
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void *p_dram;
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void *p_drcblk_da;
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void *p_drcblk_ram;
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unsigned int pdb_io_csum[2];
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#define SH2_STATE_RUN (1 << 0) // to prevent recursion
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#define SH2_STATE_SLEEP (1 << 1) // temporarily stopped (DMA, IO, ...)
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#define SH2_STATE_CPOLL (1 << 2) // polling comm regs
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#define SH2_STATE_VPOLL (1 << 3) // polling VDP
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#define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM
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#define SH2_TIMER_RUN (1 << 8) // SOC WDT timer is running
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unsigned int state;
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uint32_t poll_addr;
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int poll_cycles;
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int poll_cnt;
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// DRC branch cache. size must be 2^n and <=128
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int rts_cache_idx;
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struct { uint32_t pc; void *code; } rts_cache[16];
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struct { uint32_t pc; void *code; } branch_cache[128];
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// interpreter stuff
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int icount; // cycles left in current timeslice
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unsigned int ea;
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unsigned int delay;
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unsigned int test_irq;
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int pending_level; // MAX(pending_irl, pending_int_irq)
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int pending_irl;
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int pending_int_irq; // internal irq
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int pending_int_vector;
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int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);
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int is_slave;
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unsigned int cycles_timeslice;
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struct SH2_ *other_sh2;
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int (*run)(struct SH2_ *, int);
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// we use 68k reference cycles for easier sync
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unsigned int m68krcycles_done;
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unsigned int mult_m68k_to_sh2;
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unsigned int mult_sh2_to_m68k;
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uint8_t data_array[0x1000]; // cache (can be used as RAM)
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uint32_t peri_regs[0x200/4]; // peripheral regs
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} SH2;
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#define CYCLE_MULT_SHIFT 10
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#define C_M68K_TO_SH2(xsh2, c) \
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(int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
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#define C_SH2_TO_M68K(xsh2, c) \
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(int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
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int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
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void sh2_finish(SH2 *sh2);
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void sh2_reset(SH2 *sh2);
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int sh2_irl_irq(SH2 *sh2, int level, int nested_call);
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void sh2_internal_irq(SH2 *sh2, int level, int vector);
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void sh2_do_irq(SH2 *sh2, int level, int vector);
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void sh2_pack(const SH2 *sh2, unsigned char *buff);
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void sh2_unpack(SH2 *sh2, const unsigned char *buff);
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int sh2_execute_drc(SH2 *sh2c, int cycles);
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int sh2_execute_interpreter(SH2 *sh2c, int cycles);
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static __inline void sh2_execute_prepare(SH2 *sh2, int use_drc)
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{
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#ifdef DRC_SH2
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sh2->run = use_drc ? sh2_execute_drc : sh2_execute_interpreter;
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#else
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sh2->run = sh2_execute_interpreter;
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#endif
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}
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static __inline int sh2_execute(SH2 *sh2, int cycles)
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{
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int ret;
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sh2->cycles_timeslice = cycles;
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ret = sh2->run(sh2, cycles);
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return sh2->cycles_timeslice - ret;
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}
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// regs, pending_int*, cycles, reserved
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#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)
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// pico memhandlers
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// XXX: move somewhere else
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unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
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unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
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unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
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void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
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void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
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void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
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// debug
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#ifdef DRC_CMP
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void do_sh2_trace(SH2 *current, int cycles);
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void REGPARM(1) do_sh2_cmp(SH2 *current);
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#endif
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#endif /* __SH2_H__ */
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