mirror of
https://github.com/RaySollium99/picodrive.git
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80599a42db
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@826 be3aeb3a-fb24-0410-a615-afba39da0efa
399 lines
14 KiB
C
399 lines
14 KiB
C
// Basic macros to emit ARM instructions and some utils
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// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
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// Free for non-commercial use.
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#define CONTEXT_REG 7
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// XXX: tcache_ptr type for SVP and SH2 compilers differs..
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#define EMIT_PTR(ptr, x) \
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do { \
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*(u32 *)ptr = x; \
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ptr = (void *)((u8 *)ptr + sizeof(u32)); \
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COUNT_OP; \
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} while (0)
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#define EMIT(x) EMIT_PTR(tcache_ptr, x)
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#define A_R4M (1 << 4)
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#define A_R5M (1 << 5)
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#define A_R6M (1 << 6)
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#define A_R7M (1 << 7)
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#define A_R8M (1 << 8)
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#define A_R9M (1 << 9)
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#define A_R10M (1 << 10)
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#define A_R11M (1 << 11)
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#define A_R14M (1 << 14)
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#define A_COND_AL 0xe
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#define A_COND_EQ 0x0
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#define A_COND_NE 0x1
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#define A_COND_MI 0x4
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#define A_COND_PL 0x5
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#define A_COND_LS 0x9
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#define A_COND_LE 0xd
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/* unified conditions */
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#define DCOND_EQ A_COND_EQ
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#define DCOND_NE A_COND_NE
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#define DCOND_MI A_COND_MI
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#define DCOND_PL A_COND_PL
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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#define A_AM1_LSR 1
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#define A_AM1_ASR 2
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#define A_AM1_ROR 3
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#define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
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#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
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#define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
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/* data processing op */
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#define A_OP_AND 0x0
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#define A_OP_EOR 0x1
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#define A_OP_SUB 0x2
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#define A_OP_RSB 0x3
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#define A_OP_ADD 0x4
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#define A_OP_TST 0x8
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#define A_OP_TEQ 0x9
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#define A_OP_CMP 0xa
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#define A_OP_ORR 0xc
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#define A_OP_MOV 0xd
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#define A_OP_BIC 0xe
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#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
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EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
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#define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
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#define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
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#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
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#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
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#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
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#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
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#define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
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#define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
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#define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
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#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
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#define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
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#define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
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#define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
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#define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
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#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
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#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
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#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
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#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
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#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
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#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
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#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
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#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
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#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
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#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
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#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
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#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
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#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
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#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
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#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
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#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
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#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
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#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
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/* addressing mode 2 */
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#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
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EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
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/* addressing mode 3 */
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#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
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EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
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((s)<<6) | ((h)<<5) | (immed_reg))
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#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
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#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
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/* ldr and str */
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#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
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#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
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#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
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#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
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#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
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#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
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#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
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#define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
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/* ldm and stm */
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#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
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EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
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#define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
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#define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
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/* branches */
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#define EOP_C_BX(cond,rm) \
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EMIT(((cond)<<28) | 0x012fff10 | (rm))
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#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
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#define EOP_C_B(cond,l,signed_immed_24) \
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EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
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#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
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/* misc */
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#define EOP_C_MUL(cond,s,rd,rs,rm) \
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EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
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#define EOP_C_MRS(cond,rd) \
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EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
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#define EOP_C_MSR_IMM(cond,ror2,imm) \
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EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
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#define EOP_C_MSR_REG(cond,rm) \
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EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
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#define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
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#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
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#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
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static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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{
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int ror2, rd = r, rn = r;
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u32 v;
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if (op == A_OP_MOV)
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rn = 0;
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else if (op == A_OP_TST || op == A_OP_TEQ)
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rd = 0;
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else if (imm == 0)
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return;
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for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
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/* shift down to get 'best' rot2 */
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for (; v && !(v & 3); v >>= 2)
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ror2--;
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EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
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if (op == A_OP_MOV) {
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op = A_OP_ORR;
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rn = r;
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}
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}
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}
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#define is_offset_24(val) \
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((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
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static int emith_xbranch(int cond, void *target, int is_call)
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{
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int val = (u32 *)target - (u32 *)tcache_ptr - 2;
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int direct = is_offset_24(val);
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u32 *start_ptr = (u32 *)tcache_ptr;
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if (direct)
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{
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EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
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}
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else
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{
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#ifdef __EPOC32__
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// elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
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if (is_call)
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EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
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EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
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EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
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EMIT((u32)target);
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#else
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// should never happen
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elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
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exit(1);
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#endif
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}
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return (u32 *)tcache_ptr - start_ptr;
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}
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// fake "simple" or "short" jump - using cond insns instead
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#define EMITH_SJMP_START(cond) \
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(void)(cond)
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#define EMITH_SJMP_END(cond) \
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(void)(cond)
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#define EMITH_CONDITIONAL(code, is_nonzero) { \
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u32 val, cond, *ptr; \
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cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
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ptr = (void *)tcache_ptr; \
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tcache_ptr = (void *)(ptr + 1); \
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code; \
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val = (u32 *)tcache_ptr - (ptr + 2); \
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | (val & 0xffffff)); \
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}
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#define emith_move_r_r(d, s) \
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EOP_MOV_REG_SIMPLE(d, s)
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#define emith_add_r_r(d, s) \
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EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_sub_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_teq_r_r(d, s) \
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EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
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#define emith_subf_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_move_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
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#define emith_add_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
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#define emith_sub_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
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#define emith_bic_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
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#define emith_or_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
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// note: use 8bit imm only
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#define emith_tst_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_TST, r, imm)
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#define emith_subf_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
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#define emith_add_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ADD, r, imm)
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#define emith_sub_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_SUB, r, imm)
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ORR, r, imm)
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#define emith_lsl(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
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#define emith_lsr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
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#define emith_asrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
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#define emith_mul(d, s1, s2) { \
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if ((d) != (s1)) /* rd != rm limitation */ \
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EOP_MUL(d, s1, s2); \
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else \
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EOP_MUL(d, s2, s1); \
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}
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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#define emith_ctx_write(r, offs) \
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EOP_STR_IMM(r, CONTEXT_REG, offs)
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#define emith_clear_msb(d, s, count) { \
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u32 t; \
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if ((count) <= 8) { \
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t = (count) - 8; \
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t = (0xff << t) & 0xff; \
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EOP_BIC_IMM(d,s,8/2,t); \
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} else if ((count) >= 24) { \
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t = (count) - 24; \
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t = 0xff >> t; \
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EOP_AND_IMM(d,s,0,t); \
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} else { \
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EOP_MOV_REG_LSL(d,s,count); \
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EOP_MOV_REG_LSR(d,d,count); \
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} \
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}
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#define emith_sext(d, s, bits) { \
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EOP_MOV_REG_LSL(d,s,32 - (bits)); \
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EOP_MOV_REG_ASR(d,d,32 - (bits)); \
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}
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#define host_arg2reg(rd, arg) \
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rd = arg
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// upto 4 args
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#define emith_pass_arg_r(arg, reg) \
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EOP_MOV_REG_SIMPLE(arg, reg)
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#define emith_pass_arg_imm(arg, imm) \
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emith_move_r_imm(arg, imm)
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#define emith_call_cond(cond, target) \
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emith_xbranch(cond, target, 1)
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#define emith_jump_cond(cond, target) \
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emith_xbranch(cond, target, 0)
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#define emith_call(target) \
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emith_call_cond(A_COND_AL, target)
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#define emith_jump(target) \
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emith_jump_cond(A_COND_AL, target)
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/* SH2 drc specific */
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#define emith_sh2_test_t() { \
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int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
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EOP_TST_IMM(r, 0, 1); \
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}
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#define emith_sh2_dtbf_loop() { \
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int cr, rn; \
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tmp = rcache_get_tmp(); \
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cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
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emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
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emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
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emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
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cycles = 0; \
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emith_asrf(tmp, cr, 2+12); /* movs tmp, cr, asr #2+12 */ \
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EOP_MOV_IMM_C(A_COND_MI,tmp,0,0); /* movmi tmp, #0 */ \
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emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
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emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
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emith_subf_r_r(rn, tmp); /* subs rn, tmp */ \
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EOP_RSB_IMM_C(A_COND_LS,tmp,rn,0,0); /* rsbls tmp, rn, #0 */ \
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EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp,A_AM1_LSL,12+2); /* orrls cr,tmp,lsl #12+2 */\
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EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
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EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
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rcache_free_tmp(tmp); \
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}
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