mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
1cfc5cc4ce
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@576 be3aeb3a-fb24-0410-a615-afba39da0efa
919 lines
20 KiB
ArmAsm
919 lines
20 KiB
ArmAsm
@ this is a rewrite of MAME's ym2612 code, in particular this is only the main sample-generatin loop.
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@ it does not seem to give much performance increase (if any at all), so don't use it if it causes trouble.
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@ - notaz, 2006
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@ vim:filetype=armasm
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.equiv SLOT1, 0
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.equiv SLOT2, 2
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.equiv SLOT3, 1
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.equiv SLOT4, 3
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.equiv SLOT_STRUCT_SIZE, 0x30
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.equiv TL_TAB_LEN, 0x1A00
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.equiv EG_ATT, 4
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.equiv EG_DEC, 3
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.equiv EG_SUS, 2
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.equiv EG_REL, 1
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.equiv EG_OFF, 0
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.equiv EG_SH, 16 @ 16.16 fixed point (envelope generator timing)
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.equiv EG_TIMER_OVERFLOW, (3*(1<<EG_SH)) @ envelope generator timer overflows every 3 samples (on real chip)
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.equiv LFO_SH, 25 /* 7.25 fixed point (LFO calculations) */
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.equiv ENV_QUIET, (2*13*256/8)/2
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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@ writes output to routp, but only if vol_out changes
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.macro update_eg_phase_slot slot
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ldrb r2, [r5,#0x17] @ state
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mov r3, #1 @ 1ci
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cmp r2, #1
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blt 5f @ EG_OFF
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beq 3f @ EG_REL
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cmp r2, #3
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blt 2f @ EG_SUS
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beq 1f @ EG_DEC
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0: @ EG_ATT
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ldr r2, [r5,#0x20] @ eg_pack_ar (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mvn r2, r0
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mov r2, r2, lsl r3
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add r0, r0, r2, asr #5
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cmp r0, #0 @ if (volume <= MIN_ATT_INDEX)
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movle r3, #EG_DEC
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strleb r3, [r5,#0x17] @ state
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movle r0, #0
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b 4f
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1: @ EG_DEC
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ldr r2, [r5,#0x24] @ eg_pack_d1r (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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ldr r2, [r5,#0x1c] @ sl (can be 16bit?)
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add r0, r0, r3, asr #1
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cmp r0, r2 @ if ( volume >= (INT32) SLOT->sl )
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movge r3, #EG_SUS
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strgeb r3, [r5,#0x17] @ state
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b 4f
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2: @ EG_SUS
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ldr r2, [r5,#0x28] @ eg_pack_d2r (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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add r0, r0, r3, asr #1
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mov r2, #1024
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sub r2, r2, #1 @ r2 = MAX_ATT_INDEX
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cmp r0, r2 @ if ( volume >= MAX_ATT_INDEX )
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movge r0, r2
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b 4f
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3: @ EG_REL
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ldr r2, [r5,#0x2c] @ eg_pack_rr (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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add r0, r0, r3, asr #1
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mov r2, #1024
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sub r2, r2, #1 @ r2 = MAX_ATT_INDEX
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cmp r0, r2 @ if ( volume >= MAX_ATT_INDEX )
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movge r0, r2
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movge r3, #EG_OFF
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strgeb r3, [r5,#0x17] @ state
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4:
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ldrh r3, [r5,#0x18] @ tl
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strh r0, [r5,#0x1a] @ volume
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.if \slot == SLOT1
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mov r6, r6, lsr #16
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add r0, r0, r3
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orr r6, r0, r6, lsl #16
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.elseif \slot == SLOT2
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mov r6, r6, lsl #16
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add r0, r0, r3
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mov r0, r0, lsl #16
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orr r6, r0, r6, lsr #16
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.elseif \slot == SLOT3
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mov r7, r7, lsr #16
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add r0, r0, r3
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orr r7, r0, r7, lsl #16
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.elseif \slot == SLOT4
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mov r7, r7, lsl #16
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add r0, r0, r3
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mov r0, r0, lsl #16
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orr r7, r0, r7, lsr #16
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.endif
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5:
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.endm
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@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt, r3=scratch
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.macro advance_lfo_m
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mov r2, r2, lsr #LFO_SH
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cmp r2, r1, lsr #LFO_SH
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beq 0f
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and r3, r2, #0x3f
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cmp r2, #0x40
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rsbge r3, r3, #0x3f
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bic r12,r12, #0xff000000 @ lfo_ampm &= 0xff
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orr r12,r12, r3, lsl #1+24
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mov r2, r2, lsr #2
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cmp r2, r1, lsr #LFO_SH+2
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bicne r12,r12, #0xff0000
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orrne r12,r12, r2, lsl #16
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0:
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.endm
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@ result goes to r1, trashes r2
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.macro make_eg_out slot
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tst r12, #8
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tstne r12, #(1<<(\slot+8))
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.if \slot == SLOT1
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mov r1, r6, lsl #16
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mov r1, r1, lsr #17
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.elseif \slot == SLOT2
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mov r1, r6, lsr #17
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.elseif \slot == SLOT3
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mov r1, r7, lsl #16
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mov r1, r1, lsr #17
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.elseif \slot == SLOT4
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mov r1, r7, lsr #17
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.endif
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andne r2, r12, #0xc0
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movne r2, r2, lsr #6
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addne r2, r2, #24
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addne r1, r1, r12, lsr r2
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.endm
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.macro lookup_tl r
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tst \r, #0x100
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eorne \r, \r, #0xff @ if (sin & 0x100) sin = 0xff - (sin&0xff);
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tst \r, #0x200
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and \r, \r, #0xff
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orr \r, \r, r1, lsl #8
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mov \r, \r, lsl #1
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ldrh \r, [r3, \r] @ 2ci if ne
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rsbne \r, \r, #0
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.endm
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@ lr=context, r12=pack (stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
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@ r0-r2=scratch, r3=sin_tab, r5=scratch, r6-r7=vol_out[4], r10=op1_out
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.macro upd_algo0_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r2, [lr, #0x18]
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ldr r0, [lr, #0x38] @ mem (signed)
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mov r2, r2, lsr #16
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add r0, r2, r0, lsr #1
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lookup_tl r0 @ r0=c2
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0:
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r0, r0, lsr #1
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add r0, r0, r2, lsr #16
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lookup_tl r0 @ r0=output smp
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1:
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@ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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movcs r2, #0
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bcs 2f
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ldr r2, [lr, #0x14] @ 1ci
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2 @ r2=mem
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2:
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str r2, [lr, #0x38] @ mem
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.endm
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.macro upd_algo1_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r2, [lr, #0x18]
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ldr r0, [lr, #0x38] @ mem (signed)
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mov r2, r2, lsr #16
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add r0, r2, r0, lsr #1
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lookup_tl r0 @ r0=c2
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0:
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r0, r0, lsr #1
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add r0, r0, r2, lsr #16
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lookup_tl r0 @ r0=output smp
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1:
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@ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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movcs r2, #0
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bcs 2f
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ldr r2, [lr, #0x14] @ 1ci
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mov r2, r2, lsr #16
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lookup_tl r2 @ r2=mem
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2:
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add r2, r2, r10, asr #16
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str r2, [lr, #0x38]
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.endm
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.macro upd_algo2_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r2, [lr, #0x18]
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ldr r0, [lr, #0x38] @ mem (signed)
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mov r2, r2, lsr #16
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add r0, r2, r0, lsr #1
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lookup_tl r0 @ r0=c2
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0:
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add r0, r0, r10, asr #16
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r0, r0, lsr #1
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add r0, r0, r2, lsr #16
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lookup_tl r0 @ r0=output smp
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1:
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@ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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movcs r2, #0
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bcs 2f
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ldr r2, [lr, #0x14]
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mov r2, r2, lsr #16 @ 1ci
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lookup_tl r2 @ r2=mem
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2:
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str r2, [lr, #0x38] @ mem
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.endm
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.macro upd_algo3_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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ldr r2, [lr, #0x38] @ mem (for future)
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movcs r0, r2
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bcs 0f
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ldr r0, [lr, #0x18] @ 1ci
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mov r0, r0, lsr #16
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lookup_tl r0 @ r0=c2
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0:
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add r0, r0, r2
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r0, r0, lsr #1
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add r0, r0, r2, lsr #16
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lookup_tl r0 @ r0=output smp
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1:
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@ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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movcs r2, #0
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bcs 2f
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ldr r2, [lr, #0x14]
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2 @ r2=mem
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2:
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str r2, [lr, #0x38] @ mem
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.endm
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.macro upd_algo4_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r0, [lr, #0x18]
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mov r0, r0, lsr #16 @ 1ci
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lookup_tl r0 @ r0=c2
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0:
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r0, r0, lsr #1
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add r0, r0, r2, lsr #16
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lookup_tl r0 @ r0=output smp
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1:
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@ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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bcs 2f
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ldr r2, [lr, #0x14]
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2
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add r0, r0, r2 @ add to smp
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2:
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.endm
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.macro upd_algo5_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r2, [lr, #0x18]
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ldr r0, [lr, #0x38] @ mem (signed)
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mov r2, r2, lsr #16
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add r0, r2, r0, lsr #1
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lookup_tl r0 @ r0=output smp
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0:
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2
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add r0, r0, r2 @ add to smp
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1: @ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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bcs 2f
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ldr r2, [lr, #0x14]
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2
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add r0, r0, r2 @ add to smp
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2:
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mov r1, r10, asr #16
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str r1, [lr, #0x38] @ mem
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.endm
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.macro upd_algo6_m
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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movcs r0, #0
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bcs 0f
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ldr r0, [lr, #0x18]
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mov r0, r0, lsr #16 @ 1ci
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lookup_tl r0 @ r0=output smp
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0:
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@ SLOT4
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make_eg_out SLOT4
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cmp r1, #ENV_QUIET
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bcs 1f
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ldr r2, [lr, #0x1c]
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mov r2, r2, lsr #16 @ 1ci
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lookup_tl r2
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add r0, r0, r2 @ add to smp
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1: @ SLOT2
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make_eg_out SLOT2
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cmp r1, #ENV_QUIET
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bcs 2f
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ldr r2, [lr, #0x14]
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2
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add r0, r0, r2 @ add to smp
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2:
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.endm
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.macro upd_algo7_m
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@ SLOT3
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make_eg_out SLOT3
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|
cmp r1, #ENV_QUIET
|
|
movcs r0, #0
|
|
bcs 0f
|
|
ldr r0, [lr, #0x18]
|
|
mov r0, r0, lsr #16 @ 1ci
|
|
lookup_tl r0 @ r0=output smp
|
|
|
|
0:
|
|
add r0, r0, r10, asr #16
|
|
|
|
@ SLOT4
|
|
make_eg_out SLOT4
|
|
cmp r1, #ENV_QUIET
|
|
bcs 1f
|
|
ldr r2, [lr, #0x1c]
|
|
mov r2, r2, lsr #16 @ 1ci
|
|
lookup_tl r2
|
|
add r0, r0, r2 @ add to smp
|
|
|
|
1: @ SLOT2
|
|
make_eg_out SLOT2
|
|
cmp r1, #ENV_QUIET
|
|
bcs 2f
|
|
ldr r2, [lr, #0x14]
|
|
mov r2, r2, lsr #16 @ 1ci
|
|
lookup_tl r2
|
|
add r0, r0, r2 @ add to smp
|
|
|
|
2:
|
|
.endm
|
|
|
|
|
|
.macro upd_slot1_m
|
|
|
|
make_eg_out SLOT1
|
|
cmp r1, #ENV_QUIET
|
|
movcs r10, r10, lsl #16 @ ct->op1_out <<= 16; // op1_out0 = op1_out1; op1_out1 = 0;
|
|
bcs 0f
|
|
ands r2, r12, #0xf000
|
|
moveq r0, #0
|
|
movne r2, r2, lsr #12
|
|
addne r0, r10, r10, lsl #16
|
|
movne r0, r0, asr #16
|
|
movne r0, r0, lsl r2
|
|
|
|
ldr r2, [lr, #0x10]
|
|
mov r0, r0, lsr #16
|
|
add r0, r0, r2, lsr #16
|
|
lookup_tl r0
|
|
mov r10,r10,lsl #16 @ ct->op1_out <<= 16;
|
|
mov r0, r0, lsl #16
|
|
orr r10,r10, r0, lsr #16
|
|
|
|
0:
|
|
.endm
|
|
|
|
|
|
/*
|
|
.global update_eg_phase @ FM_SLOT *SLOT, UINT32 eg_cnt
|
|
|
|
update_eg_phase:
|
|
stmfd sp!, {r5,r6}
|
|
mov r5, r0 @ slot
|
|
ldrh r3, [r5,#0x18] @ tl
|
|
ldrh r6, [r5,#0x1a] @ volume
|
|
add r6, r6, r3
|
|
update_eg_phase_slot SLOT1
|
|
mov r0, r6
|
|
ldmfd sp!, {r5,r6}
|
|
bx lr
|
|
.pool
|
|
|
|
|
|
.global advance_lfo @ int lfo_ampm, UINT32 lfo_cnt_old, UINT32 lfo_cnt
|
|
|
|
advance_lfo:
|
|
mov r12, r0, lsl #16
|
|
advance_lfo_m
|
|
mov r0, r12, lsr #16
|
|
bx lr
|
|
.pool
|
|
|
|
|
|
.global upd_algo0 @ chan_rend_context *c
|
|
upd_algo0:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo0_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo1 @ chan_rend_context *c
|
|
upd_algo1:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo1_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo2 @ chan_rend_context *c
|
|
upd_algo2:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo2_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo3 @ chan_rend_context *c
|
|
upd_algo3:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo3_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo4 @ chan_rend_context *c
|
|
upd_algo4:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo4_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo5 @ chan_rend_context *c
|
|
upd_algo5:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo5_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo6 @ chan_rend_context *c
|
|
upd_algo6:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo6_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_algo7 @ chan_rend_context *c
|
|
upd_algo7:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_algo7_m
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
|
|
|
|
.global upd_slot1 @ chan_rend_context *c
|
|
upd_slot1:
|
|
stmfd sp!, {r4-r10,lr}
|
|
mov lr, r0
|
|
|
|
ldr r3, =ym_sin_tab
|
|
ldr r5, =ym_tl_tab
|
|
ldmia lr, {r6-r7}
|
|
ldr r10, [lr, #0x54]
|
|
ldr r12, [lr, #0x4c]
|
|
|
|
upd_slot1_m
|
|
str r10, [lr, #0x38]
|
|
|
|
ldmfd sp!, {r4-r10,pc}
|
|
.pool
|
|
*/
|
|
|
|
|
|
@ lr=context, r12=pack (stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
|
|
@ r0-r2=scratch, r3=sin_tab/scratch, r4=(length<<8)|unused[4],was_update,algo[3], r5=tl_tab/slot,
|
|
@ r6-r7=vol_out[4], r8=eg_timer, r9=eg_timer_add[31:16], r10=op1_out, r11=buffer
|
|
.global chan_render_loop @ chan_rend_context *ct, int *buffer, int length
|
|
|
|
chan_render_loop:
|
|
stmfd sp!, {r4-r11,lr}
|
|
mov lr, r0
|
|
mov r4, r2, lsl #8 @ no more 24 bits here
|
|
ldr r12, [lr, #0x4c]
|
|
ldr r0, [lr, #0x50]
|
|
mov r11, r1
|
|
and r0, r0, #7
|
|
orr r4, r4, r0 @ (length<<8)|algo
|
|
add r0, lr, #0x44
|
|
ldmia r0, {r8,r9} @ eg_timer, eg_timer_add
|
|
ldr r10, [lr, #0x54] @ op1_out
|
|
ldmia lr, {r6,r7} @ load volumes
|
|
|
|
tst r12, #8 @ lfo?
|
|
beq crl_loop
|
|
|
|
crl_loop_lfo:
|
|
add r0, lr, #0x30
|
|
ldmia r0, {r1,r2}
|
|
add r2, r2, r1
|
|
str r2, [lr, #0x30]
|
|
@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt
|
|
advance_lfo_m
|
|
|
|
crl_loop:
|
|
subs r4, r4, #0x100
|
|
bmi crl_loop_end
|
|
|
|
@ -- EG --
|
|
add r8, r8, r9
|
|
cmp r8, #EG_TIMER_OVERFLOW
|
|
bcc eg_done
|
|
add r0, lr, #0x3c
|
|
ldmia r0, {r1,r5} @ eg_cnt, CH
|
|
eg_loop:
|
|
sub r8, r8, #EG_TIMER_OVERFLOW
|
|
add r1, r1, #1
|
|
@ SLOT1 (0)
|
|
@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
|
|
update_eg_phase_slot SLOT1
|
|
add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT2 (2)
|
|
update_eg_phase_slot SLOT2
|
|
sub r5, r5, #SLOT_STRUCT_SIZE @ SLOT3 (1)
|
|
update_eg_phase_slot SLOT3
|
|
add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT4 (3)
|
|
update_eg_phase_slot SLOT4
|
|
|
|
cmp r8, #EG_TIMER_OVERFLOW
|
|
subcs r5, r5, #SLOT_STRUCT_SIZE*3
|
|
bcs eg_loop
|
|
str r1, [lr, #0x3c]
|
|
|
|
eg_done:
|
|
|
|
@ -- disabled? --
|
|
and r0, r12, #0xC
|
|
cmp r0, #0xC
|
|
beq crl_loop_lfo
|
|
cmp r0, #0x4
|
|
beq crl_loop
|
|
|
|
@ -- SLOT1 --
|
|
ldr r3, =ym_tl_tab
|
|
|
|
@ lr=context, r12=pack (stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
|
|
@ r0-r2=scratch, r3=tl_tab, r5=scratch, r6-r7=vol_out[4], r10=op1_out
|
|
upd_slot1_m
|
|
|
|
@ -- SLOT2+ --
|
|
and r0, r4, #7
|
|
ldr pc, [pc, r0, lsl #2]
|
|
nop
|
|
.word crl_algo0
|
|
.word crl_algo1
|
|
.word crl_algo2
|
|
.word crl_algo3
|
|
.word crl_algo4
|
|
.word crl_algo5
|
|
.word crl_algo6
|
|
.word crl_algo7
|
|
.pool
|
|
|
|
crl_algo0:
|
|
upd_algo0_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo1:
|
|
upd_algo1_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo2:
|
|
upd_algo2_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo3:
|
|
upd_algo3_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo4:
|
|
upd_algo4_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo5:
|
|
upd_algo5_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo6:
|
|
upd_algo6_m
|
|
b crl_algo_done
|
|
.pool
|
|
|
|
crl_algo7:
|
|
upd_algo7_m
|
|
.pool
|
|
|
|
|
|
crl_algo_done:
|
|
@ -- WRITE SAMPLE --
|
|
tst r0, r0
|
|
beq ctl_sample_skip
|
|
orr r4, r4, #8 @ have_output
|
|
tst r12, #1
|
|
beq ctl_sample_mono
|
|
|
|
tst r12, #0x20 @ L
|
|
ldrne r1, [r11]
|
|
addeq r11, r11, #4
|
|
addne r1, r0, r1
|
|
strne r1, [r11], #4
|
|
tst r12, #0x10 @ R
|
|
ldrne r1, [r11]
|
|
addeq r11, r11, #4
|
|
addne r1, r0, r1
|
|
strne r1, [r11], #4
|
|
b crl_do_phase
|
|
|
|
ctl_sample_skip:
|
|
and r1, r12, #1
|
|
add r1, r1, #1
|
|
add r11,r11, r1, lsl #2
|
|
b crl_do_phase
|
|
|
|
ctl_sample_mono:
|
|
ldr r1, [r11]
|
|
add r1, r0, r1
|
|
str r1, [r11], #4
|
|
|
|
crl_do_phase:
|
|
@ -- PHASE UPDATE --
|
|
add r5, lr, #0x10
|
|
ldmia r5, {r0-r1}
|
|
add r5, lr, #0x20
|
|
ldmia r5, {r2-r3}
|
|
add r5, lr, #0x10
|
|
add r0, r0, r2
|
|
add r1, r1, r3
|
|
stmia r5!,{r0-r1}
|
|
ldmia r5, {r0-r1}
|
|
add r5, lr, #0x28
|
|
ldmia r5, {r2-r3}
|
|
add r5, lr, #0x18
|
|
add r0, r0, r2
|
|
add r1, r1, r3
|
|
stmia r5, {r0-r1}
|
|
|
|
tst r12, #8
|
|
bne crl_loop_lfo
|
|
b crl_loop
|
|
|
|
|
|
crl_loop_end:
|
|
str r8, [lr, #0x44] @ eg_timer
|
|
str r12, [lr, #0x4c] @ pack (for lfo_ampm)
|
|
str r4, [lr, #0x50] @ was_update
|
|
str r10, [lr, #0x54] @ op1_out
|
|
ldmfd sp!, {r4-r11,pc}
|
|
|
|
.pool
|
|
|