mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
532 lines
14 KiB
C
532 lines
14 KiB
C
/*
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* PicoDrive
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* (C) notaz, 2009,2010,2013
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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#include "../pico_int.h"
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#include "../sound/ym2612.h"
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#include "../../cpu/sh2/compiler.h"
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struct Pico32x Pico32x;
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SH2 sh2s[2];
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#define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
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static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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{
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if (sh2->pending_irl > sh2->pending_int_irq) {
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elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
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sh2->is_slave ? 's' : 'm', level, sh2->pc);
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return 64 + sh2->pending_irl / 2;
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} else {
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elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
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sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
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sh2->pending_int_irq = 0; // auto-clear
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sh2->pending_level = sh2->pending_irl;
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return sh2->pending_int_vector;
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}
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}
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// if !nested_call, must sync CPUs before calling this
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void p32x_update_irls(SH2 *active_sh2)
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{
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int irqs, mlvl = 0, slvl = 0;
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int m68k_cycles = 0;
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int mrun, srun;
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if (active_sh2 != NULL)
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m68k_cycles = sh2_cycles_done_m68k(active_sh2);
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// msh2
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irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
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while ((irqs >>= 1))
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mlvl++;
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mlvl *= 2;
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// ssh2
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irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
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while ((irqs >>= 1))
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slvl++;
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slvl *= 2;
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mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
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if (mrun)
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p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
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srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
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if (srun)
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p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
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elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
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}
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void Pico32xStartup(void)
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{
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elprintf(EL_STATUS|EL_32X, "32X startup");
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// TODO: OOM handling
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PicoAHW |= PAHW_32X;
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sh2_init(&msh2, 0);
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msh2.irq_callback = sh2_irq_cb;
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sh2_init(&ssh2, 1);
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ssh2.irq_callback = sh2_irq_cb;
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PicoMemSetup32x();
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p32x_timers_recalc();
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if (!Pico.m.pal)
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Pico32x.vdp_regs[0] |= P32XV_nPAL;
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PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
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PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
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rendstatus_old = -1;
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emu_32x_startup();
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}
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#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
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void p32x_reset_sh2s(void)
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{
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elprintf(EL_32X, "sh2 reset");
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sh2_reset(&msh2);
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sh2_reset(&ssh2);
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// if we don't have BIOS set, perform it's work here.
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// MSH2
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if (p32x_bios_m == NULL) {
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unsigned int idl_src, idl_dst, idl_size; // initial data load
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unsigned int vbr;
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// initial data
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idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
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idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
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idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
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if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
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idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
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elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
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idl_src, idl_dst, idl_size);
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}
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else
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memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
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// GBR/VBR
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vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
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sh2_set_gbr(0, 0x20004000);
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sh2_set_vbr(0, vbr);
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// checksum and M_OK
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Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
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// program will set M_OK
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}
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// SSH2
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if (p32x_bios_s == NULL) {
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unsigned int vbr;
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// GBR/VBR
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vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
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sh2_set_gbr(1, 0x20004000);
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sh2_set_vbr(1, vbr);
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// program will set S_OK
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}
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msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
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}
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void Pico32xInit(void)
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{
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if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
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Pico32xSetClocks(PICO_MSH2_HZ, 0);
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if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
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Pico32xSetClocks(0, PICO_MSH2_HZ);
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}
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void PicoPower32x(void)
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{
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memset(&Pico32x, 0, sizeof(Pico32x));
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Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
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Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
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Pico32x.sh2_regs[0] = P32XS2_ADEN;
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}
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void PicoUnload32x(void)
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{
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if (Pico32xMem != NULL)
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plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
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Pico32xMem = NULL;
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sh2_finish(&msh2);
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sh2_finish(&ssh2);
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PicoAHW &= ~PAHW_32X;
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}
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void PicoReset32x(void)
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{
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if (PicoAHW & PAHW_32X) {
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Pico32x.sh2irqs |= P32XI_VRES;
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p32x_update_irls(NULL);
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p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
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p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
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p32x_timers_recalc();
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}
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}
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static void p32x_start_blank(void)
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{
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if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
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int offs, lines;
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pprof_start(draw);
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offs = 8; lines = 224;
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if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
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offs = 0;
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lines = 240;
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}
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// XXX: no proper handling of 32col mode..
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if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
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(Pico.video.reg[12] & 1) && // 40col mode
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(PicoDrawMask & PDRAW_32X_ON))
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{
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int md_bg = Pico.video.reg[7] & 0x3f;
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// we draw full layer (not line-by-line)
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PicoDraw32xLayer(offs, lines, md_bg);
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}
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else if (Pico32xDrawMode != PDM32X_32X_ONLY)
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PicoDraw32xLayerMdOnly(offs, lines);
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pprof_end(draw);
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}
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// enter vblank
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Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
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// FB swap waits until vblank
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if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
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Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
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Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
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}
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Pico32x.sh2irqs |= P32XI_VINT;
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p32x_update_irls(NULL);
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
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}
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// compare cycles, handling overflows
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// check if a > b
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#define CYCLES_GT(a, b) \
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((int)((a) - (b)) > 0)
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// check if a >= b
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#define CYCLES_GE(a, b) \
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((int)((a) - (b)) >= 0)
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/* events */
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static void pwm_irq_event(unsigned int now)
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{
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Pico32x.emu_flags &= ~P32XF_PWM_PEND;
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p32x_pwm_schedule(now);
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Pico32x.sh2irqs |= P32XI_PWM;
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p32x_update_irls(NULL);
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}
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static void fillend_event(unsigned int now)
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{
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
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}
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typedef void (event_cb)(unsigned int now);
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unsigned int event_times[P32X_EVENT_COUNT];
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static unsigned int event_time_next;
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static event_cb *event_cbs[] = {
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[P32X_EVENT_PWM] = pwm_irq_event,
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[P32X_EVENT_FILLEND] = fillend_event,
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};
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// schedule event at some time 'after', in m68k clocks
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void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
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{
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unsigned int when;
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when = (now + after) | 1;
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elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
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event_times[event] = when;
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if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
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event_time_next = when;
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}
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void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
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{
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unsigned int now = sh2_cycles_done_m68k(sh2);
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int left_to_next;
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p32x_event_schedule(now, event, after);
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left_to_next = (event_time_next - now) * 3;
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if (sh2_cycles_left(sh2) > left_to_next)
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sh2_end_run(sh2, left_to_next);
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}
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static void run_events(unsigned int until)
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{
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int oldest, oldest_diff, time;
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int i, diff;
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while (1) {
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oldest = -1, oldest_diff = 0x7fffffff;
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for (i = 0; i < P32X_EVENT_COUNT; i++) {
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if (event_times[i]) {
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diff = event_times[i] - until;
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if (diff < oldest_diff) {
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oldest_diff = diff;
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oldest = i;
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}
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}
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}
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if (oldest_diff <= 0) {
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time = event_times[oldest];
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event_times[oldest] = 0;
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elprintf(EL_32X, "run event #%d %u", oldest, time);
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event_cbs[oldest](time);
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}
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else if (oldest_diff < 0x7fffffff) {
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event_time_next = event_times[oldest];
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break;
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}
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else {
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event_time_next = 0;
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break;
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}
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}
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if (oldest != -1)
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elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
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}
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static inline void run_sh2(SH2 *sh2, int m68k_cycles)
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{
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int cycles, done;
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pevt_log_sh2_o(sh2, EVT_RUN_START);
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sh2->state |= SH2_STATE_RUN;
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cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
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elprintf(EL_32X, "%csh2 +run %u %d",
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sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
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done = sh2_execute(sh2, cycles);
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sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
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sh2->state &= ~SH2_STATE_RUN;
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pevt_log_sh2_o(sh2, EVT_RUN_END);
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elprintf(EL_32X, "%csh2 -run %u %d",
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sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
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}
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// sync other sh2 to this one
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// note: recursive call
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void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
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{
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SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
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int left_to_event;
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int m68k_cycles;
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if (osh2->state & SH2_STATE_RUN)
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return;
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m68k_cycles = m68k_target - osh2->m68krcycles_done;
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if (m68k_cycles < 200)
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return;
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if (osh2->state & SH2_IDLE_STATES) {
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osh2->m68krcycles_done = m68k_target;
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return;
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}
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elprintf(EL_32X, "%csh2 sync to %u %d",
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osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
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run_sh2(osh2, m68k_cycles);
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// there might be new event to schedule current sh2 to
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if (event_time_next) {
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left_to_event = event_time_next - m68k_target;
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left_to_event *= 3;
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if (sh2_cycles_left(sh2) > left_to_event) {
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if (left_to_event < 1)
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left_to_event = 1;
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sh2_end_run(sh2, left_to_event);
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}
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}
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}
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#define sync_sh2s_normal p32x_sync_sh2s
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//#define sync_sh2s_lockstep p32x_sync_sh2s
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/* most timing is in 68k clock */
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void sync_sh2s_normal(unsigned int m68k_target)
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{
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unsigned int now, target, timer_cycles;
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int cycles;
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elprintf(EL_32X, "sh2 sync to %u", m68k_target);
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if (!(Pico32x.regs[0] & P32XS_nRES)) {
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msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
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return; // rare
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}
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now = msh2.m68krcycles_done;
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if (CYCLES_GT(now, ssh2.m68krcycles_done))
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now = ssh2.m68krcycles_done;
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timer_cycles = now;
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while (CYCLES_GT(m68k_target, now))
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{
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if (event_time_next && CYCLES_GE(now, event_time_next))
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run_events(now);
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target = m68k_target;
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if (event_time_next && CYCLES_GT(target, event_time_next))
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target = event_time_next;
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while (CYCLES_GT(target, now))
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{
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elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
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target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
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m68k_target - now, Pico32x.emu_flags);
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if (!(ssh2.state & SH2_IDLE_STATES)) {
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cycles = target - ssh2.m68krcycles_done;
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if (cycles > 0) {
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run_sh2(&ssh2, cycles);
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if (event_time_next && CYCLES_GT(target, event_time_next))
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target = event_time_next;
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}
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}
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if (!(msh2.state & SH2_IDLE_STATES)) {
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cycles = target - msh2.m68krcycles_done;
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if (cycles > 0) {
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run_sh2(&msh2, cycles);
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if (event_time_next && CYCLES_GT(target, event_time_next))
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target = event_time_next;
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}
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}
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now = target;
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if (!(msh2.state & SH2_IDLE_STATES)) {
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if (CYCLES_GT(now, msh2.m68krcycles_done))
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now = msh2.m68krcycles_done;
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}
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if (!(ssh2.state & SH2_IDLE_STATES)) {
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if (CYCLES_GT(now, ssh2.m68krcycles_done))
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now = ssh2.m68krcycles_done;
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}
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}
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p32x_timers_do(now, now - timer_cycles);
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timer_cycles = now;
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}
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// advance idle CPUs
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if (msh2.state & SH2_IDLE_STATES) {
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if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
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msh2.m68krcycles_done = m68k_target;
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}
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if (ssh2.state & SH2_IDLE_STATES) {
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if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
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ssh2.m68krcycles_done = m68k_target;
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}
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}
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#define STEP_68K 24
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void sync_sh2s_lockstep(unsigned int m68k_target)
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{
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unsigned int mcycles;
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mcycles = msh2.m68krcycles_done;
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if (ssh2.m68krcycles_done < mcycles)
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mcycles = ssh2.m68krcycles_done;
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while (mcycles < m68k_target) {
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mcycles += STEP_68K;
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sync_sh2s_normal(mcycles);
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}
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}
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#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
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SekRunM68k(m68k_cycles); \
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if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
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p32x_sync_sh2s(SekCyclesDoneT2()); \
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} while (0)
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#define PICO_32X
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#include "../pico_cmn.c"
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void PicoFrame32x(void)
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{
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
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if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
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PicoFrameStart();
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PicoFrameHints();
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sh2_drc_frame();
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elprintf(EL_32X, "poll: %02x %02x %02x",
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Pico32x.emu_flags & 3, msh2.state, ssh2.state);
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}
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// calculate multipliers against 68k clock (7670442)
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// normally * 3, but effectively slower due to high latencies everywhere
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// however using something lower breaks MK2 animations
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void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
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{
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float m68k_clk = (float)(OSC_NTSC / 7);
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if (msh2_hz > 0) {
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msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
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msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
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}
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if (ssh2_hz > 0) {
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ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
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ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
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}
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}
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|
|
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void Pico32xStateLoaded(int is_early)
|
|
{
|
|
if (is_early) {
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|
Pico32xMemStateLoaded();
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return;
|
|
}
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|
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SekCycleCnt = 0;
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|
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
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|
p32x_update_irls(NULL);
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|
p32x_timers_recalc();
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|
run_events(SekCycleCntT);
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|
}
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// vim:shiftwidth=2:ts=2:expandtab
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