mirror of
https://github.com/RaySollium99/picodrive.git
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c299a73848
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@471 be3aeb3a-fb24-0410-a615-afba39da0efa
304 lines
6.1 KiB
C
304 lines
6.1 KiB
C
/******************************************************************************
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*
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* CZ80 (Z80 CPU emulator) version 0.9
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* Compiled with Dev-C++
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* Copyright 2004-2005 Stéphane Dallongeville
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*
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* (Modified by NJ)
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*
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*****************************************************************************/
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#ifndef CZ80_H
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#define CZ80_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/******************************/
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/* Compiler dependant defines */
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/******************************/
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#ifndef UINT8
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#define UINT8 unsigned char
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#endif
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#ifndef INT8
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#define INT8 signed char
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#endif
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#ifndef UINT16
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#define UINT16 unsigned short
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#endif
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#ifndef INT16
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#define INT16 signed short
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#endif
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#ifndef UINT32
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#define UINT32 unsigned int
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#endif
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#ifndef INT32
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#define INT32 signed int
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#endif
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/*************************************/
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/* Z80 core Structures & definitions */
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/*************************************/
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#define CZ80_FETCH_BITS 4 // [4-12] default = 8
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#define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)
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#define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)
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#define PICODRIVE_HACKS 1
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#define CZ80_LITTLE_ENDIAN 1
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#define CZ80_USE_JUMPTABLE 1
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#define CZ80_BIG_FLAGS_ARRAY 1
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//#ifdef BUILD_CPS1PSP
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//#define CZ80_ENCRYPTED_ROM 1
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//#else
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#define CZ80_ENCRYPTED_ROM 0
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//#endif
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#define CZ80_EMULATE_R_EXACTLY 1
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#define zR8(A) (*CPU->pzR8[A])
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#define zR16(A) (CPU->pzR16[A]->W)
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#define pzAF &(CPU->AF)
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#define zAF CPU->AF.W
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#define zlAF CPU->AF.B.L
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#define zhAF CPU->AF.B.H
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#define zA zhAF
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#define zF zlAF
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#define pzBC &(CPU->BC)
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#define zBC CPU->BC.W
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#define zlBC CPU->BC.B.L
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#define zhBC CPU->BC.B.H
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#define zB zhBC
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#define zC zlBC
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#define pzDE &(CPU->DE)
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#define zDE CPU->DE.W
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#define zlDE CPU->DE.B.L
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#define zhDE CPU->DE.B.H
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#define zD zhDE
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#define zE zlDE
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#define pzHL &(CPU->HL)
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#define zHL CPU->HL.W
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#define zlHL CPU->HL.B.L
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#define zhHL CPU->HL.B.H
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#define zH zhHL
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#define zL zlHL
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#define zAF2 CPU->AF2.W
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#define zlAF2 CPU->AF2.B.L
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#define zhAF2 CPU->AF2.B.H
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#define zA2 zhAF2
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#define zF2 zlAF2
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#define zBC2 CPU->BC2.W
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#define zDE2 CPU->DE2.W
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#define zHL2 CPU->HL2.W
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#define pzIX &(CPU->IX)
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#define zIX CPU->IX.W
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#define zlIX CPU->IX.B.L
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#define zhIX CPU->IX.B.H
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#define pzIY &(CPU->IY)
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#define zIY CPU->IY.W
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#define zlIY CPU->IY.B.L
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#define zhIY CPU->IY.B.H
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#define pzSP &(CPU->SP)
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#define zSP CPU->SP.W
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#define zlSP CPU->SP.B.L
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#define zhSP CPU->SP.B.H
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#define zRealPC (PC - CPU->BasePC)
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#define zPC PC
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#define zI CPU->I
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#define zIM CPU->IM
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#define zwR CPU->R.W
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#define zR1 CPU->R.B.L
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#define zR2 CPU->R.B.H
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#define zR zR1
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#define zIFF CPU->IFF.W
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#define zIFF1 CPU->IFF.B.L
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#define zIFF2 CPU->IFF.B.H
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#define CZ80_SF_SFT 7
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#define CZ80_ZF_SFT 6
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#define CZ80_YF_SFT 5
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#define CZ80_HF_SFT 4
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#define CZ80_XF_SFT 3
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#define CZ80_PF_SFT 2
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#define CZ80_VF_SFT 2
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#define CZ80_NF_SFT 1
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#define CZ80_CF_SFT 0
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#define CZ80_SF (1 << CZ80_SF_SFT)
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#define CZ80_ZF (1 << CZ80_ZF_SFT)
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#define CZ80_YF (1 << CZ80_YF_SFT)
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#define CZ80_HF (1 << CZ80_HF_SFT)
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#define CZ80_XF (1 << CZ80_XF_SFT)
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#define CZ80_PF (1 << CZ80_PF_SFT)
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#define CZ80_VF (1 << CZ80_VF_SFT)
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#define CZ80_NF (1 << CZ80_NF_SFT)
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#define CZ80_CF (1 << CZ80_CF_SFT)
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#define CZ80_IFF_SFT CZ80_PF_SFT
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#define CZ80_IFF CZ80_PF
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#ifndef IRQ_LINE_STATE
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#define IRQ_LINE_STATE
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#define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */
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#define ASSERT_LINE 1 /* assert an interrupt immediately */
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#define HOLD_LINE 2 /* hold interrupt line until acknowledged */
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#define PULSE_LINE 3 /* pulse interrupt line for one instruction */
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#define IRQ_LINE_NMI 127 /* IRQ line for NMIs */
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#endif
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enum
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{
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CZ80_PC = 1,
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CZ80_SP,
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CZ80_AF,
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CZ80_BC,
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CZ80_DE,
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CZ80_HL,
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CZ80_IX,
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CZ80_IY,
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CZ80_AF2,
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CZ80_BC2,
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CZ80_DE2,
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CZ80_HL2,
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CZ80_R,
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CZ80_I,
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CZ80_IM,
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CZ80_IFF1,
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CZ80_IFF2,
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CZ80_HALT,
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CZ80_IRQ
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};
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typedef union
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{
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struct
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{
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#if CZ80_LITTLE_ENDIAN
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UINT8 L;
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UINT8 H;
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#else
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UINT8 H;
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UINT8 L;
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#endif
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} B;
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UINT16 W;
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} union16;
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typedef struct cz80_t
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{
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union
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{
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UINT8 r8[8];
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union16 r16[4];
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struct
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{
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union16 BC;
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union16 DE;
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union16 HL;
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union16 AF;
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};
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};
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union16 IX;
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union16 IY;
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union16 SP;
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UINT32 PC;
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union16 BC2;
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union16 DE2;
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union16 HL2;
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union16 AF2;
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union16 R;
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union16 IFF;
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UINT8 I;
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UINT8 IM;
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UINT8 HaltState;
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UINT8 dummy;
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INT32 IRQLine;
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INT32 IRQState;
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INT32 ICount;
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INT32 ExtraCycles;
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UINT32 BasePC;
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UINT32 Fetch[CZ80_FETCH_BANK];
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#if CZ80_ENCRYPTED_ROM
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INT32 OPBase;
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INT32 OPFetch[CZ80_FETCH_BANK];
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#endif
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UINT8 *pzR8[8];
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union16 *pzR16[4];
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UINT8 (*Read_Byte)(UINT32 address);
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void (*Write_Byte)(UINT32 address, UINT8 data);
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UINT8 (*IN_Port)(UINT16 port);
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void (*OUT_Port)(UINT16 port, UINT8 value);
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INT32 (*Interrupt_Callback)(INT32 irqline);
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} cz80_struc;
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/*************************/
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/* Publics Z80 variables */
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/*************************/
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extern cz80_struc CZ80;
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/*************************/
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/* Publics Z80 functions */
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/*************************/
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void Cz80_Init(cz80_struc *CPU);
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void Cz80_Reset(cz80_struc *CPU);
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INT32 Cz80_Exec(cz80_struc *CPU, INT32 cycles);
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void Cz80_Set_IRQ(cz80_struc *CPU, INT32 line, INT32 state);
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UINT32 Cz80_Get_Reg(cz80_struc *CPU, INT32 regnum);
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void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 value);
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void Cz80_Set_Fetch(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 fetch_adr);
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#if CZ80_ENCRYPTED_ROM
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void Cz80_Set_Encrypt_Range(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 decrypted_rom);
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#endif
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void Cz80_Set_ReadB(cz80_struc *CPU, UINT8 (*Func)(UINT32 address));
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void Cz80_Set_WriteB(cz80_struc *CPU, void (*Func)(UINT32 address, UINT8 data));
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void Cz80_Set_INPort(cz80_struc *CPU, UINT8 (*Func)(UINT16 port));
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void Cz80_Set_OUTPort(cz80_struc *CPU, void (*Func)(UINT16 port, UINT8 value));
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void Cz80_Set_IRQ_Callback(cz80_struc *CPU, INT32 (*Func)(INT32 irqline));
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#ifdef __cplusplus
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};
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#endif
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#endif /* CZ80_H */
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