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https://github.com/RaySollium99/picodrive.git
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272 lines
7.4 KiB
ArmAsm
272 lines
7.4 KiB
ArmAsm
@ vim:filetype=armasm:
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.equ mmsp2_regs, (0xc0000000-0x02000000) @ assume we live @ 0x2000000 bank
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.equ shared_ctl, 0x00200000 @ this is where shared_ctl struncture is located
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@ exception table:
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.global code940
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code940:
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b .b_reset @ reset
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b .b_undef @ undefined instructions
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b .b_swi @ software interrupt
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b .b_pabort @ prefetch abort
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b .b_dabort @ data abort
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b .b_reserved @ reserved
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b .b_irq @ IRQ
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b .b_fiq @ FIQ
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@ test
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.b_reset:
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mov r12, #0
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b .Begin
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.b_undef:
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mov r12, #1
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b .Begin
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.b_swi:
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mov r12, #2
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b .Begin
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.b_pabort:
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mov r12, #3
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b .Begin
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.b_dabort:
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mov r12, #4
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b .Begin
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.b_reserved:
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mov r12, #5
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b .Begin
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.b_irq:
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mov sp, #0x100000 @ reset stack
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sub sp, sp, #4
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mov r0, #shared_ctl @ remember where we were when interrupt happened
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add r0, r0, #0x20
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str lr, [r0]
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mov r0, #shared_ctl @ increment exception counter (for debug)
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add r0, r0, #(6*4)
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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bl Main940
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@ we should never get here
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b .b_reserved
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.b_fiq:
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mov r12, #7
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b .Begin
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.Begin:
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mov sp, #0x100000 @ set the stack top (1M)
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sub sp, sp, #4 @ minus 4
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@ set up memory region 0 -- the whole 4GB address space
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mov r0, #(0x1f<<1)|1 @ region data
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mcr p15, 0, r0, c6, c0, 0 @ opcode2 ~ data/instr
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mcr p15, 0, r0, c6, c0, 1
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@ set up region 1 which is the first 2 megabytes.
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mov r0, #(0x14<<1)|1 @ region data
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mcr p15, 0, r0, c6, c1, 0
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mcr p15, 0, r0, c6, c1, 1
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@ set up region 2: 64k 0x200000-0x210000
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mov r0, #(0x0f<<1)|1
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orr r0, r0, #0x200000
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mcr p15, 0, r0, c6, c2, 0
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mcr p15, 0, r0, c6, c2, 1
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@ set up region 3: 64k 0xbe000000-0xbe010000 (hw control registers)
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mov r0, #(0x0f<<1)|1
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orr r0, r0, #mmsp2_regs
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mcr p15, 0, r0, c6, c3, 0
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mcr p15, 0, r0, c6, c3, 1
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@ set up region 4: 16M 0x01000000-0x02000000 (mp3 area)
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mov r0, #(0x17<<1)|1
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orr r0, r0, #0x01000000
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mcr p15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c4, 1
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@ region 5: 4K 0x00000000-0x00001000 (boot code protection region)
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mov r0, #(0x0b<<1)|1
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mcr p15, 0, r0, c6, c5, 0
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mcr p15, 0, r0, c6, c5, 1
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@ set regions 1, 4 and 5 to be cacheable (so the first 2M and mp3 area will be cacheable)
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mov r0, #(1<<1)|(1<<4)|(1<<5)
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r0, c2, c0, 1
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@ set region 1 to be bufferable too (only data)
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mov r0, #(1<<1)
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mcr p15, 0, r0, c3, c0, 0
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@ set access protection
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@ data: [no, full, full, full, full, no access] for regions [5 4 3 2 1 0]
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mov r0, #(0<<10)|(3<<8)|(3<<6)|(3<<4)|(3<<2)|(0)
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mcr p15, 0, r0, c5, c0, 0
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@ instructions: [full, no access, no, no, full, no]
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mov r0, #(0<< 6)|(0<<4)|(3<<2)|(0)
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orr r0, r0, #(3<<10)|(0<<8)
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mcr p15, 0, r0, c5, c0, 1
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mrc p15, 0, r0, c1, c0, 0 @ fetch current control reg
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orr r0, r0, #1 @ 0x00000001: enable protection unit
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orr r0, r0, #4 @ 0x00000004: enable D cache
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orr r0, r0, #0x1000 @ 0x00001000: enable I cache
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@ bic r0, r0, #0xC0000000
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@ orr r0, r0, #0x40000000 @ 0x40000000: synchronous, faster?
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orr r0, r0, #0xC0000000 @ 0xC0000000: async
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mcr p15, 0, r0, c1, c0, 0 @ set control reg
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@ flush (invalidate) the cache (just in case)
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mov r0, #0
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mcr p15, 0, r0, c7, c6, 0
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@ remember which exception vector we came from (increment counter for debug)
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mov r0, #shared_ctl
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add r0, r0, r12, lsl #2
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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@ remember last lr (for debug)
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mov r0, #shared_ctl
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add r0, r0, #0x20
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str lr, [r0]
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@ ready to take first job-interrupt
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wait_for_irq:
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mrs r0, cpsr
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bic r0, r0, #0x80
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msr cpsr_c, r0 @ enable interrupts
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 4 @ wait for IRQ
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@ mcr p15, 0, r0, c15, c8, 2
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nop
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nop
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b .b_reserved
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@ next job getter
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.global wait_get_job @ int oldjob
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wait_get_job:
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mov r3, #mmsp2_regs
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orr r2, r3, #0x3B00
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orr r2, r2, #0x0046 @ DUALPEND940 register
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ldrh r12,[r2]
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tst r0, r0
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beq wgj_no_old
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sub r0, r0, #1
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mov r1, #1
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mov r1, r1, lsl r0
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strh r1, [r2] @ clear finished job's pending bit
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bic r12,r12,r1
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wgj_no_old:
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tst r12,r12
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beq wgj_no_jobs
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mov r0, #0
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wgj_loop:
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add r0, r0, #1
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movs r12,r12,lsr #1
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bxcs lr
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b wgj_loop
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wgj_no_jobs:
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mvn r0, #0
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orr r2, r3, #0x4500
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str r0, [r2] @ clear all pending interrupts in irq controller's SRCPND register
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orr r2, r2, #0x0010
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str r0, [r2] @ clear all pending interrupts in irq controller's INTPND register
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b wait_for_irq
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.pool
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@ some asm utils are also defined here:
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.global spend_cycles @ c
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spend_cycles:
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mov r0, r0, lsr #2 @ 4 cycles/iteration
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sub r0, r0, #2 @ entry/exit/init
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.sc_loop:
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subs r0, r0, #1
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bpl .sc_loop
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bx lr
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@ clean-flush function from ARM940T technical reference manual
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.global dcache_clean_flush
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dcache_clean_flush:
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mov r1, #0 @ init line counter
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ccf_outer_loop:
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mov r0, #0 @ segment counter
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ccf_inner_loop:
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orr r2, r1, r0 @ make segment and line address
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mcr p15, 0, r2, c7, c14, 2 @ clean and flush that line
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add r0, r0, #0x10 @ incremet segment counter
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cmp r0, #0x40 @ complete all 4 segments?
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bne ccf_inner_loop
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add r1, r1, #0x04000000 @ increment line counter
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cmp r1, #0 @ complete all lines?
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bne ccf_outer_loop
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bx lr
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@ clean-only version
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.global dcache_clean
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dcache_clean:
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mov r1, #0 @ init line counter
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cf_outer_loop:
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mov r0, #0 @ segment counter
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cf_inner_loop:
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orr r2, r1, r0 @ make segment and line address
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mcr p15, 0, r2, c7, c10, 2 @ clean that line
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add r0, r0, #0x10 @ incremet segment counter
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cmp r0, #0x40 @ complete all 4 segments?
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bne cf_inner_loop
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add r1, r1, #0x04000000 @ increment line counter
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cmp r1, #0 @ complete all lines?
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bne cf_outer_loop
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bx lr
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@ drain write buffer
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.global drain_wb
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drain_wb:
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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.global set_if_not_changed @ int *val, int oldval, int newval
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set_if_not_changed:
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swp r3, r2, [r0]
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cmp r1, r3
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bxeq lr
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strne r3, [r0] @ restore value which was changed there by other core
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bx lr
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@ pad the protected region.
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.rept 1024
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.long 0
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.endr
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