mirror of
https://github.com/RaySollium99/picodrive.git
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156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/* cpuctrl for GP2X
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Copyright (C) 2005 Hermes/PS2Reality
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the gamma-routine was provided by theoddbot
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parts (c) Rlyehs Work & (C) 2006 god_at_hell
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <sys/mman.h>
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#include <math.h>
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#include "cpuctrl.h"
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/* system registers */
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static struct
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{
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unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,MEMTIMEX0,MEMTIMEX1;
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}
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system_reg;
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static unsigned short dispclockdiv;
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static volatile unsigned short *MEM_REG;
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#define SYS_CLK_FREQ 7372800
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void cpuctrl_init(void)
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{
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extern volatile unsigned short *gp2x_memregs; /* from minimal library rlyeh */
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MEM_REG=&gp2x_memregs[0];
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system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
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system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
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system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
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system_reg.DUALINT920=MEM_REG[0x3B40>>1];
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system_reg.DUALINT940=MEM_REG[0x3B42>>1];
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system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
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system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
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system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
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dispclockdiv=MEM_REG[0x924>>1];
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}
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void cpuctrl_deinit(void)
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{
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MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
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MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
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MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
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MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
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MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
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MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
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MEM_REG[0x924>>1]=dispclockdiv;
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MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
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MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1 /*| 0x9000*/;
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}
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void set_display_clock_div(unsigned div)
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{
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div=((div & 63) | 64)<<8;
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MEM_REG[0x924>>1]=(MEM_REG[0x924>>1] & ~(255<<8)) | div;
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}
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void set_FCLK(unsigned MHZ)
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{
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unsigned v;
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unsigned mdiv,pdiv=3,scale=0;
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MHZ*=1000000;
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mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
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mdiv=((mdiv-8)<<8) & 0xff00;
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pdiv=((pdiv-2)<<2) & 0xfc;
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scale&=3;
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v=mdiv | pdiv | scale;
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MEM_REG[0x910>>1]=v;
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}
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void set_920_Div(unsigned short div)
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{
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unsigned short v;
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v = MEM_REG[0x91c>>1] & (~0x3);
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MEM_REG[0x91c>>1] = (div & 0x7) | v;
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}
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void set_DCLK_Div( unsigned short div )
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{
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unsigned short v;
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v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)) );
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MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
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}
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/*
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void Disable_940(void)
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{
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MEM_REG[0x3B42>>1];
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MEM_REG[0x3B42>>1]=0;
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MEM_REG[0x3B46>>1]=0xffff;
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MEM_REG[0x3B48>>1]|= (1 << 7);
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MEM_REG[0x904>>1]&=0xfffe;
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}
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*/
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void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD)
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{
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tRC -= 1; tRAS -= 1; tWR -= 1; tMRD -= 1; tRFC -= 1; tRP -= 1; tRCD -= 1; // ???
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MEM_REG[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF);
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MEM_REG[0x3804>>1] = /*0x9000 |*/ ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF);
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}
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/*
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void gp2x_video_wait_vsync(void)
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{
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MEM_REG[0x2846>>1]=(MEM_REG[0x2846>>1] | 0x20) & ~2;
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while(!(MEM_REG[0x2846>>1] & 2));
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}
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*/
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void set_gamma(int g100)
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{
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float gamma = (float) g100 / 100;
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int i;
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//printf ("set gamma = %f\r\n",gamma);
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gamma = 1/gamma;
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//enable gamma
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MEM_REG[0x2880>>1]&=~(1<<12);
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MEM_REG[0x295C>>1]=0;
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for(i=0; i<256; i++)
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{
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unsigned char g;
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unsigned short s;
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g =(unsigned char)(255.0*pow(i/255.0,gamma));
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s = (g<<8) | g;
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MEM_REG[0x295E>>1]= s;
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MEM_REG[0x295E>>1]= g;
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}
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}
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