mirror of
https://github.com/RaySollium99/picodrive.git
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f81107f590
- use consistent read tables (with write) - use sh2 ptr instead of id - place data_array/peri_regs in sh2 struct
704 lines
17 KiB
C
704 lines
17 KiB
C
/*
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* Basic macros to emit x86 instructions and some utils
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* Copyright (C) 2008,2009,2010 notaz
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*
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* note:
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* temp registers must be eax-edx due to use of SETcc and r/w 8/16.
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* note about silly things like emith_eor_r_r_r:
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* these are here because the compiler was designed
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* for ARM as it's primary target.
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*/
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#include <stdarg.h>
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enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define CONTEXT_REG xBP
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#define ICOND_JO 0x00
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#define ICOND_JNO 0x01
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#define ICOND_JB 0x02
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#define ICOND_JAE 0x03
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#define ICOND_JE 0x04
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#define ICOND_JNE 0x05
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#define ICOND_JBE 0x06
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#define ICOND_JA 0x07
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#define ICOND_JS 0x08
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#define ICOND_JNS 0x09
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#define ICOND_JL 0x0c
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#define ICOND_JGE 0x0d
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#define ICOND_JLE 0x0e
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#define ICOND_JG 0x0f
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#define IOP_JMP 0xeb
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// unified conditions (we just use rel8 jump instructions for x86)
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#define DCOND_EQ ICOND_JE
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#define DCOND_NE ICOND_JNE
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#define DCOND_MI ICOND_JS // MInus
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#define DCOND_PL ICOND_JNS // PLus or zero
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#define DCOND_HI ICOND_JA // higher (unsigned)
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#define DCOND_HS ICOND_JAE // higher || same (unsigned)
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#define DCOND_LO ICOND_JB // lower (unsigned)
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#define DCOND_LS ICOND_JBE // lower || same (unsigned)
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#define DCOND_GE ICOND_JGE // greater || equal (signed)
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#define DCOND_GT ICOND_JG // greater (signed)
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#define DCOND_LE ICOND_JLE // less || equal (signed)
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#define DCOND_LT ICOND_JL // less (signed)
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#define DCOND_VS ICOND_JO // oVerflow Set
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#define DCOND_VC ICOND_JNO // oVerflow Clear
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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#define EMIT(val, type) { \
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EMIT_PTR(tcache_ptr, val, type); \
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tcache_ptr += sizeof(type); \
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}
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#define EMIT_OP(op) { \
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COUNT_OP; \
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EMIT(op, u8); \
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}
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#define EMIT_MODRM(mod,r,rm) \
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EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
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#define EMIT_SIB(scale,index,base) \
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EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
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#define EMIT_OP_MODRM(op,mod,r,rm) do { \
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EMIT_OP(op); \
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EMIT_MODRM(mod, r, rm); \
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} while (0)
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#define JMP8_POS(ptr) \
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ptr = tcache_ptr; \
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tcache_ptr += 2
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#define JMP8_EMIT(op, ptr) \
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EMIT_PTR(ptr, 0x70|(op), u8); \
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EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
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#define JMP8_EMIT_NC(ptr) \
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EMIT_PTR(ptr, IOP_JMP, u8); \
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EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
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// _r_r
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#define emith_move_r_r(dst, src) \
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EMIT_OP_MODRM(0x8b, 3, dst, src)
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#define emith_add_r_r(d, s) \
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EMIT_OP_MODRM(0x01, 3, s, d)
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#define emith_sub_r_r(d, s) \
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EMIT_OP_MODRM(0x29, 3, s, d)
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#define emith_adc_r_r(d, s) \
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EMIT_OP_MODRM(0x11, 3, s, d)
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#define emith_sbc_r_r(d, s) \
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EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
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#define emith_or_r_r(d, s) \
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EMIT_OP_MODRM(0x09, 3, s, d)
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#define emith_and_r_r(d, s) \
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EMIT_OP_MODRM(0x21, 3, s, d)
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#define emith_eor_r_r(d, s) \
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EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
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#define emith_tst_r_r(d, s) \
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EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
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#define emith_cmp_r_r(d, s) \
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EMIT_OP_MODRM(0x39, 3, s, d)
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// fake teq - test equivalence - get_flags(d ^ s)
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#define emith_teq_r_r(d, s) { \
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emith_push(d); \
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emith_eor_r_r(d, s); \
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emith_pop(d); \
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}
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#define emith_mvn_r_r(d, s) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
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}
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#define emith_negc_r_r(d, s) { \
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int tmp_ = rcache_get_tmp(); \
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emith_move_r_imm(tmp_, 0); \
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emith_sbc_r_r(tmp_, s); \
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emith_move_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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#define emith_neg_r_r(d, s) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
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}
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// _r_r_r
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#define emith_add_r_r_r(d, s1, s2) { \
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if (d == s1) { \
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emith_add_r_r(d, s2); \
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} else if (d == s2) { \
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emith_add_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_add_r_r(d, s2); \
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} \
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}
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#define emith_eor_r_r_r(d, s1, s2) { \
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if (d == s1) { \
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emith_eor_r_r(d, s2); \
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} else if (d == s2) { \
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emith_eor_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_eor_r_r(d, s2); \
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} \
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}
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// _r_r_shift
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#define emith_or_r_r_lsl(d, s, lslimm) { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsl(tmp_, s, lslimm); \
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emith_or_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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// d != s
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#define emith_eor_r_r_lsr(d, s, lsrimm) { \
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emith_push(s); \
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emith_lsr(s, s, lsrimm); \
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emith_eor_r_r(d, s); \
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emith_pop(s); \
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}
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// _r_imm
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#define emith_move_r_imm(r, imm) { \
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EMIT_OP(0xb8 + (r)); \
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EMIT(imm, u32); \
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}
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#define emith_move_r_imm_s8(r, imm) \
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emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
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#define emith_arith_r_imm(op, r, imm) do { \
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EMIT_OP_MODRM(0x81, 3, op, r); \
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EMIT(imm, u32); \
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} while (0)
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#define emith_add_r_imm(r, imm) \
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emith_arith_r_imm(0, r, imm)
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#define emith_or_r_imm(r, imm) \
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emith_arith_r_imm(1, r, imm)
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#define emith_adc_r_imm(r, imm) \
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emith_arith_r_imm(2, r, imm)
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#define emith_sbc_r_imm(r, imm) \
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emith_arith_r_imm(3, r, imm) // sbb
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#define emith_and_r_imm(r, imm) \
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emith_arith_r_imm(4, r, imm)
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#define emith_sub_r_imm(r, imm) \
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emith_arith_r_imm(5, r, imm)
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#define emith_eor_r_imm(r, imm) \
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emith_arith_r_imm(6, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_arith_r_imm(7, r, imm)
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#define emith_tst_r_imm(r, imm) do { \
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EMIT_OP_MODRM(0xf7, 3, 0, r); \
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EMIT(imm, u32); \
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} while (0)
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// fake
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#define emith_bic_r_imm(r, imm) \
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emith_arith_r_imm(4, r, ~(imm))
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// fake conditionals (using SJMP instead)
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#define emith_move_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_move_r_imm(r, imm); \
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}
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#define emith_add_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_add_r_imm(r, imm); \
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}
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#define emith_sub_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_sub_r_imm(r, imm); \
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}
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_or_r_imm(r, imm)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_eor_r_imm(r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_bic_r_imm(r, imm)
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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#define emith_read_r_r_offs_c(cond, r, rs, offs) \
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emith_read_r_r_offs(r, rs, offs)
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#define emith_write_r_r_offs_c(cond, r, rs, offs) \
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emith_write_r_r_offs(r, rs, offs)
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#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
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emith_read8_r_r_offs(r, rs, offs)
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#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
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emith_write8_r_r_offs(r, rs, offs)
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#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
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emith_read16_r_r_offs(r, rs, offs)
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#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
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emith_write16_r_r_offs(r, rs, offs)
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#define emith_jump_reg_c(cond, r) \
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emith_jump_reg(r)
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#define emith_jump_ctx_c(cond, offs) \
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emith_jump_ctx(offs)
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#define emith_ret_c(cond) \
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emith_ret()
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// _r_r_imm
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#define emith_add_r_r_imm(d, s, imm) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_add_r_imm(d, imm); \
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}
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#define emith_and_r_r_imm(d, s, imm) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_and_r_imm(d, imm); \
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}
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// shift
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#define emith_shift(op, d, s, cnt) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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EMIT_OP_MODRM(0xc1, 3, op, d); \
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EMIT(cnt, u8); \
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}
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#define emith_lsl(d, s, cnt) \
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emith_shift(4, d, s, cnt)
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#define emith_lsr(d, s, cnt) \
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emith_shift(5, d, s, cnt)
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#define emith_asr(d, s, cnt) \
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emith_shift(7, d, s, cnt)
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#define emith_rol(d, s, cnt) \
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emith_shift(0, d, s, cnt)
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#define emith_ror(d, s, cnt) \
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emith_shift(1, d, s, cnt)
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#define emith_rolc(r) \
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EMIT_OP_MODRM(0xd1, 3, 2, r)
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#define emith_rorc(r) \
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EMIT_OP_MODRM(0xd1, 3, 3, r)
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// misc
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#define emith_push(r) \
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EMIT_OP(0x50 + (r))
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#define emith_push_imm(imm) { \
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EMIT_OP(0x68); \
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EMIT(imm, u32); \
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}
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#define emith_pop(r) \
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EMIT_OP(0x58 + (r))
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#define emith_neg_r(r) \
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EMIT_OP_MODRM(0xf7, 3, 3, r)
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#define emith_clear_msb(d, s, count) { \
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u32 t = (u32)-1; \
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t >>= count; \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_and_r_imm(d, t); \
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}
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#define emith_clear_msb_c(cond, d, s, count) { \
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(void)(cond); \
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emith_clear_msb(d, s, count); \
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}
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#define emith_sext(d, s, bits) { \
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emith_lsl(d, s, 32 - (bits)); \
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emith_asr(d, d, 32 - (bits)); \
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}
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#define emith_setc(r) { \
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EMIT_OP(0x0f); \
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EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
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}
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// XXX: stupid mess
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#define emith_mul_(op, dlo, dhi, s1, s2) { \
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int rmr; \
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if (dlo != xAX && dhi != xAX) \
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emith_push(xAX); \
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if (dlo != xDX && dhi != xDX) \
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emith_push(xDX); \
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if ((s1) == xAX) \
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rmr = s2; \
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else if ((s2) == xAX) \
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rmr = s1; \
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else { \
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emith_move_r_r(xAX, s1); \
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rmr = s2; \
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} \
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EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
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/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
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if (dhi != xDX && dhi != -1) \
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emith_push(xDX); \
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if (dlo != xAX) \
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emith_move_r_r(dlo, xAX); \
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if (dhi != xDX && dhi != -1) \
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emith_pop(dhi); \
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if (dlo != xDX && dhi != xDX) \
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emith_pop(xDX); \
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if (dlo != xAX && dhi != xAX) \
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emith_pop(xAX); \
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}
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#define emith_mul_u64(dlo, dhi, s1, s2) \
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emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
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#define emith_mul_s64(dlo, dhi, s1, s2) \
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emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
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#define emith_mul(d, s1, s2) \
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emith_mul_(4, d, -1, s1, s2)
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// (dlo,dhi) += signed(s1) * signed(s2)
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#define emith_mula_s64(dlo, dhi, s1, s2) { \
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emith_push(dhi); \
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emith_push(dlo); \
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emith_mul_(5, dlo, dhi, s1, s2); \
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EMIT_OP_MODRM(0x03, 0, dlo, 4); \
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EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
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EMIT_OP_MODRM(0x13, 1, dhi, 4); \
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EMIT_SIB(0, 4, 4); \
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EMIT(4, u8); /* adc dhi, [esp+4] */ \
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emith_add_r_imm(xSP, 4*2); \
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}
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// "flag" instructions are the same
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#define emith_subf_r_imm emith_sub_r_imm
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#define emith_addf_r_r emith_add_r_r
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#define emith_subf_r_r emith_sub_r_r
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#define emith_adcf_r_r emith_adc_r_r
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#define emith_sbcf_r_r emith_sbc_r_r
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#define emith_eorf_r_r emith_eor_r_r
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#define emith_negcf_r_r emith_negc_r_r
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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#define emith_asrf emith_asr
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#define emith_rolf emith_rol
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#define emith_rorf emith_ror
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#define emith_rolcf emith_rolc
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#define emith_rorcf emith_rorc
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#define emith_deref_op(op, r, rs, offs) do { \
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/* mov r <-> [ebp+#offs] */ \
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if ((offs) >= 0x80) { \
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EMIT_OP_MODRM(op, 2, r, rs); \
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EMIT(offs, u32); \
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} else { \
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EMIT_OP_MODRM(op, 1, r, rs); \
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EMIT(offs, u8); \
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} \
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} while (0)
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#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
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#define emith_read_r_r_offs(r, rs, offs) \
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emith_deref_op(0x8b, r, rs, offs)
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#define emith_write_r_r_offs(r, rs, offs) \
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emith_deref_op(0x89, r, rs, offs)
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// note: don't use prefixes on this
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#define emith_read8_r_r_offs(r, rs, offs) do { \
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int r_ = r; \
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if (!is_abcdx(r)) \
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r_ = rcache_get_tmp(); \
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emith_deref_op(0x8a, r_, rs, offs); \
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if ((r) != r_) { \
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emith_move_r_r(r, r_); \
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rcache_free_tmp(r_); \
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} \
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} while (0)
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#define emith_write8_r_r_offs(r, rs, offs) do {\
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int r_ = r; \
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if (!is_abcdx(r)) { \
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r_ = rcache_get_tmp(); \
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emith_move_r_r(r_, r); \
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} \
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emith_deref_op(0x88, r_, rs, offs); \
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if ((r) != r_) \
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rcache_free_tmp(r_); \
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} while (0)
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#define emith_read16_r_r_offs(r, rs, offs) { \
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EMIT(0x66, u8); /* operand override */ \
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emith_read_r_r_offs(r, rs, offs); \
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}
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#define emith_write16_r_r_offs(r, rs, offs) { \
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EMIT(0x66, u8); \
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emith_write_r_r_offs(r, rs, offs); \
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}
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#define emith_ctx_read(r, offs) \
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emith_read_r_r_offs(r, CONTEXT_REG, offs)
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#define emith_ctx_write(r, offs) \
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emith_write_r_r_offs(r, CONTEXT_REG, offs)
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#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
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int r_ = r, offs_ = offs, cnt_ = cnt; \
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for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
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emith_ctx_read(r_, offs_); \
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} while (0)
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#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
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int r_ = r, offs_ = offs, cnt_ = cnt; \
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for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
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emith_ctx_write(r_, offs_); \
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} while (0)
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// assumes EBX is free
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#define emith_ret_to_ctx(offs) { \
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emith_pop(xBX); \
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emith_ctx_write(xBX, offs); \
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}
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#define emith_jump(ptr) { \
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u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
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EMIT_OP(0xe9); \
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EMIT(disp, u32); \
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}
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#define emith_jump_patchable(target) \
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emith_jump(target)
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#define emith_jump_cond(cond, ptr) { \
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u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
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EMIT(0x0f, u8); \
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EMIT_OP(0x80 | (cond)); \
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EMIT(disp, u32); \
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}
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#define emith_jump_cond_patchable(cond, target) \
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emith_jump_cond(cond, target)
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#define emith_jump_patch(ptr, target) do { \
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u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
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u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
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EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
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} while (0)
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#define emith_jump_at(ptr, target) { \
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u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
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EMIT_PTR(ptr, 0xe9, u8); \
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EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
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}
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#define emith_call(ptr) { \
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u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
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EMIT_OP(0xe8); \
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EMIT(disp, u32); \
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}
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#define emith_call_cond(cond, ptr) \
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emith_call(ptr)
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#define emith_call_reg(r) \
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EMIT_OP_MODRM(0xff, 3, 2, r)
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#define emith_call_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
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EMIT(offs, u32); \
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}
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#define emith_ret() \
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EMIT_OP(0xc3)
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#define emith_jump_reg(r) \
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EMIT_OP_MODRM(0xff, 3, 4, r)
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#define emith_jump_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
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EMIT(offs, u32); \
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}
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#define emith_push_ret()
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#define emith_pop_and_ret() \
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emith_ret()
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#define EMITH_JMP_START(cond) { \
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u8 *cond_ptr; \
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JMP8_POS(cond_ptr)
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#define EMITH_JMP_END(cond) \
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JMP8_EMIT(cond, cond_ptr); \
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}
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#define EMITH_JMP3_START(cond) { \
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u8 *cond_ptr, *else_ptr; \
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JMP8_POS(cond_ptr)
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#define EMITH_JMP3_MID(cond) \
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JMP8_POS(else_ptr); \
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JMP8_EMIT(cond, cond_ptr);
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#define EMITH_JMP3_END() \
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JMP8_EMIT_NC(else_ptr); \
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}
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// "simple" jump (no more then a few insns)
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// ARM will use conditional instructions here
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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#define EMITH_SJMP3_START EMITH_JMP3_START
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#define EMITH_SJMP3_MID EMITH_JMP3_MID
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#define EMITH_SJMP3_END EMITH_JMP3_END
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#define emith_pass_arg_r(arg, reg) { \
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int rd = 7; \
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host_arg2reg(rd, arg); \
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emith_move_r_r(rd, reg); \
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}
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#define emith_pass_arg_imm(arg, imm) { \
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int rd = 7; \
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host_arg2reg(rd, arg); \
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emith_move_r_imm(rd, imm); \
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}
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#define host_instructions_updated(base, end)
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#define host_arg2reg(rd, arg) \
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switch (arg) { \
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case 0: rd = xAX; break; \
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case 1: rd = xDX; break; \
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case 2: rd = xCX; break; \
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}
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/* SH2 drc specific */
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#define emith_sh2_drc_entry() { \
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emith_push(xBX); \
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emith_push(xBP); \
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emith_push(xSI); \
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emith_push(xDI); \
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}
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#define emith_sh2_drc_exit() { \
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emith_pop(xDI); \
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emith_pop(xSI); \
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emith_pop(xBP); \
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|
emith_pop(xBX); \
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emith_ret(); \
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}
|
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// assumes EBX is free temporary
|
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#define emith_sh2_wcall(a, tab) { \
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int arg2_; \
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host_arg2reg(arg2_, 2); \
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emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
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EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
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EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
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emith_move_r_r(arg2_, CONTEXT_REG); \
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emith_jump_reg(xBX); \
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}
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#define emith_sh2_dtbf_loop() { \
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u8 *jmp0; /* negative cycles check */ \
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u8 *jmp1; /* unsinged overflow check */ \
|
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int cr, rn; \
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int tmp_ = rcache_get_tmp(); \
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cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
|
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emith_sub_r_imm(rn, 1); \
|
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emith_sub_r_imm(cr, (cycles+1) << 12); \
|
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cycles = 0; \
|
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emith_asr(tmp_, cr, 2+12); \
|
|
JMP8_POS(jmp0); /* no negative cycles */ \
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emith_move_r_imm(tmp_, 0); \
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JMP8_EMIT(ICOND_JNS, jmp0); \
|
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emith_and_r_imm(cr, 0xffe); \
|
|
emith_subf_r_r(rn, tmp_); \
|
|
JMP8_POS(jmp1); /* no overflow */ \
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|
emith_neg_r(rn); /* count left */ \
|
|
emith_lsl(rn, rn, 2+12); \
|
|
emith_or_r_r(cr, rn); \
|
|
emith_or_r_imm(cr, 1); \
|
|
emith_move_r_imm(rn, 0); \
|
|
JMP8_EMIT(ICOND_JA, jmp1); \
|
|
rcache_free_tmp(tmp_); \
|
|
}
|
|
|
|
#define emith_write_sr(sr, srcr) { \
|
|
int tmp_ = rcache_get_tmp(); \
|
|
emith_clear_msb(tmp_, srcr, 22); \
|
|
emith_bic_r_imm(sr, 0x3ff); \
|
|
emith_or_r_r(sr, tmp_); \
|
|
rcache_free_tmp(tmp_); \
|
|
}
|
|
|
|
#define emith_tpop_carry(sr, is_sub) \
|
|
emith_lsr(sr, sr, 1)
|
|
|
|
#define emith_tpush_carry(sr, is_sub) \
|
|
emith_adc_r_r(sr, sr)
|
|
|
|
/*
|
|
* if Q
|
|
* t = carry(Rn += Rm)
|
|
* else
|
|
* t = carry(Rn -= Rm)
|
|
* T ^= t
|
|
*/
|
|
#define emith_sh2_div1_step(rn, rm, sr) { \
|
|
u8 *jmp0, *jmp1; \
|
|
int tmp_ = rcache_get_tmp(); \
|
|
emith_eor_r_r(tmp_, tmp_); \
|
|
emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
|
|
JMP8_POS(jmp0); /* je do_sub */ \
|
|
emith_add_r_r(rn, rm); \
|
|
JMP8_POS(jmp1); /* jmp done */ \
|
|
JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
|
|
emith_sub_r_r(rn, rm); \
|
|
JMP8_EMIT_NC(jmp1); /* done: */ \
|
|
emith_setc(tmp_); \
|
|
EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
|
|
rcache_free_tmp(tmp_); \
|
|
}
|
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|