mirror of
https://github.com/RaySollium99/picodrive.git
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cff531af94
- PicoDrive was originally released by fDave with simple
"free for non-commercial use / For commercial use, separate licencing
terms must be obtained" license and I kept it in my releases.
- in 2011, fDave re-released his code (same that I used as base
many years ago) dual licensed with GPLv2 and MAME licenses:
https://code.google.com/p/cyclone68000/
Based on the above I now proclaim that the whole source code is licensed
under the MAME license as more elaborate form of "for non-commercial use".
If that raises any doubt, I announce that all my modifications (which
is the vast majority of code by now) is licensed under the MAME license,
as it reads in COPYING file in this commit.
This does not affect ym2612.c/sn76496.c that were MAME licensed already
from the beginning.
185 lines
4.9 KiB
ArmAsm
185 lines
4.9 KiB
ArmAsm
@*
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@* CPU scheduling code
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@* (C) notaz, 2007-2008
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@*
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@* This work is licensed under the terms of MAME license.
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@* See COPYING file in the top-level directory.
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@*
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@ SekRunPS runs PicoCpuCM68k and PicoCpuCS68k interleaved in steps of PS_STEP_M68K
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@ cycles. This is done without calling CycloneRun and jumping directly to
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@ Cyclone code to avoid pushing/popping all the registers every time.
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.equiv PS_STEP_M68K, ((488<<16)/20) @ ~24
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@ .extern is ignored by gas, we add these here just to see what we depend on.
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.extern CycloneJumpTab
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.extern CycloneDoInterrupt
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.extern PicoCpuCM68k
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.extern PicoCpuCS68k
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.extern SekCycleAim
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.extern SekCycleCnt
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.extern SekCycleAimS68k
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.extern SekCycleCntS68k
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.text
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.align 4
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.global SekRunPS @ cyc_m68k, cyc_s68k
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SekRunPS:
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stmfd sp!, {r4-r8,r10,r11,lr}
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sub sp, sp, #2*4 @ sp[0] = main_cycle_cnt, sp[4] = run_cycle_cnt
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@ override CycloneEnd for both contexts
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ldr r7, =PicoCpuCM68k
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ldr lr, =PicoCpuCS68k
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ldr r2, =CycloneEnd_M68k
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ldr r3, =CycloneEnd_S68k
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str r2, [r7,#0x98]
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str r3, [lr,#0x98]
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@ update aims
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ldr r8, =SekCycleAim
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ldr r10,=SekCycleAimS68k
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ldr r2, [r8]
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ldr r3, [r10]
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add r2, r2, r0
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add r3, r3, r1
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str r2, [r8]
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str r3, [r10]
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ldr r6, =CycloneJumpTab
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ldr r1, =SekCycleCnt
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ldr r0, =((488<<16)-PS_STEP_M68K)
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str r6, [r7,#0x54]
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str r6, [lr,#0x54] @ make copies to avoid literal pools
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@ schedule m68k for the first time..
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ldr r1, [r1]
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str r0, [sp] @ main target 'left cycle' counter
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sub r1, r2, r1
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subs r5, r1, r0, asr #16
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ble schedule_s68k @ m68k has not enough cycles
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str r5, [sp,#4] @ run_cycle_cnt
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b CycloneRunLocal
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CycloneEnd_M68k:
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ldr r3, =SekCycleCnt
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ldr r0, [sp,#4] @ run_cycle_cnt
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ldr r1, [r3]
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str r4, [r7,#0x40] ;@ Save Current PC + Memory Base
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strb r10,[r7,#0x46] ;@ Save Flags (NZCV)
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sub r0, r0, r5 @ subtract leftover cycles (which should be negative)
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add r0, r0, r1
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str r0, [r3]
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schedule_s68k:
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ldr r8, =SekCycleCntS68k
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ldr r10,=SekCycleAimS68k
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ldr r3, [sp]
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ldr r8, [r8]
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ldr r10,[r10]
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sub r0, r10, r8
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mov r2, r3
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add r3, r3, r2, asr #1
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add r3, r3, r2, asr #3 @ cycn_s68k = (cycn + cycn/2 + cycn/8)
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subs r5, r0, r3, asr #16
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ble schedule_m68k @ s68k has not enough cycles
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ldr r7, =PicoCpuCS68k
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str r5, [sp,#4] @ run_cycle_cnt
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b CycloneRunLocal
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CycloneEnd_S68k:
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ldr r3, =SekCycleCntS68k
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ldr r0, [sp,#4] @ run_cycle_cnt
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ldr r1, [r3]
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str r4, [r7,#0x40] ;@ Save Current PC + Memory Base
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strb r10,[r7,#0x46] ;@ Save Flags (NZCV)
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sub r0, r0, r5 @ subtract leftover cycles (should be negative)
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add r0, r0, r1
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str r0, [r3]
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schedule_m68k:
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ldr r1, =PS_STEP_M68K
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ldr r3, [sp] @ main_cycle_cnt
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ldr r8, =SekCycleCnt
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ldr r10,=SekCycleAim
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subs r3, r3, r1
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bmi SekRunPS_end
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ldr r8, [r8]
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ldr r10,[r10]
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str r3, [sp] @ update main_cycle_cnt
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sub r0, r10, r8
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subs r5, r0, r3, asr #16
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ble schedule_s68k @ m68k has not enough cycles
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ldr r7, =PicoCpuCM68k
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str r5, [sp,#4] @ run_cycle_cnt
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b CycloneRunLocal
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SekRunPS_end:
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ldr r7, =PicoCpuCM68k
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ldr lr, =PicoCpuCS68k
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mov r0, #0
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str r0, [r7,#0x98] @ remove CycloneEnd handler
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str r0, [lr,#0x98]
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@ return
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add sp, sp, #2*4
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ldmfd sp!, {r4-r8,r10,r11,pc}
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CycloneRunLocal:
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;@ r0-3 = Temporary registers
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ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base
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;@ r5 = Cycles
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;@ r6 = Opcode Jump table
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;@ r7 = Pointer to Cpu Context
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;@ r8 = Current Opcode
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ldrb r10,[r7,#0x46];@ r10 = Flags (NZCV)
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ldr r1,[r7,#0x44] ;@ get SR high and IRQ level
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orr r10,r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format
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;@ CheckInterrupt:
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movs r0,r1,lsr #24 ;@ Get IRQ level
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beq NoIntsLocal
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cmp r0,#6 ;@ irq>6 ?
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andle r1,r1,#7 ;@ Get interrupt mask
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cmple r0,r1 ;@ irq<=6: Is irq<=mask ?
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bgt CycloneDoInterrupt
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NoIntsLocal:
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;@ Check if our processor is in special state
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;@ and jump to opcode handler if not
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ldr r0,[r7,#0x58] ;@ state_flags
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ldrh r8,[r4],#2 ;@ Fetch first opcode
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tst r0,#0x03 ;@ special state?
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andeq r10,r10,#0xf0000000
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ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler
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CycloneSpecial2:
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tst r0,#2 ;@ tracing?
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bne CycloneDoTrace
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;@ stopped or halted
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sub r4,r4,#2
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ldr r1,[r7,#0x98]
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mov r5,#0
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bx r1
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@ vim:filetype=armasm
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