mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
d274c33b6b
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@364 be3aeb3a-fb24-0410-a615-afba39da0efa
1155 lines
26 KiB
C
1155 lines
26 KiB
C
// 187 blocks, 12072 bytes
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// 14 IRAM blocks
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#include "../../PicoInt.h"
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#include "compiler.h"
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static unsigned int *block_table[0x5090/2];
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static unsigned int *block_table_iram[15][0x800/2];
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static unsigned int *tcache_ptr = NULL;
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static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x1d7c
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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#endif
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#define EMBED_INTERPRETER
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#define ssp1601_reset ssp1601_reset_local
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#define ssp1601_run ssp1601_run_local
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#define GET_PC() rPC
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#define GET_PPC_OFFS() (GET_PC()*2 - 2)
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#define SET_PC(d) { rPC = d; } /* must return to dispatcher after this */
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//#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
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//#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
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//#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
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#include "ssp16.c"
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#include "gen_arm.c"
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// -----------------------------------------------------
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// ld d, s
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static void op00(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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PC = ((unsigned short *)(void *)&op) + 1; /* FIXME: needed for interpreter */
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if (op == 0) return; // nop
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if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
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// not sure. MAME claims that only hi word is transfered.
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read_P(); // update P
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rA32 = rP.v;
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}
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else
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{
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tmpv = REG_READ(op & 0x0f);
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REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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}
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// ld d, (ri)
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static void op01(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ld (ri), s
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static void op02(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv);
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}
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// ldi d, imm
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static void op04(unsigned int op, unsigned int imm)
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{
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REG_WRITE((op & 0xf0) >> 4, imm);
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}
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// ld d, ((ri))
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static void op05(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ldi (ri), imm
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static void op06(unsigned int op, unsigned int imm)
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{
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ptr1_write(op, imm);
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}
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// ld adr, a
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static void op07(unsigned int op, unsigned int imm)
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{
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ssp->RAM[op & 0x1ff] = rA;
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}
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// ld d, ri
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static void op09(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// ld ri, s
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static void op0a(unsigned int op, unsigned int imm)
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{
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rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4);
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}
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// ldi ri, simm (also op0d op0e op0f)
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static void op0c(unsigned int op, unsigned int imm)
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{
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rIJ[(op>>8)&7] = op;
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}
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// call cond, addr
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static void op24(unsigned int op, unsigned int imm)
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{
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int cond = 0;
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do {
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COND_CHECK
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if (cond) { int new_PC = imm; write_STACK(GET_PC()); SET_PC(new_PC); }
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}
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while (0);
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}
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// ld d, (a)
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static void op25(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv);
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}
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// bra cond, addr
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static void op26(unsigned int op, unsigned int imm)
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{
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do
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{
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int cond = 0;
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COND_CHECK
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if (cond) SET_PC(imm);
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}
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while (0);
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}
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// mod cond, op
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static void op48(unsigned int op, unsigned int imm)
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{
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do
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{
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int cond = 0;
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COND_CHECK
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if (cond) {
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switch (op & 7) {
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case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
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case 3: rA32 <<= 1; break; // shl
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case 6: rA32 = -(signed int)rA32; break; // neg
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case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
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default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
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op&7, GET_PPC_OFFS());
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}
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UPD_ACC_ZN // ?
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}
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}
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while(0);
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}
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// mpys?
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static void op1b(unsigned int op, unsigned int imm)
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{
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read_P(); // update P
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rA32 -= rP.v; // maybe only upper word?
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UPD_ACC_ZN // there checking flags after this
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// mpya (rj), (ri), b
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static void op4b(unsigned int op, unsigned int imm)
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{
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read_P(); // update P
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rA32 += rP.v; // confirmed to be 32bit
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UPD_ACC_ZN // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// mld (rj), (ri), b
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static void op5b(unsigned int op, unsigned int imm)
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{
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rA32 = 0;
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rST &= 0x0fff; // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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}
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// OP a, s
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static void op10(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv);
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}
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while(0);
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}
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static void op30(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv);
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}
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while(0);
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}
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static void op40(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv);
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}
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while(0);
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}
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static void op50(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv);
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}
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while(0);
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}
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static void op60(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv);
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}
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while(0);
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}
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static void op70(unsigned int op, unsigned int imm)
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{
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do
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{
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unsigned int tmpv;
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OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv);
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}
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while(0);
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}
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// OP a, (ri)
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static void op11(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_SUBA(tmpv);
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}
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static void op31(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_CMPA(tmpv);
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}
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static void op41(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ADDA(tmpv);
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}
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static void op51(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ANDA(tmpv);
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}
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static void op61(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_ORA (tmpv);
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}
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static void op71(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr1_read(op); OP_EORA(tmpv);
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}
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// OP a, adr
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static void op03(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv);
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}
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static void op13(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv);
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}
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static void op33(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv);
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}
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static void op43(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv);
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}
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static void op53(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv);
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}
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static void op63(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv);
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}
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static void op73(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv);
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}
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// OP a, imm
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static void op14(unsigned int op, unsigned int imm)
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{
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OP_SUBA(imm);
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}
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static void op34(unsigned int op, unsigned int imm)
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{
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OP_CMPA(imm);
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}
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static void op44(unsigned int op, unsigned int imm)
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{
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OP_ADDA(imm);
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}
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static void op54(unsigned int op, unsigned int imm)
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{
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OP_ANDA(imm);
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}
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static void op64(unsigned int op, unsigned int imm)
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{
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OP_ORA (imm);
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}
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static void op74(unsigned int op, unsigned int imm)
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{
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OP_EORA(imm);
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}
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// OP a, ((ri))
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static void op15(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_SUBA(tmpv);
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}
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static void op35(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_CMPA(tmpv);
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}
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static void op45(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ADDA(tmpv);
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}
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static void op55(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ANDA(tmpv);
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}
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static void op65(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_ORA (tmpv);
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}
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static void op75(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = ptr2_read(op); OP_EORA(tmpv);
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}
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// OP a, ri
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static void op19(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_SUBA(tmpv);
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}
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static void op39(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_CMPA(tmpv);
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}
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static void op49(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ADDA(tmpv);
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}
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static void op59(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ANDA(tmpv);
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}
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static void op69(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_ORA (tmpv);
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}
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static void op79(unsigned int op, unsigned int imm)
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{
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unsigned int tmpv;
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tmpv = rIJ[IJind]; OP_EORA(tmpv);
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}
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// OP simm
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static void op1c(unsigned int op, unsigned int imm)
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{
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OP_SUBA(op & 0xff);
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}
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static void op3c(unsigned int op, unsigned int imm)
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{
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OP_CMPA(op & 0xff);
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}
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static void op4c(unsigned int op, unsigned int imm)
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{
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OP_ADDA(op & 0xff);
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}
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static void op5c(unsigned int op, unsigned int imm)
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{
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OP_ANDA(op & 0xff);
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}
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static void op6c(unsigned int op, unsigned int imm)
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{
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OP_ORA (op & 0xff);
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}
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static void op7c(unsigned int op, unsigned int imm)
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{
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OP_EORA(op & 0xff);
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}
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typedef void (in_func)(unsigned int op, unsigned int imm);
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static in_func *in_funcs[0x80] =
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{
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op00, op01, op02, op03, op04, op05, op06, op07,
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NULL, op09, op0a, NULL, op0c, op0c, op0c, op0c,
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op10, op11, NULL, op13, op14, op15, NULL, NULL,
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NULL, op19, NULL, op1b, op1c, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, op24, op25, op26, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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op30, op31, NULL, op33, op34, op35, NULL, NULL,
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NULL, op39, NULL, NULL, op3c, NULL, NULL, NULL,
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op40, op41, NULL, op43, op44, op45, NULL, NULL,
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op48, op49, NULL, op4b, op4c, NULL, NULL, NULL,
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op50, op51, NULL, op53, op54, op55, NULL, NULL,
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NULL, op59, NULL, op5b, op5c, NULL, NULL, NULL,
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op60, op61, NULL, op63, op64, op65, NULL, NULL,
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NULL, op69, NULL, NULL, op6c, NULL, NULL, NULL,
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op70, op71, NULL, op73, op74, op75, NULL, NULL,
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NULL, op79, NULL, NULL, op7c, NULL, NULL, NULL,
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};
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// -----------------------------------------------------
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static unsigned char iram_context_map[] =
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{
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0, 0, 0, 0, 1, 0, 0, 0, // 04
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0, 0, 0, 0, 0, 0, 2, 0, // 0e
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0, 0, 0, 0, 0, 3, 0, 4, // 15 17
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5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
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8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0,11, 0, 0,12, 0, 0, // 32 35
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13,14, 0, 0, 0, 0, 0, 0 // 38 39
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};
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static int get_iram_context(void)
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{
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unsigned char *ir = (unsigned char *)svp->iram_rom;
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int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
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val1 = iram_context_map[(val>>1)&0x3f];
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if (val1 == 0) {
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printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
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//debug_dump2file(name, svp->iram_rom, 0x800);
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exit(1);
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}
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// elprintf(EL_ANOMALY, "iram_context: %02i", val1);
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return val1;
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}
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// -----------------------------------------------------
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/*
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enum {
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SSP_GR0, SSP_X, SSP_Y, SSP_A,
|
|
SSP_ST, SSP_STACK, SSP_PC, SSP_P,
|
|
SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
|
|
SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
|
|
};
|
|
*/
|
|
/* regs with known values */
|
|
static struct
|
|
{
|
|
ssp_reg_t gr[8];
|
|
unsigned char r[8];
|
|
} const_regs;
|
|
|
|
#define CRREG_X (1 << SSP_X)
|
|
#define CRREG_Y (1 << SSP_Y)
|
|
#define CRREG_A (1 << SSP_A) /* AH only */
|
|
#define CRREG_ST (1 << SSP_ST)
|
|
#define CRREG_STACK (1 << SSP_STACK)
|
|
#define CRREG_PC (1 << SSP_PC)
|
|
#define CRREG_P (1 << SSP_P)
|
|
#define CRREG_PR0 (1 << 8)
|
|
#define CRREG_PR4 (1 << 12)
|
|
#define CRREG_AL (1 << 16)
|
|
|
|
static u32 const_regb = 0; /* bitfield of known register values */
|
|
static u32 dirty_regb = 0; /* known vals, which need to be flushed (only P, r0-r7) */
|
|
|
|
/* known values of host regs.
|
|
* -1 - unknown
|
|
* 000000-00ffff - 16bit value
|
|
* 100000-10ffff - base reg (r7) + 16bit val
|
|
* 0r0000 - means reg (low) eq gr[r].h
|
|
*/
|
|
static int hostreg_r[4];
|
|
|
|
static void hostreg_clear(void)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 4; i++)
|
|
hostreg_r[i] = -1;
|
|
}
|
|
|
|
/*static*/ void hostreg_ah_changed(void)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 4; i++)
|
|
if (hostreg_r[i] == (SSP_A<<16)) hostreg_r[i] = -1;
|
|
}
|
|
|
|
|
|
#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
|
|
|
|
/* load 16bit val into host reg r0-r3. Nothing is trashed */
|
|
static void tr_mov16(int r, int val)
|
|
{
|
|
if (hostreg_r[r] != val) {
|
|
emit_mov_const(r, val);
|
|
hostreg_r[r] = val;
|
|
}
|
|
}
|
|
|
|
/* update P, if needed. Trashes r1 */
|
|
static void tr_flush_dirty_P(void)
|
|
{
|
|
// TODO: const regs
|
|
if (!(dirty_regb & CRREG_P)) return;
|
|
EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
|
|
EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16
|
|
EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15
|
|
EOP_MUL(10, 1, 10); // mul r10, r1, r10
|
|
dirty_regb &= ~CRREG_P;
|
|
}
|
|
|
|
/* write dirty r0-r7 to host regs. Nothing is trashed */
|
|
static void tr_flush_dirty_pr(void)
|
|
{
|
|
int i, ror = 0, reg;
|
|
dirty_regb >>= 8;
|
|
/* r0-r7 */
|
|
for (i = 0; dirty_regb && i < 8; i++, dirty_regb >>= 1)
|
|
{
|
|
if (!(dirty_regb&1)) continue;
|
|
switch (i&3) {
|
|
case 0: ror = 0; break;
|
|
case 1: ror = 24/2; break;
|
|
case 2: ror = 16/2; break;
|
|
}
|
|
reg = (i < 4) ? 8 : 9;
|
|
EOP_BIC_IMM(reg,reg,ror,0xff);
|
|
if (const_regs.r[i] != 0)
|
|
EOP_ORR_IMM(reg,reg,ror,const_regs.r[i]);
|
|
}
|
|
}
|
|
|
|
/* read bank word to r0 (MSW may contain trash). Thrashes r1. */
|
|
static void tr_bank_read(int addr) /* word addr 0-0x1ff */
|
|
{
|
|
if (addr&1) {
|
|
int breg = 7;
|
|
if (addr > 0x7f) {
|
|
if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
|
|
EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
|
|
hostreg_r[1] = 0x100000|((addr&0x180)<<1);
|
|
}
|
|
breg = 1;
|
|
}
|
|
EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
|
|
} else {
|
|
EOP_LDR_IMM(0,7,(addr&0x1ff)<<1); // ldr r0, [r1, (op&0x1ff)<<1]
|
|
}
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
/* write r0 to bank. Trashes r1. */
|
|
static void tr_bank_write(int addr)
|
|
{
|
|
int breg = 7;
|
|
if (addr > 0x7f) {
|
|
if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
|
|
EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
|
|
hostreg_r[1] = 0x100000|((addr&0x180)<<1);
|
|
}
|
|
breg = 1;
|
|
}
|
|
EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
|
|
}
|
|
|
|
/* handle RAM bank pointer modifiers. Nothing is trashed. */
|
|
static void tr_ptrr_mod(int r, int mod, int need_modulo)
|
|
{
|
|
int modulo = -1, modulo_shift = -1; /* unknown */
|
|
|
|
if (mod == 0) return;
|
|
|
|
if (!need_modulo || mod == 1) // +!
|
|
modulo_shift = 8;
|
|
else if (need_modulo && (const_regb & CRREG_ST)) {
|
|
modulo_shift = const_regs.gr[SSP_ST].h & 7;
|
|
if (modulo_shift == 0) modulo_shift = 8;
|
|
}
|
|
|
|
if (mod > 1 && modulo_shift == -1) { printf("need var modulo\n"); exit(1); }
|
|
modulo = (1 << modulo_shift) - 1;
|
|
|
|
if (const_regb & (1 << (r + 8))) {
|
|
if (mod == 2)
|
|
const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] - 1) & modulo);
|
|
else const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] + 1) & modulo);
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
|
|
EOP_MOV_REG_ROR(reg,reg,ror);
|
|
// {add|sub} reg, reg, #1<<shift
|
|
EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
|
|
EOP_MOV_REG_ROR(reg,reg,32-ror);
|
|
}
|
|
}
|
|
|
|
// SSP_GR0, SSP_X, SSP_Y, SSP_A,
|
|
// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
|
|
//@ r4: XXYY
|
|
//@ r5: A
|
|
//@ r6: STACK and emu flags
|
|
//@ r7: SSP context
|
|
//@ r10: P
|
|
|
|
static void tr_GR0_to_r0(void)
|
|
{
|
|
tr_mov16(0, 0xffff);
|
|
}
|
|
|
|
static void tr_X_to_r0(void)
|
|
{
|
|
if (hostreg_r[0] != (SSP_X<<16)) {
|
|
EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
|
|
hostreg_r[0] = SSP_X<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_Y_to_r0(void)
|
|
{
|
|
// TODO..
|
|
if (hostreg_r[0] != (SSP_Y<<16)) {
|
|
EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
|
|
hostreg_r[0] = SSP_Y<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_A_to_r0(void)
|
|
{
|
|
if (hostreg_r[0] != (SSP_A<<16)) {
|
|
EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
|
|
hostreg_r[0] = SSP_A<<16;
|
|
}
|
|
}
|
|
|
|
static void tr_ST_to_r0(void)
|
|
{
|
|
// VR doesn't need much accuracy here..
|
|
EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
|
|
EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
static void tr_STACK_to_r0(void)
|
|
{
|
|
// 448
|
|
EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
|
|
EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
|
|
EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
|
|
EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
|
|
EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_PC_to_r0(void)
|
|
{
|
|
tr_mov16(0, const_regs.gr[SSP_PC].h);
|
|
}
|
|
|
|
static void tr_P_to_r0(void)
|
|
{
|
|
tr_flush_dirty_P();
|
|
EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
|
|
hostreg_r[0] = -1;
|
|
}
|
|
|
|
typedef void (tr_read_func)(void);
|
|
|
|
static tr_read_func *tr_read_funcs[8] =
|
|
{
|
|
tr_GR0_to_r0,
|
|
tr_X_to_r0,
|
|
tr_Y_to_r0,
|
|
tr_A_to_r0,
|
|
tr_ST_to_r0,
|
|
tr_STACK_to_r0,
|
|
tr_PC_to_r0,
|
|
tr_P_to_r0
|
|
};
|
|
|
|
|
|
// write r0 to general reg handlers. Trashes r1
|
|
static void tr_unhandled(void)
|
|
{
|
|
printf("unhandled @ %04x\n", const_regs.gr[SSP_PC].h<<1);
|
|
exit(1);
|
|
}
|
|
|
|
static void tr_r0_to_GR0(void)
|
|
{
|
|
// do nothing
|
|
}
|
|
|
|
static void tr_r0_to_X(void)
|
|
{
|
|
EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
|
|
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
|
|
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
|
|
dirty_regb |= CRREG_P; // touching X or Y makes P dirty.
|
|
}
|
|
|
|
static void tr_r0_to_Y(void)
|
|
{
|
|
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
|
|
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
|
|
EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
|
|
dirty_regb |= CRREG_P;
|
|
}
|
|
|
|
static void tr_r0_to_A(void)
|
|
{
|
|
EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
|
|
EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
|
|
EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
|
|
}
|
|
|
|
static void tr_r0_to_ST(void)
|
|
{
|
|
// VR doesn't need much accuracy here..
|
|
EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
|
|
EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
|
|
EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_r0_to_STACK(void)
|
|
{
|
|
// 448
|
|
EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
|
|
EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
|
|
EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
|
|
EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
|
|
EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
static void tr_r0_to_PC(void)
|
|
{
|
|
EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
|
|
EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
|
|
hostreg_r[1] = -1;
|
|
}
|
|
|
|
typedef void (tr_write_func)(void);
|
|
|
|
static tr_write_func *tr_write_funcs[8] =
|
|
{
|
|
tr_r0_to_GR0,
|
|
tr_r0_to_X,
|
|
tr_r0_to_Y,
|
|
tr_r0_to_A,
|
|
tr_r0_to_ST,
|
|
tr_r0_to_STACK,
|
|
tr_r0_to_PC,
|
|
tr_unhandled
|
|
};
|
|
|
|
|
|
static int translate_op(unsigned int op, int *pc, int imm)
|
|
{
|
|
u32 tmpv, tmpv2;
|
|
int ret = 0;
|
|
const_regs.gr[SSP_PC].h = *pc;
|
|
|
|
switch (op >> 9)
|
|
{
|
|
// ld d, s
|
|
case 0x00:
|
|
if (op == 0) { ret++; break; } // nop
|
|
tmpv = op & 0xf; // src
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO
|
|
if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
|
|
tr_flush_dirty_P();
|
|
EOP_MOV_REG_SIMPLE(5, 10);
|
|
const_regb &= ~(CRREG_A|CRREG_AL);
|
|
ret++; break;
|
|
}
|
|
tr_read_funcs[tmpv]();
|
|
tr_write_funcs[tmpv2]();
|
|
if (const_regb & (1 << tmpv)) {
|
|
const_regs.gr[tmpv2].h = const_regs.gr[tmpv].h;
|
|
const_regb |= 1 << tmpv2;
|
|
} else
|
|
const_regb &= ~(1 << tmpv2);
|
|
ret++; break;
|
|
|
|
// ld a, adr
|
|
case 0x03:
|
|
tr_bank_read(op&0x1ff);
|
|
tr_r0_to_A();
|
|
const_regb &= ~CRREG_A;
|
|
hostreg_r[0] = SSP_A<<16;
|
|
ret++; break;
|
|
|
|
// ldi d, imm
|
|
case 0x04:
|
|
tmpv = (op & 0xf0) >> 4;
|
|
if (tmpv < 8)
|
|
{
|
|
tr_mov16(0, imm);
|
|
tr_write_funcs[tmpv]();
|
|
const_regs.gr[tmpv].h = imm;
|
|
const_regb |= 1 << tmpv;
|
|
ret++; break;
|
|
}
|
|
else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
|
|
{
|
|
// programming PMC..
|
|
(*pc)++;
|
|
tmpv = imm | (PROGRAM((*pc)++) << 16);
|
|
emit_mov_const(0, tmpv);
|
|
EOP_LDR_IMM(1,7,0x484); // ldr r0, [r7, #0x484] // emu_status
|
|
EOP_STR_IMM(0,7,0x400+14*4); // PMC
|
|
// reads on fe06, fe08; next op is ld -,
|
|
if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
|
|
{
|
|
int flag = (tmpv == 0x187f03) ? (SSP_WAIT_30FE06) : (SSP_WAIT_30FE08);
|
|
EOP_LDR_IMM(0,7,0x490); // dram_ptr
|
|
EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
|
|
EOP_LDRH_IMM(0,0,8); // ldrh r0, [r0, #8]
|
|
EOP_TST_REG_SIMPLE(0,0);
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
|
|
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
|
|
}
|
|
EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET
|
|
EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
|
|
hostreg_r[0] = hostreg_r[1] = -1;
|
|
ret += 2; break;
|
|
}
|
|
else
|
|
return -1; /* TODO.. */
|
|
|
|
|
|
// ldi (ri), imm
|
|
case 0x06:
|
|
// int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
|
|
tr_mov16(0, imm);
|
|
if ((op&3) == 3)
|
|
{
|
|
tmpv = (op>>2) & 3; // direct addressing
|
|
if (op & 0x100) {
|
|
if (hostreg_r[1] != 0x100200) {
|
|
EOP_ADD_IMM(1,7,30/2,0x200>>2); // add r1, r7, 0x200
|
|
hostreg_r[1] = 0x100200;
|
|
}
|
|
EOP_STRH_IMM(0,1,tmpv<<1); // str r0, [r1, {0,2,4,6}]
|
|
} else {
|
|
EOP_STRH_IMM(0,7,tmpv<<1); // str r0, [r7, {0,2,4,6}]
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int r = (op&3) | ((op>>6)&4);
|
|
if (const_regb & (1 << (r + 8))) {
|
|
tr_bank_write(const_regs.r[r] | ((r < 4) ? 0 : 0x100));
|
|
} else {
|
|
int reg = (r < 4) ? 8 : 9;
|
|
int ror = ((4 - (r&3))*8) & 0x1f;
|
|
EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
|
|
if (r >= 4)
|
|
EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
|
|
if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
|
|
else EOP_ADD_REG_LSL(1,7,1,1);
|
|
EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
|
|
hostreg_r[1] = -1;
|
|
}
|
|
tr_ptrr_mod(r, (op>>2) & 3, 0);
|
|
}
|
|
ret++; break;
|
|
|
|
// ld adr, a
|
|
case 0x07:
|
|
if (hostreg_r[0] != (SSP_A<<16)) {
|
|
EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
|
|
hostreg_r[0] = SSP_A<<16;
|
|
}
|
|
tr_bank_write(op&0x1ff);
|
|
ret++; break;
|
|
|
|
// ld d, ri
|
|
case 0x09: {
|
|
int r, reg;
|
|
r = (op&3) | ((op>>6)&4); // src
|
|
tmpv2 = (op >> 4) & 0xf; // dst
|
|
if (tmpv2 >= 8) tr_unhandled();
|
|
|
|
if (const_regb & (1 << (r+8))) {
|
|
tr_mov16(0, const_regs.r[r]);
|
|
const_regs.gr[tmpv2].h = const_regs.r[r];
|
|
const_regb |= 1 << tmpv2;
|
|
} else {
|
|
reg = (r < 4) ? 8 : 9;
|
|
if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
|
|
EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
|
|
hostreg_r[0] = -1;
|
|
const_regb &= ~(1 << tmpv2);
|
|
}
|
|
tr_write_funcs[tmpv2]();
|
|
ret++; break;
|
|
}
|
|
|
|
// ldi ri, simm
|
|
case 0x0c ... 0x0f:
|
|
tmpv = (op>>8)&7;
|
|
const_regs.r[tmpv] = op;
|
|
const_regb |= 1 << (tmpv + 8);
|
|
dirty_regb |= 1 << (tmpv + 8);
|
|
ret++; break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void *translate_block(int pc)
|
|
{
|
|
unsigned int op, op1, imm, ccount = 0;
|
|
unsigned int *block_start;
|
|
int ret, ret_prev = -1;
|
|
|
|
// create .pool
|
|
//*tcache_ptr++ = (u32) in_funcs; // -1 func pool
|
|
|
|
printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
|
|
block_start = tcache_ptr;
|
|
const_regb = 0;
|
|
dirty_regb = CRREG_P;
|
|
hostreg_clear();
|
|
|
|
emit_block_prologue();
|
|
|
|
for (; ccount < 100;)
|
|
{
|
|
//printf(" insn #%i\n", icount);
|
|
op = PROGRAM(pc++);
|
|
op1 = op >> 9;
|
|
imm = (u32)-1;
|
|
|
|
if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
|
|
imm = PROGRAM(pc++); // immediate
|
|
|
|
ret = translate_op(op, &pc, imm);
|
|
if (ret <= 0)
|
|
{
|
|
tr_flush_dirty_pr();
|
|
|
|
emit_mov_const(0, op);
|
|
|
|
// need immediate?
|
|
if (imm != (u32)-1)
|
|
emit_mov_const(1, imm);
|
|
|
|
// dump PC
|
|
emit_pc_dump(pc);
|
|
|
|
if (ret_prev > 0) emit_call(regfile_store);
|
|
emit_call(in_funcs[op1]);
|
|
emit_call(regfile_load);
|
|
|
|
if (in_funcs[op1] == NULL) {
|
|
printf("NULL func! op=%08x (%02x)\n", op, op1);
|
|
exit(1);
|
|
}
|
|
ccount++;
|
|
hostreg_clear();
|
|
dirty_regb |= CRREG_P;
|
|
}
|
|
else
|
|
ccount += ret;
|
|
|
|
if (op1 == 0x24 || op1 == 0x26 || // call, bra
|
|
((op1 == 0 || op1 == 1 || op1 == 4 || op1 == 5 || op1 == 9 || op1 == 0x25) &&
|
|
(op & 0xf0) == 0x60)) { // ld PC
|
|
break;
|
|
}
|
|
ret_prev = ret;
|
|
}
|
|
|
|
tr_flush_dirty_pr();
|
|
emit_block_epilogue(ccount + 1);
|
|
*tcache_ptr++ = 0xffffffff; // end of block
|
|
//printf(" %i inst\n", icount);
|
|
|
|
if (tcache_ptr - tcache > TCACHE_SIZE/4) {
|
|
printf("tcache overflow!\n");
|
|
fflush(stdout);
|
|
exit(1);
|
|
}
|
|
|
|
// stats
|
|
nblocks++;
|
|
//if (pc >= 0x400)
|
|
printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
|
|
//printf("%p %p\n", tcache_ptr, emit_block_epilogue);
|
|
|
|
#ifdef DUMP_BLOCK
|
|
{
|
|
FILE *f = fopen("tcache.bin", "wb");
|
|
fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
|
|
fclose(f);
|
|
}
|
|
exit(0);
|
|
#endif
|
|
|
|
handle_caches();
|
|
|
|
return block_start;
|
|
}
|
|
|
|
|
|
|
|
// -----------------------------------------------------
|
|
|
|
int ssp1601_dyn_startup(void)
|
|
{
|
|
memset(tcache, 0, TCACHE_SIZE);
|
|
memset(block_table, 0, sizeof(block_table));
|
|
memset(block_table_iram, 0, sizeof(block_table_iram));
|
|
tcache_ptr = tcache;
|
|
*tcache_ptr++ = 0xffffffff;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void ssp1601_dyn_reset(ssp1601_t *ssp)
|
|
{
|
|
ssp1601_reset_local(ssp);
|
|
ssp->ptr_rom = (unsigned int) Pico.rom;
|
|
ssp->ptr_iram = (unsigned int) svp->iram_rom;
|
|
ssp->ptr_dram = (unsigned int) svp->dram;
|
|
}
|
|
|
|
void ssp1601_dyn_run(int cycles)
|
|
{
|
|
if (ssp->emu_status & SSP_WAIT_MASK) return;
|
|
//{ printf("%i wait\n", Pico.m.frame_count); return; }
|
|
//printf("%i %04x\n", Pico.m.frame_count, rPC<<1);
|
|
|
|
#ifdef DUMP_BLOCK
|
|
rPC = DUMP_BLOCK >> 1;
|
|
#endif
|
|
while (cycles > 0)
|
|
{
|
|
int (*trans_entry)(void);
|
|
if (rPC < 0x800/2)
|
|
{
|
|
if (iram_dirty) {
|
|
iram_context = get_iram_context();
|
|
iram_dirty--;
|
|
}
|
|
if (block_table_iram[iram_context][rPC] == NULL)
|
|
block_table_iram[iram_context][rPC] = translate_block(rPC);
|
|
trans_entry = (void *) block_table_iram[iram_context][rPC];
|
|
}
|
|
else
|
|
{
|
|
if (block_table[rPC] == NULL)
|
|
block_table[rPC] = translate_block(rPC);
|
|
trans_entry = (void *) block_table[rPC];
|
|
}
|
|
|
|
//printf("enter %04x\n", rPC<<1);
|
|
cycles -= trans_entry();
|
|
//printf("leave %04x\n", rPC<<1);
|
|
}
|
|
// debug_dump2file("tcache.bin", tcache, (tcache_ptr - tcache) << 1);
|
|
// exit(1);
|
|
}
|
|
|