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82bc9cdd10
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@220 be3aeb3a-fb24-0410-a615-afba39da0efa
300 lines
8.1 KiB
C
300 lines
8.1 KiB
C
/* cpuctrl for GP2X
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Copyright (C) 2005 Hermes/PS2Reality
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the gamma-routine was provided by theoddbot
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parts (c) Rlyehs Work & (C) 2006 god_at_hell
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdio.h>
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#include <math.h>
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#include "cpuctrl.h"
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/* system registers */
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static struct
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{
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unsigned short SYSCLKENREG,SYSCSETREG,UPLLVSETREG,FPLLVSETREG,
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DUALINT920,DUALINT940,DUALCTRL940,MEMTIMEX0,MEMTIMEX1,DISPCSETREG,
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DPC_HS_WIDTH,DPC_HS_STR,DPC_HS_END,DPC_VS_END,DPC_DE;
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}
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system_reg;
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static volatile unsigned short *MEM_REG;
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#define SYS_CLK_FREQ 7372800
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// Fout = (m * Fin) / (p * 2^s)
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// m = MDIV+8, p = PDIV+2, s = SDIV
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// m = (Fout * p * 2^s) / Fin
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void cpuctrl_init(void)
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{
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extern volatile unsigned short *gp2x_memregs; /* from minimal library rlyeh */
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MEM_REG=&gp2x_memregs[0];
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system_reg.DISPCSETREG=MEM_REG[0x924>>1];
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system_reg.UPLLVSETREG=MEM_REG[0x916>>1];
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system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
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system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
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system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
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system_reg.DUALINT920=MEM_REG[0x3B40>>1];
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system_reg.DUALINT940=MEM_REG[0x3B42>>1];
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system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
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system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
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system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
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system_reg.DPC_HS_WIDTH=MEM_REG[0x281A>>1];
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system_reg.DPC_HS_STR=MEM_REG[0x281C>>1];
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system_reg.DPC_HS_END=MEM_REG[0x281E>>1];
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system_reg.DPC_VS_END=MEM_REG[0x2822>>1];
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system_reg.DPC_DE=MEM_REG[0x2826>>1];
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}
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void cpuctrl_deinit(void)
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{
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MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
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MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
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MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
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MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
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MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
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MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
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MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
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MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1 /*| 0x9000*/;
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unset_LCD_custom_rate();
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}
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void set_display_clock_div(unsigned div)
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{
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div=((div & 63) | 64)<<8;
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MEM_REG[0x924>>1]=(MEM_REG[0x924>>1] & ~(255<<8)) | div;
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}
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void set_FCLK(unsigned MHZ)
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{
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unsigned v;
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unsigned mdiv,pdiv=3,scale=0;
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MHZ*=1000000;
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mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
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mdiv=((mdiv-8)<<8) & 0xff00;
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pdiv=((pdiv-2)<<2) & 0xfc;
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scale&=3;
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v=mdiv | pdiv | scale;
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MEM_REG[0x910>>1]=v;
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}
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void set_920_Div(unsigned short div)
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{
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unsigned short v;
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v = MEM_REG[0x91c>>1] & (~0x3);
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MEM_REG[0x91c>>1] = (div & 0x7) | v;
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}
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void set_DCLK_Div( unsigned short div )
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{
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unsigned short v;
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v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)) );
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MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
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}
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/*
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void Disable_940(void)
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{
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MEM_REG[0x3B42>>1];
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MEM_REG[0x3B42>>1]=0;
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MEM_REG[0x3B46>>1]=0xffff;
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MEM_REG[0x3B48>>1]|= (1 << 7);
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MEM_REG[0x904>>1]&=0xfffe;
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}
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*/
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typedef struct
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{
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unsigned short reg, valmask, val;
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}
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reg_setting;
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// ~59.998, couldn't figure closer values
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static reg_setting rate_almost60[] =
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{
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{ 0x0914, 0xffff, (212<<8)|(2<<2)|1 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(36<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 1 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 0 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 2 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 12 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 34<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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// perfect 50Hz?
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static reg_setting rate_50[] =
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{
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{ 0x0914, 0xffff, (39<<8)|(0<<2)|2 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(7<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 31 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 16 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 15 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 15 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 37<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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// 16639/2 ~120.20
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static reg_setting rate_120_20[] =
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{
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{ 0x0914, 0xffff, (96<<8)|(0<<2)|2 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(7<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 19 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 7 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 7 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 12 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 37<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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// 19997/2 ~100.02
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static reg_setting rate_100_02[] =
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{
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{ 0x0914, 0xffff, (98<<8)|(0<<2)|2 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(8<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 26 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 6 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 6 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 31 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 37<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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// 120.00 97/0/2/7|25/ 7/ 7/11/37
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static reg_setting rate_120[] =
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{
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{ 0x0914, 0xffff, (97<<8)|(0<<2)|2 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(7<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 25 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 7 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 7 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 11 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 37<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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// 100.00 96/0/2/7|29/25/53/15/37
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static reg_setting rate_100[] =
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{
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{ 0x0914, 0xffff, (96<<8)|(0<<2)|2 }, /* UPLLSETVREG */
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{ 0x0924, 0xff00, (2<<14)|(7<<8) }, /* DISPCSETREG */
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{ 0x281A, 0x00ff, 29 }, /* .HSWID(T2) */
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{ 0x281C, 0x00ff, 25 }, /* .HSSTR(T8) */
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{ 0x281E, 0x00ff, 53 }, /* .HSEND(T7) */
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{ 0x2822, 0x01ff, 15 }, /* .VSEND (T9) */
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{ 0x2826, 0x0ff0, 37<<4 }, /* .DESTR(T3) */
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{ 0, 0, 0 }
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};
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static reg_setting *possible_rates[] = { rate_almost60, rate_50, rate_120_20, rate_100_02, rate_120, rate_100 };
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void set_LCD_custom_rate(lcd_rate_t rate)
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{
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reg_setting *set;
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if (MEM_REG[0x2800>>1] & 0x100) // tv-out
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{
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return;
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}
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printf("setting custom LCD refresh, mode=%i... ", rate); fflush(stdout);
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for (set = possible_rates[rate]; set->reg; set++)
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{
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unsigned short val = MEM_REG[set->reg >> 1];
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val &= ~set->valmask;
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val |= set->val;
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MEM_REG[set->reg >> 1] = val;
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}
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printf("done.\n");
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}
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void unset_LCD_custom_rate(void)
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{
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printf("reset to prev LCD refresh.\n");
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MEM_REG[0x914>>1]=system_reg.UPLLVSETREG;
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MEM_REG[0x924>>1]=system_reg.DISPCSETREG;
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MEM_REG[0x281A>>1]=system_reg.DPC_HS_WIDTH;
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MEM_REG[0x281C>>1]=system_reg.DPC_HS_STR;
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MEM_REG[0x281E>>1]=system_reg.DPC_HS_END;
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MEM_REG[0x2822>>1]=system_reg.DPC_VS_END;
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MEM_REG[0x2826>>1]=system_reg.DPC_DE;
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}
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void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD)
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{
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tRC -= 1; tRAS -= 1; tWR -= 1; tMRD -= 1; tRFC -= 1; tRP -= 1; tRCD -= 1; // ???
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MEM_REG[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF);
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MEM_REG[0x3804>>1] = /*0x9000 |*/ ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF);
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}
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void set_gamma(int g100, int A_SNs_curve)
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{
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float gamma = (float) g100 / 100;
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int i;
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gamma = 1/gamma;
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//enable gamma
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MEM_REG[0x2880>>1]&=~(1<<12);
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MEM_REG[0x295C>>1]=0;
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for(i=0; i<256; i++)
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{
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unsigned char g;
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unsigned short s;
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const unsigned short grey50=143, grey75=177, grey25=97;
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float blah;
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if (A_SNs_curve)
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{
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// The next formula is all about gaussian interpolation
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blah = (( -128 * exp(-powf((float) i/64.0f + 2.0f , 2.0f))) +
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( -64 * exp(-powf((float) i/64.0f + 1.0f , 2.0f))) +
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(grey25 * exp(-powf((float) i/64.0f - 1.0f , 2.0f))) +
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(grey50 * exp(-powf((float) i/64.0f - 2.0f , 2.0f))) +
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(grey75 * exp(-powf((float) i/64.0f - 3.0f , 2.0f))) +
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( 256 * exp(-powf((float) i/64.0f - 4.0f , 2.0f))) +
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( 320 * exp(-powf((float) i/64.0f - 5.0f , 2.0f))) +
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( 384 * exp(-powf((float) i/64.0f - 6.0f , 2.0f)))) / (1.772637f);
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blah += 0.5f;
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}
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else
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{
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blah = i;
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}
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g = (unsigned char)(255.0*pow(blah/255.0,gamma));
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//printf("%d : %d\n", i, g);
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s = (g<<8) | g;
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MEM_REG[0x295E>>1]= s;
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MEM_REG[0x295E>>1]= g;
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}
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}
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