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https://github.com/RaySollium99/picodrive.git
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86 lines
3 KiB
C
86 lines
3 KiB
C
int sh2_drc_init(SH2 *sh2);
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void sh2_drc_finish(SH2 *sh2);
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void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2);
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void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2);
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#ifdef DRC_SH2
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void sh2_drc_mem_setup(SH2 *sh2);
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void sh2_drc_flush_all(void);
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#else
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#define sh2_drc_mem_setup(x)
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#define sh2_drc_flush_all()
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#define sh2_drc_frame()
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#endif
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#define BLOCK_INSN_LIMIT 1024
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/* op_flags */
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#define OF_DELAY_OP (1 << 0)
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#define OF_BTARGET (1 << 1)
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#define OF_LOOP (3 << 2) // NONE, IDLE, DELAY, POLL loop
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#define OF_B_IN_DS (1 << 4)
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#define OF_DELAY_INSN (1 << 5) // DT, (TODO ADD+CMP?)
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#define OF_POLL_INSN (1 << 6) // MOV @(...),Rn (no post increment), TST @(...)
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#define OF_BASIC_LOOP (1 << 7) // pinnable loop without any branches in it
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#define OF_IDLE_LOOP (1 << 2)
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#define OF_DELAY_LOOP (2 << 2)
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#define OF_POLL_LOOP (3 << 2)
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u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc,
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u32 *base_literals, u32 *end_literals);
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#if defined(DRC_SH2) && defined(__GNUC__) && !defined(__clang__)
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// direct access to some host CPU registers used by the DRC if gcc is used.
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// XXX MUST match SHR_SR definitions in cpu/drc/emit_*.c; should be moved there
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// XXX yuck, there's no portable way to determine register size. Use long long
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// if target is 64 bit and data model is ILP32 or LLP64(windows), else long
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#if defined(__arm__)
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#define DRC_SR_REG "r10"
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#define DRC_REG_LL 0 // 32 bit
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#elif defined(__aarch64__)
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#define DRC_SR_REG "r28"
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#define DRC_REG_LL (__ILP32__ || _WIN32)
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#elif defined(__mips__)
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#define DRC_SR_REG "s6"
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#define DRC_REG_LL (_MIPS_SZPTR > _MIPS_SZLONG) // (_MIPS_SIM == _ABIN32)
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#elif defined(__riscv__) || defined(__riscv)
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#define DRC_SR_REG "s11"
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#define DRC_REG_LL 0 // no ABI for (__ILP32__ && __riscv_xlen != 32)
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#elif defined(__powerpc__) || defined(__ppc__) || defined(__PPC__)
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#define DRC_SR_REG "r28"
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#define DRC_REG_LL 0 // no ABI for __ILP32__
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#elif defined(__i386__)
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#define DRC_SR_REG "edi"
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#define DRC_REG_LL 0 // 32 bit
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#elif defined(__x86_64__)
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#define DRC_SR_REG "rbx"
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#define DRC_REG_LL (__ILP32__ || _WIN32)
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#endif
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#endif
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#ifdef DRC_SR_REG
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// XXX this is more clear but produces too much overhead for slow platforms
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extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
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extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
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// NB: sh2_sr MUST have register size if optimizing with -O3 (-fif-conversion)
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#if DRC_REG_LL
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#define DRC_DECLARE_SR register long long _sh2_sr asm(DRC_SR_REG)
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#else
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#define DRC_DECLARE_SR register long _sh2_sr asm(DRC_SR_REG)
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#endif
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// NB: save/load SR register only when DRC is executing and not in DMA access
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#define DRC_SAVE_SR(sh2) \
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if (likely((sh2->state & (SH2_IN_DRC|SH2_STATE_SLEEP)) == SH2_IN_DRC)) \
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sh2->sr = (s32)_sh2_sr
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// sh2_drc_save_sr(sh2)
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#define DRC_RESTORE_SR(sh2) \
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if (likely((sh2->state & (SH2_IN_DRC|SH2_STATE_SLEEP)) == SH2_IN_DRC)) \
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_sh2_sr = (s32)sh2->sr
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// sh2_drc_restore_sr(sh2)
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#else
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#define DRC_DECLARE_SR
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#define DRC_SAVE_SR(sh2)
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#define DRC_RESTORE_SR(sh2)
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#endif
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