mirror of
https://github.com/RaySollium99/picodrive.git
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f0d7b1faa1
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@832 be3aeb3a-fb24-0410-a615-afba39da0efa
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
#include "../sh2.h"
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// MAME types
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typedef signed char INT8;
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typedef signed short INT16;
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typedef signed int INT32;
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typedef unsigned int UINT32;
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typedef unsigned short UINT16;
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typedef unsigned char UINT8;
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#define RB(a) p32x_sh2_read8(a,sh2)
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#define RW(a) p32x_sh2_read16(a,sh2)
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#define RL(a) p32x_sh2_read32(a,sh2)
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#define WB(a,d) p32x_sh2_write8(a,d,sh2)
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#define WW(a,d) p32x_sh2_write16(a,d,sh2)
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#define WL(a,d) p32x_sh2_write32(a,d,sh2)
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// some stuff from sh2comn.h
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#define T 0x00000001
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#define S 0x00000002
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#define I 0x000000f0
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#define Q 0x00000100
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#define M 0x00000200
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#define AM 0xc7ffffff
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#define FLAGS (M|Q|I|S|T)
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#define Rn ((opcode>>8)&15)
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#define Rm ((opcode>>4)&15)
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#define sh2_icount sh2->icount
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#include "sh2.c"
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#ifndef DRC_SH2
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void sh2_execute(SH2 *sh2_, int cycles)
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{
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sh2 = sh2_;
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sh2->cycles_aim += cycles;
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sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
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if (sh2->icount <= 0)
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return;
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do
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{
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UINT32 opcode;
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/* FIXME: Darxide doesn't like this */
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if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
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{
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if (sh2->pending_irl > sh2->pending_int_irq)
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sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
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else {
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sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
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sh2->pending_int_irq = 0; // auto-clear
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sh2->pending_level = sh2->pending_irl;
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}
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sh2->test_irq = 0;
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}
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if (sh2->delay)
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{
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sh2->ppc = sh2->delay;
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opcode = RW(sh2->delay);
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sh2->pc -= 2;
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}
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else
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{
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sh2->ppc = sh2->pc;
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opcode = RW(sh2->pc);
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}
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sh2->delay = 0;
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sh2->pc += 2;
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switch (opcode & ( 15 << 12))
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{
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case 0<<12: op0000(opcode); break;
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case 1<<12: op0001(opcode); break;
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case 2<<12: op0010(opcode); break;
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case 3<<12: op0011(opcode); break;
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case 4<<12: op0100(opcode); break;
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case 5<<12: op0101(opcode); break;
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case 6<<12: op0110(opcode); break;
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case 7<<12: op0111(opcode); break;
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case 8<<12: op1000(opcode); break;
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case 9<<12: op1001(opcode); break;
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case 10<<12: op1010(opcode); break;
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case 11<<12: op1011(opcode); break;
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case 12<<12: op1100(opcode); break;
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case 13<<12: op1101(opcode); break;
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case 14<<12: op1110(opcode); break;
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default: op1111(opcode); break;
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}
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sh2->icount--;
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}
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while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
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sh2->cycles_done += cycles - sh2->icount;
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}
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#else // DRC_SH2
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#ifdef __i386__
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#define REGPARM(x) __attribute__((regparm(x)))
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#else
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#define REGPARM(x)
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#endif
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// drc debug
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void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
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{
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sh2 = sh2_;
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sh2->pc += 2;
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switch (opcode & ( 15 << 12))
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{
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case 0<<12: op0000(opcode); break;
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case 1<<12: op0001(opcode); break;
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case 2<<12: op0010(opcode); break;
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case 3<<12: op0011(opcode); break;
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case 4<<12: op0100(opcode); break;
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case 5<<12: op0101(opcode); break;
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case 6<<12: op0110(opcode); break;
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case 7<<12: op0111(opcode); break;
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case 8<<12: op1000(opcode); break;
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case 9<<12: op1001(opcode); break;
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case 10<<12: op1010(opcode); break;
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case 11<<12: op1011(opcode); break;
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case 12<<12: op1100(opcode); break;
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case 13<<12: op1101(opcode); break;
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case 14<<12: op1110(opcode); break;
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default: op1111(opcode); break;
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}
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}
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#endif
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