mirror of
https://github.com/RaySollium99/picodrive.git
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f8ef8ff710
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@318 be3aeb3a-fb24-0410-a615-afba39da0efa
215 lines
6.2 KiB
C
215 lines
6.2 KiB
C
// basic, incomplete SSP160x (SSP1601?) interpreter
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/*
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* Register info
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* most names taken from MAME code
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*
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* 0. "-"
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* size: 16
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* desc: Constant register with all bits set (0xffff).
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*
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* 1. "X"
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* size: 16
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* desc: Generic register. When set, updates P (P = X * Y * 2) ??
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*
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* 2. "Y"
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* size: 16
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* desc: Generic register. When set, updates P (P = X * Y * 2) ??
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*
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* 3. "A"
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* size: 32
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* desc: Accumulator.
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*
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* 4. "ST"
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* size: 16
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* desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
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* fedc ba98 7654 3210
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* 210 - RPL (?) (e: "loop size", fir16_32.sc)
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* 43 - RB (?)
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* 5 - GP0_0 (ST5?) Changed before acessing AL (affects banking?).
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* 6 - GP0_1 (ST6?) Cleared before acessing AL (affects banking?). Set after.
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* 7 - IE (?) Not used by SVP code (never set, but preserved)?
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* 8 - OP (?) Not used by SVP code (only cleared)?
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* 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
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* a - GPI_0 Interrupt 0 enable/status?
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* b - GPI_1 Interrupt 1 enable/status?
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* c - L L flag. Carry?
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* d - Z Zero flag.
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* e - OV Overflow flag.
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* f - N Negative flag.
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* seen directly changing code sequences:
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* ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
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* ldi ST, 60h ori A, 60h and A, E8h and A, E8h
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* ld ST, A ld ST, A ori 3
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* ld ST, A
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*
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* 5. "STACK"
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* size: 16
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* desc: hw stack of 6 levels (according to datasheet)
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*
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* 6. "PC"
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* size: 16
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* desc: Program counter.
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*
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* 7. "P"
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* size: 32
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* desc: multiply result register. Updated after mp* instructions,
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* or writes to X or Y (P = X * Y * 2) ??
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* probably affected by MACS bit in ST.
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*
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* 8. "PM0" (PM from PMAR name from Tasco's docs)
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* size: 16?
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* desc: Programmable Memory access register.
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* On reset, or when one (both?) GP0 bits are clear,
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* acts as some additional status reg?
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*
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* 9. "PM1"
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* size: 16?
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* desc: Programmable Memory access register.
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* This reg. is only used as PMAR.
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*
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* 10. "PM2"
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* size: 16?
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* desc: Programmable Memory access register.
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* This reg. is only used as PMAR.
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*
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* 11. "XST"
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* size: 16?
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* desc: eXternal STate. Mapped to a15000 at 68k side.
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* Can be programmed as PMAR? (only seen in test mode code)
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*
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* 12. "PM4"
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* size: 16?
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* desc: Programmable Memory access register.
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* This reg. is only used as PMAR. The most used PMAR by VR.
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*
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* 13. (unused by VR)
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*
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* 14. "PMC" (PMC from PMAC name from Tasco's docs)
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* size: 32?
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* desc: Programmable Memory access Control. Set using 2 16bit writes,
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* first address, then mode word. After setting PMAC, PMAR sould
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* be accessed to program it.
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*
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* 15. "AL"
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* size: 16
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* desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
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* (normally reading acc (ld X, A) you get 16 most significant bits).
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*
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*
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* There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
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* They can be accessed directly, or 2 indirection levels can be used [ (r0), ((r0)) ],
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* which work similar to * and ** operators in C.
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*
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* r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
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* 3 modifiers can be applied (optional):
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* + : post-increment [ex: ld a, (r0+) ]
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* - : post-decrement
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* +!: same as '+' ???
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*
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* r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
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* They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
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* Samsung's old DSP page claims that).
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* 1 of these 4 modifiers must be used (short form direct addressing?):
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* |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
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* |01: RAMx[1]
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* |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
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* |11: RAMx[3]
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*
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*
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* Instruction notes
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*
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* mld (rj), (ri) [, b]
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* operation: A = 0; P = (rj) * (ri)
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* notes: based on IIR_4B.SC sample. flags? what is b???
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* TODO: figure out if (rj) and (ri) get loaded in X and Y
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*
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* mpya (rj), (ri) [, b]
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* name: multiply and add?
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* operation: A += P; P = (rj) * (ri)
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*
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* mpys (rj), (ri), b
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* name: multiply and subtract?
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* notes: not used by VR code.
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*/
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#include "../../PicoInt.h"
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#define rX ssp->gr[SSP_X].l
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#define rY ssp->gr[SSP_Y].l
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#define rA ssp->gr[SSP_A] // 4
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#define rST ssp->gr[SSP_ST].l
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#define rSTACK ssp->gr[SSP_STACK].l
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#define rPC ssp->gr[SSP_PC].l
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#define rP ssp->gr[SSP_P] // 8
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#define rPM0 ssp->gr[SSP_PM0].l
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#define rPM1 ssp->gr[SSP_PM1].l
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#define rPM2 ssp->gr[SSP_PM2].l
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#define rXST ssp->gr[SSP_XST].l // 12
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#define rPM4 ssp->gr[SSP_PM4].l // 14
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#define rPMC ssp->gr[SSP_PMC].l
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#define rAL ssp->gr[SSP_A].l
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#define GET_PC() (PC - (unsigned short *)Pico.rom)
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#define SET_PC() PC = (unsigned short *)Pico.rom + rPC
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void ssp1601_reset(ssp1601_t *ssp)
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{
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ssp->emu_status = 0;
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ssp->gr[SSP_GR0].v = 0xffff;
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rPC = 0x400;
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rSTACK = 5; // ?
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}
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void ssp1601_run(ssp1601_t *ssp, int cycles)
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{
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unsigned short *PC;
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int op;
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SET_PC();
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while (cycles > 0)
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{
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op = *PC;
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switch (op >> 9)
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{
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// ld d, s
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case 0:
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{
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int s, d, opdata = 0;
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if (op == 0) break; // nop
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s = op & 0x0f;
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d = (op & 0xf0) >> 4;
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if (s == SSP_A || s == SSP_P) opdata |= 1; // src is 32bit
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if (d == SSP_A || d == SSP_P) opdata |= 2; // dst is 32bit
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if (s == SSP_STACK) opdata |= 4; // src is stack
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if (d == SSP_STACK) opdata |= 8; // dst is stack
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switch (opdata)
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{
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case 0x0: ssp->gr[d].l = ssp->gr[s].l; break; // 16 <- 16
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case 0x1: ssp->gr[d].l = ssp->gr[s].h; break; // 16 <- 32
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case 0x2: ssp->gr[d].h = ssp->gr[s].l; break; // 32 <- 16
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// TODO: MAME claims that only hi word is transfered. Go figure.
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case 0x3: ssp->gr[d].v = ssp->gr[s].v; break; // 32 <- 32
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case 0x4: ; // TODO
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}
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if (d == SSP_PC)
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{
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SET_PC();
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cycles--;
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}
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break;
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}
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default:
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elprintf(0xffff, "ssp: unhandled op %04x @ %04x", op, GET_PC()<<1);
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break;
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}
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cycles--;
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PC++;
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}
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rPC = GET_PC();
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}
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