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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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37
include/linux/8250_pci.h Normal file
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/*
* Definitions for PCI support.
*/
#define FL_BASE_MASK 0x0007
#define FL_BASE0 0x0000
#define FL_BASE1 0x0001
#define FL_BASE2 0x0002
#define FL_BASE3 0x0003
#define FL_BASE4 0x0004
#define FL_GET_BASE(x) (x & FL_BASE_MASK)
/* Use successive BARs (PCI base address registers),
else use offset into some specified BAR */
#define FL_BASE_BARS 0x0008
/* do not assign an irq */
#define FL_NOIRQ 0x0080
/* Use the Base address register size to cap number of ports */
#define FL_REGION_SZ_CAP 0x0100
struct pciserial_board {
unsigned int flags;
unsigned int num_ports;
unsigned int base_baud;
unsigned int uart_offset;
unsigned int reg_shift;
unsigned int first_offset;
};
struct serial_private;
struct serial_private *
pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board);
void pciserial_remove_ports(struct serial_private *priv);
void pciserial_suspend_ports(struct serial_private *priv);
void pciserial_resume_ports(struct serial_private *priv);

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include/linux/Kbuild Normal file
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header-y += if_pppolac.h
header-y += if_pppopns.h

84
include/linux/a.out.h Normal file
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#ifndef __A_OUT_GNU_H__
#define __A_OUT_GNU_H__
#include <uapi/linux/a.out.h>
#ifndef __ASSEMBLY__
#if defined (M_OLDSUN2)
#else
#endif
#if defined (M_68010)
#else
#endif
#if defined (M_68020)
#else
#endif
#if defined (M_SPARC)
#else
#endif
#if !defined (N_MAGIC)
#endif
#if !defined (N_BADMAG)
#endif
#if !defined (N_TXTOFF)
#endif
#if !defined (N_DATOFF)
#endif
#if !defined (N_TRELOFF)
#endif
#if !defined (N_DRELOFF)
#endif
#if !defined (N_SYMOFF)
#endif
#if !defined (N_STROFF)
#endif
#if !defined (N_TXTADDR)
#endif
#if defined(vax) || defined(hp300) || defined(pyr)
#endif
#ifdef sony
#endif /* Sony. */
#ifdef is68k
#endif
#if defined(m68k) && defined(PORTAR)
#endif
#ifdef linux
#include <asm/page.h>
#if defined(__i386__) || defined(__mc68000__)
#else
#ifndef SEGMENT_SIZE
#define SEGMENT_SIZE PAGE_SIZE
#endif
#endif
#endif
#ifndef N_DATADDR
#endif
#if !defined (N_BSSADDR)
#endif
#if !defined (N_NLIST_DECLARED)
#endif /* no N_NLIST_DECLARED. */
#if !defined (N_UNDF)
#endif
#if !defined (N_ABS)
#endif
#if !defined (N_TEXT)
#endif
#if !defined (N_DATA)
#endif
#if !defined (N_BSS)
#endif
#if !defined (N_FN)
#endif
#if !defined (N_EXT)
#endif
#if !defined (N_TYPE)
#endif
#if !defined (N_STAB)
#endif
#if !defined (N_RELOCATION_INFO_DECLARED)
#ifdef NS32K
#else
#endif
#endif /* no N_RELOCATION_INFO_DECLARED. */
#endif /*__ASSEMBLY__ */
#endif /* __A_OUT_GNU_H__ */

105
include/linux/acct.h Normal file
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/*
* BSD Process Accounting for Linux - Definitions
*
* Author: Marco van Wieringen (mvw@planets.elm.net)
*
* This header file contains the definitions needed to implement
* BSD-style process accounting. The kernel accounting code and all
* user-level programs that try to do something useful with the
* process accounting log must include this file.
*
* Copyright (C) 1995 - 1997 Marco van Wieringen - ELM Consultancy B.V.
*
*/
#ifndef _LINUX_ACCT_H
#define _LINUX_ACCT_H
#include <uapi/linux/acct.h>
#ifdef CONFIG_BSD_PROCESS_ACCT
struct vfsmount;
struct super_block;
struct pacct_struct;
struct pid_namespace;
extern int acct_parm[]; /* for sysctl */
extern void acct_collect(long exitcode, int group_dead);
extern void acct_process(void);
extern void acct_exit_ns(struct pid_namespace *);
#else
#define acct_collect(x,y) do { } while (0)
#define acct_process() do { } while (0)
#define acct_exit_ns(ns) do { } while (0)
#endif
/*
* ACCT_VERSION numbers as yet defined:
* 0: old format (until 2.6.7) with 16 bit uid/gid
* 1: extended variant (binary compatible on M68K)
* 2: extended variant (binary compatible on everything except M68K)
* 3: new binary incompatible format (64 bytes)
* 4: new binary incompatible format (128 bytes)
* 5: new binary incompatible format (128 bytes, second half)
*
*/
#undef ACCT_VERSION
#undef AHZ
#ifdef CONFIG_BSD_PROCESS_ACCT_V3
#define ACCT_VERSION 3
#define AHZ 100
typedef struct acct_v3 acct_t;
#else
#ifdef CONFIG_M68K
#define ACCT_VERSION 1
#else
#define ACCT_VERSION 2
#endif
#define AHZ (USER_HZ)
typedef struct acct acct_t;
#endif
#include <linux/jiffies.h>
/*
* Yet another set of HZ to *HZ helper functions.
* See <linux/jiffies.h> for the original.
*/
static inline u32 jiffies_to_AHZ(unsigned long x)
{
#if (TICK_NSEC % (NSEC_PER_SEC / AHZ)) == 0
# if HZ < AHZ
return x * (AHZ / HZ);
# else
return x / (HZ / AHZ);
# endif
#else
u64 tmp = (u64)x * TICK_NSEC;
do_div(tmp, (NSEC_PER_SEC / AHZ));
return (long)tmp;
#endif
}
static inline u64 nsec_to_AHZ(u64 x)
{
#if (NSEC_PER_SEC % AHZ) == 0
do_div(x, (NSEC_PER_SEC / AHZ));
#elif (AHZ % 512) == 0
x *= AHZ/512;
do_div(x, (NSEC_PER_SEC / 512));
#else
/*
* max relative error 5.7e-8 (1.8s per year) for AHZ <= 1024,
* overflow after 64.99 years.
* exact for AHZ=60, 72, 90, 120, 144, 180, 300, 600, 900, ...
*/
x *= 9;
do_div(x, (unsigned long)((9ull * NSEC_PER_SEC + (AHZ/2))
/ AHZ));
#endif
return x;
}
#endif /* _LINUX_ACCT_H */

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/*
* acpi.h - ACPI Interface
*
* Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#ifndef _LINUX_ACPI_H
#define _LINUX_ACPI_H
#include <linux/errno.h>
#include <linux/ioport.h> /* for struct resource */
#include <linux/device.h>
#ifndef _LINUX
#define _LINUX
#endif
#include <acpi/acpi.h>
#ifdef CONFIG_ACPI
#include <linux/list.h>
#include <linux/mod_devicetable.h>
#include <linux/dynamic_debug.h>
#include <acpi/acpi_bus.h>
#include <acpi/acpi_drivers.h>
#include <acpi/acpi_numa.h>
#include <acpi/acpi_io.h>
#include <asm/acpi.h>
static inline acpi_handle acpi_device_handle(struct acpi_device *adev)
{
return adev ? adev->handle : NULL;
}
#define ACPI_COMPANION(dev) ((dev)->acpi_node.companion)
#define ACPI_COMPANION_SET(dev, adev) ACPI_COMPANION(dev) = (adev)
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
static inline void acpi_preset_companion(struct device *dev,
struct acpi_device *parent, u64 addr)
{
ACPI_COMPANION_SET(dev, acpi_find_child_device(parent, addr, NULL));
}
static inline const char *acpi_dev_name(struct acpi_device *adev)
{
return dev_name(&adev->dev);
}
enum acpi_irq_model_id {
ACPI_IRQ_MODEL_PIC = 0,
ACPI_IRQ_MODEL_IOAPIC,
ACPI_IRQ_MODEL_IOSAPIC,
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_COUNT
};
extern enum acpi_irq_model_id acpi_irq_model;
enum acpi_interrupt_id {
ACPI_INTERRUPT_PMI = 1,
ACPI_INTERRUPT_INIT,
ACPI_INTERRUPT_CPEI,
ACPI_INTERRUPT_COUNT
};
#define ACPI_SPACE_MEM 0
enum acpi_address_range_id {
ACPI_ADDRESS_RANGE_MEMORY = 1,
ACPI_ADDRESS_RANGE_RESERVED = 2,
ACPI_ADDRESS_RANGE_ACPI = 3,
ACPI_ADDRESS_RANGE_NVS = 4,
ACPI_ADDRESS_RANGE_COUNT
};
/* Table Handlers */
typedef int (*acpi_tbl_table_handler)(struct acpi_table_header *table);
typedef int (*acpi_tbl_entry_handler)(struct acpi_subtable_header *header,
const unsigned long end);
#ifdef CONFIG_ACPI_INITRD_TABLE_OVERRIDE
void acpi_initrd_override(void *data, size_t size);
#else
static inline void acpi_initrd_override(void *data, size_t size)
{
}
#endif
#define BAD_MADT_ENTRY(entry, end) ( \
(!entry) || (unsigned long)entry + sizeof(*entry) > end || \
((struct acpi_subtable_header *)entry)->length < sizeof(*entry))
char * __acpi_map_table (unsigned long phys_addr, unsigned long size);
void __acpi_unmap_table(char *map, unsigned long size);
int early_acpi_boot_init(void);
int acpi_boot_init (void);
void acpi_boot_table_init (void);
int acpi_mps_check (void);
int acpi_numa_init (void);
int acpi_table_init (void);
int acpi_table_parse(char *id, acpi_tbl_table_handler handler);
int __init acpi_table_parse_entries(char *id, unsigned long table_size,
int entry_id,
acpi_tbl_entry_handler handler,
unsigned int max_entries);
int acpi_table_parse_madt(enum acpi_madt_type id,
acpi_tbl_entry_handler handler,
unsigned int max_entries);
int acpi_parse_mcfg (struct acpi_table_header *header);
void acpi_table_print_madt_entry (struct acpi_subtable_header *madt);
/* the following four functions are architecture-dependent */
void acpi_numa_slit_init (struct acpi_table_slit *slit);
void acpi_numa_processor_affinity_init (struct acpi_srat_cpu_affinity *pa);
void acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_affinity *pa);
int acpi_numa_memory_affinity_init (struct acpi_srat_mem_affinity *ma);
void acpi_numa_arch_fixup(void);
#ifdef CONFIG_ACPI_HOTPLUG_CPU
/* Arch dependent functions for cpu hotplug support */
int acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu);
int acpi_unmap_lsapic(int cpu);
#endif /* CONFIG_ACPI_HOTPLUG_CPU */
int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base);
int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base);
void acpi_irq_stats_init(void);
extern u32 acpi_irq_handled;
extern u32 acpi_irq_not_handled;
extern int sbf_port;
extern unsigned long acpi_realmode_flags;
int acpi_register_gsi (struct device *dev, u32 gsi, int triggering, int polarity);
int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
int acpi_isa_irq_to_gsi (unsigned isa_irq, u32 *gsi);
#ifdef CONFIG_X86_IO_APIC
extern int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
#else
#define acpi_get_override_irq(gsi, trigger, polarity) (-1)
#endif
/*
* This function undoes the effect of one call to acpi_register_gsi().
* If this matches the last registration, any IRQ resources for gsi
* are freed.
*/
void acpi_unregister_gsi (u32 gsi);
struct pci_dev;
int acpi_pci_irq_enable (struct pci_dev *dev);
void acpi_penalize_isa_irq(int irq, int active);
void acpi_pci_irq_disable (struct pci_dev *dev);
extern int ec_read(u8 addr, u8 *val);
extern int ec_write(u8 addr, u8 val);
extern int ec_transaction(u8 command,
const u8 *wdata, unsigned wdata_len,
u8 *rdata, unsigned rdata_len);
extern acpi_handle ec_get_handle(void);
extern bool acpi_is_pnp_device(struct acpi_device *);
#if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE)
typedef void (*wmi_notify_handler) (u32 value, void *context);
extern acpi_status wmi_evaluate_method(const char *guid, u8 instance,
u32 method_id,
const struct acpi_buffer *in,
struct acpi_buffer *out);
extern acpi_status wmi_query_block(const char *guid, u8 instance,
struct acpi_buffer *out);
extern acpi_status wmi_set_block(const char *guid, u8 instance,
const struct acpi_buffer *in);
extern acpi_status wmi_install_notify_handler(const char *guid,
wmi_notify_handler handler, void *data);
extern acpi_status wmi_remove_notify_handler(const char *guid);
extern acpi_status wmi_get_event_data(u32 event, struct acpi_buffer *out);
extern bool wmi_has_guid(const char *guid);
#endif /* CONFIG_ACPI_WMI */
#define ACPI_VIDEO_OUTPUT_SWITCHING 0x0001
#define ACPI_VIDEO_DEVICE_POSTING 0x0002
#define ACPI_VIDEO_ROM_AVAILABLE 0x0004
#define ACPI_VIDEO_BACKLIGHT 0x0008
#define ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR 0x0010
#define ACPI_VIDEO_BACKLIGHT_FORCE_VIDEO 0x0020
#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR 0x0040
#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO 0x0080
#define ACPI_VIDEO_BACKLIGHT_DMI_VENDOR 0x0100
#define ACPI_VIDEO_BACKLIGHT_DMI_VIDEO 0x0200
#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR 0x0400
#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO 0x0800
#if defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE)
extern long acpi_video_get_capabilities(acpi_handle graphics_dev_handle);
extern long acpi_is_video_device(acpi_handle handle);
extern void acpi_video_dmi_promote_vendor(void);
extern void acpi_video_dmi_demote_vendor(void);
extern int acpi_video_backlight_support(void);
extern int acpi_video_display_switch_support(void);
#else
static inline long acpi_video_get_capabilities(acpi_handle graphics_dev_handle)
{
return 0;
}
static inline long acpi_is_video_device(acpi_handle handle)
{
return 0;
}
static inline void acpi_video_dmi_promote_vendor(void)
{
}
static inline void acpi_video_dmi_demote_vendor(void)
{
}
static inline int acpi_video_backlight_support(void)
{
return 0;
}
static inline int acpi_video_display_switch_support(void)
{
return 0;
}
#endif /* defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE) */
extern int acpi_blacklisted(void);
extern void acpi_dmi_osi_linux(int enable, const struct dmi_system_id *d);
extern void acpi_osi_setup(char *str);
#ifdef CONFIG_ACPI_NUMA
int acpi_get_node(acpi_handle handle);
#else
static inline int acpi_get_node(acpi_handle handle)
{
return 0;
}
#endif
extern int acpi_paddr_to_node(u64 start_addr, u64 size);
extern int pnpacpi_disabled;
#define PXM_INVAL (-1)
bool acpi_dev_resource_memory(struct acpi_resource *ares, struct resource *res);
bool acpi_dev_resource_io(struct acpi_resource *ares, struct resource *res);
bool acpi_dev_resource_address_space(struct acpi_resource *ares,
struct resource *res);
bool acpi_dev_resource_ext_address_space(struct acpi_resource *ares,
struct resource *res);
unsigned long acpi_dev_irq_flags(u8 triggering, u8 polarity, u8 shareable);
bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
struct resource *res);
struct resource_list_entry {
struct list_head node;
struct resource res;
};
void acpi_dev_free_resource_list(struct list_head *list);
int acpi_dev_get_resources(struct acpi_device *adev, struct list_head *list,
int (*preproc)(struct acpi_resource *, void *),
void *preproc_data);
int acpi_check_resource_conflict(const struct resource *res);
int acpi_check_region(resource_size_t start, resource_size_t n,
const char *name);
int acpi_resources_are_enforced(void);
#ifdef CONFIG_HIBERNATION
void __init acpi_no_s4_hw_signature(void);
#endif
#ifdef CONFIG_PM_SLEEP
void __init acpi_old_suspend_ordering(void);
void __init acpi_nvs_nosave(void);
void __init acpi_nvs_nosave_s3(void);
#endif /* CONFIG_PM_SLEEP */
struct acpi_osc_context {
char *uuid_str; /* UUID string */
int rev;
struct acpi_buffer cap; /* list of DWORD capabilities */
struct acpi_buffer ret; /* free by caller if success */
};
acpi_status acpi_str_to_uuid(char *str, u8 *uuid);
acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
/* Indexes into _OSC Capabilities Buffer (DWORDs 2 & 3 are device-specific) */
#define OSC_QUERY_DWORD 0 /* DWORD 1 */
#define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
#define OSC_CONTROL_DWORD 2 /* DWORD 3 */
/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
#define OSC_QUERY_ENABLE 0x00000001 /* input */
#define OSC_REQUEST_ERROR 0x00000002 /* return */
#define OSC_INVALID_UUID_ERROR 0x00000004 /* return */
#define OSC_INVALID_REVISION_ERROR 0x00000008 /* return */
#define OSC_CAPABILITIES_MASK_ERROR 0x00000010 /* return */
/* Platform-Wide Capabilities _OSC: Capabilities DWORD 2: Support Field */
#define OSC_SB_PAD_SUPPORT 0x00000001
#define OSC_SB_PPC_OST_SUPPORT 0x00000002
#define OSC_SB_PR3_SUPPORT 0x00000004
#define OSC_SB_HOTPLUG_OST_SUPPORT 0x00000008
#define OSC_SB_APEI_SUPPORT 0x00000010
#define OSC_SB_CPC_SUPPORT 0x00000020
extern bool osc_sb_apei_support_acked;
/* PCI Host Bridge _OSC: Capabilities DWORD 2: Support Field */
#define OSC_PCI_EXT_CONFIG_SUPPORT 0x00000001
#define OSC_PCI_ASPM_SUPPORT 0x00000002
#define OSC_PCI_CLOCK_PM_SUPPORT 0x00000004
#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 0x00000008
#define OSC_PCI_MSI_SUPPORT 0x00000010
#define OSC_PCI_SUPPORT_MASKS 0x0000001f
/* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */
#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 0x00000001
#define OSC_PCI_SHPC_NATIVE_HP_CONTROL 0x00000002
#define OSC_PCI_EXPRESS_PME_CONTROL 0x00000004
#define OSC_PCI_EXPRESS_AER_CONTROL 0x00000008
#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL 0x00000010
#define OSC_PCI_CONTROL_MASKS 0x0000001f
#define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
#define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
#define ACPI_GSB_ACCESS_ATTRIB_WORD 0x00000008
#define ACPI_GSB_ACCESS_ATTRIB_BLOCK 0x0000000A
#define ACPI_GSB_ACCESS_ATTRIB_MULTIBYTE 0x0000000B
#define ACPI_GSB_ACCESS_ATTRIB_WORD_CALL 0x0000000C
#define ACPI_GSB_ACCESS_ATTRIB_BLOCK_CALL 0x0000000D
#define ACPI_GSB_ACCESS_ATTRIB_RAW_BYTES 0x0000000E
#define ACPI_GSB_ACCESS_ATTRIB_RAW_PROCESS 0x0000000F
extern acpi_status acpi_pci_osc_control_set(acpi_handle handle,
u32 *mask, u32 req);
/* Enable _OST when all relevant hotplug operations are enabled */
#if defined(CONFIG_ACPI_HOTPLUG_CPU) && \
defined(CONFIG_ACPI_HOTPLUG_MEMORY) && \
defined(CONFIG_ACPI_CONTAINER)
#define ACPI_HOTPLUG_OST
#endif
/* _OST Source Event Code (OSPM Action) */
#define ACPI_OST_EC_OSPM_SHUTDOWN 0x100
#define ACPI_OST_EC_OSPM_EJECT 0x103
#define ACPI_OST_EC_OSPM_INSERTION 0x200
/* _OST General Processing Status Code */
#define ACPI_OST_SC_SUCCESS 0x0
#define ACPI_OST_SC_NON_SPECIFIC_FAILURE 0x1
#define ACPI_OST_SC_UNRECOGNIZED_NOTIFY 0x2
/* _OST OS Shutdown Processing (0x100) Status Code */
#define ACPI_OST_SC_OS_SHUTDOWN_DENIED 0x80
#define ACPI_OST_SC_OS_SHUTDOWN_IN_PROGRESS 0x81
#define ACPI_OST_SC_OS_SHUTDOWN_COMPLETED 0x82
#define ACPI_OST_SC_OS_SHUTDOWN_NOT_SUPPORTED 0x83
/* _OST Ejection Request (0x3, 0x103) Status Code */
#define ACPI_OST_SC_EJECT_NOT_SUPPORTED 0x80
#define ACPI_OST_SC_DEVICE_IN_USE 0x81
#define ACPI_OST_SC_DEVICE_BUSY 0x82
#define ACPI_OST_SC_EJECT_DEPENDENCY_BUSY 0x83
#define ACPI_OST_SC_EJECT_IN_PROGRESS 0x84
/* _OST Insertion Request (0x200) Status Code */
#define ACPI_OST_SC_INSERT_IN_PROGRESS 0x80
#define ACPI_OST_SC_DRIVER_LOAD_FAILURE 0x81
#define ACPI_OST_SC_INSERT_NOT_SUPPORTED 0x82
extern void acpi_early_init(void);
extern int acpi_nvs_register(__u64 start, __u64 size);
extern int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
void *data);
const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
const struct device *dev);
static inline bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv)
{
return !!acpi_match_device(drv->acpi_match_table, dev);
}
int acpi_device_uevent_modalias(struct device *, struct kobj_uevent_env *);
int acpi_device_modalias(struct device *, char *, int);
struct platform_device *acpi_create_platform_device(struct acpi_device *);
#define ACPI_PTR(_ptr) (_ptr)
#else /* !CONFIG_ACPI */
#define acpi_disabled 1
#define ACPI_COMPANION(dev) (NULL)
#define ACPI_COMPANION_SET(dev, adev) do { } while (0)
#define ACPI_HANDLE(dev) (NULL)
static inline const char *acpi_dev_name(struct acpi_device *adev)
{
return NULL;
}
static inline void acpi_early_init(void) { }
static inline int early_acpi_boot_init(void)
{
return 0;
}
static inline int acpi_boot_init(void)
{
return 0;
}
static inline void acpi_boot_table_init(void)
{
return;
}
static inline int acpi_mps_check(void)
{
return 0;
}
static inline int acpi_check_resource_conflict(struct resource *res)
{
return 0;
}
static inline int acpi_check_region(resource_size_t start, resource_size_t n,
const char *name)
{
return 0;
}
struct acpi_table_header;
static inline int acpi_table_parse(char *id,
int (*handler)(struct acpi_table_header *))
{
return -ENODEV;
}
static inline int acpi_nvs_register(__u64 start, __u64 size)
{
return 0;
}
static inline int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
void *data)
{
return 0;
}
struct acpi_device_id;
static inline const struct acpi_device_id *acpi_match_device(
const struct acpi_device_id *ids, const struct device *dev)
{
return NULL;
}
static inline bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv)
{
return false;
}
static inline int acpi_device_uevent_modalias(struct device *dev,
struct kobj_uevent_env *env)
{
return -ENODEV;
}
static inline int acpi_device_modalias(struct device *dev,
char *buf, int size)
{
return -ENODEV;
}
#define ACPI_PTR(_ptr) (NULL)
#endif /* !CONFIG_ACPI */
#ifdef CONFIG_ACPI
void acpi_os_set_prepare_sleep(int (*func)(u8 sleep_state,
u32 pm1a_ctrl, u32 pm1b_ctrl));
acpi_status acpi_os_prepare_sleep(u8 sleep_state,
u32 pm1a_control, u32 pm1b_control);
void acpi_os_set_prepare_extended_sleep(int (*func)(u8 sleep_state,
u32 val_a, u32 val_b));
acpi_status acpi_os_prepare_extended_sleep(u8 sleep_state,
u32 val_a, u32 val_b);
#ifdef CONFIG_X86
void arch_reserve_mem_area(acpi_physical_address addr, size_t size);
#else
static inline void arch_reserve_mem_area(acpi_physical_address addr,
size_t size)
{
}
#endif /* CONFIG_X86 */
#else
#define acpi_os_set_prepare_sleep(func, pm1a_ctrl, pm1b_ctrl) do { } while (0)
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_PM_RUNTIME)
int acpi_dev_runtime_suspend(struct device *dev);
int acpi_dev_runtime_resume(struct device *dev);
int acpi_subsys_runtime_suspend(struct device *dev);
int acpi_subsys_runtime_resume(struct device *dev);
#else
static inline int acpi_dev_runtime_suspend(struct device *dev) { return 0; }
static inline int acpi_dev_runtime_resume(struct device *dev) { return 0; }
static inline int acpi_subsys_runtime_suspend(struct device *dev) { return 0; }
static inline int acpi_subsys_runtime_resume(struct device *dev) { return 0; }
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_PM_SLEEP)
int acpi_dev_suspend_late(struct device *dev);
int acpi_dev_resume_early(struct device *dev);
int acpi_subsys_prepare(struct device *dev);
void acpi_subsys_complete(struct device *dev);
int acpi_subsys_suspend_late(struct device *dev);
int acpi_subsys_resume_early(struct device *dev);
int acpi_subsys_suspend(struct device *dev);
int acpi_subsys_freeze(struct device *dev);
#else
static inline int acpi_dev_suspend_late(struct device *dev) { return 0; }
static inline int acpi_dev_resume_early(struct device *dev) { return 0; }
static inline int acpi_subsys_prepare(struct device *dev) { return 0; }
static inline void acpi_subsys_complete(struct device *dev) {}
static inline int acpi_subsys_suspend_late(struct device *dev) { return 0; }
static inline int acpi_subsys_resume_early(struct device *dev) { return 0; }
static inline int acpi_subsys_suspend(struct device *dev) { return 0; }
static inline int acpi_subsys_freeze(struct device *dev) { return 0; }
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_PM)
struct acpi_device *acpi_dev_pm_get_node(struct device *dev);
int acpi_dev_pm_attach(struct device *dev, bool power_on);
#else
static inline struct acpi_device *acpi_dev_pm_get_node(struct device *dev)
{
return NULL;
}
static inline int acpi_dev_pm_attach(struct device *dev, bool power_on)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_ACPI
__printf(3, 4)
void acpi_handle_printk(const char *level, acpi_handle handle,
const char *fmt, ...);
#else /* !CONFIG_ACPI */
static inline __printf(3, 4) void
acpi_handle_printk(const char *level, void *handle, const char *fmt, ...) {}
#endif /* !CONFIG_ACPI */
#if defined(CONFIG_ACPI) && defined(CONFIG_DYNAMIC_DEBUG)
__printf(3, 4)
void __acpi_handle_debug(struct _ddebug *descriptor, acpi_handle handle, const char *fmt, ...);
#else
#define __acpi_handle_debug(descriptor, handle, fmt, ...) \
acpi_handle_printk(KERN_DEBUG, handle, fmt, ##__VA_ARGS__);
#endif
/*
* acpi_handle_<level>: Print message with ACPI prefix and object path
*
* These interfaces acquire the global namespace mutex to obtain an object
* path. In interrupt context, it shows the object path as <n/a>.
*/
#define acpi_handle_emerg(handle, fmt, ...) \
acpi_handle_printk(KERN_EMERG, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_alert(handle, fmt, ...) \
acpi_handle_printk(KERN_ALERT, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_crit(handle, fmt, ...) \
acpi_handle_printk(KERN_CRIT, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_err(handle, fmt, ...) \
acpi_handle_printk(KERN_ERR, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_warn(handle, fmt, ...) \
acpi_handle_printk(KERN_WARNING, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_notice(handle, fmt, ...) \
acpi_handle_printk(KERN_NOTICE, handle, fmt, ##__VA_ARGS__)
#define acpi_handle_info(handle, fmt, ...) \
acpi_handle_printk(KERN_INFO, handle, fmt, ##__VA_ARGS__)
#if defined(DEBUG)
#define acpi_handle_debug(handle, fmt, ...) \
acpi_handle_printk(KERN_DEBUG, handle, fmt, ##__VA_ARGS__)
#else
#if defined(CONFIG_DYNAMIC_DEBUG)
#define acpi_handle_debug(handle, fmt, ...) \
do { \
DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, fmt); \
if (unlikely(descriptor.flags & _DPRINTK_FLAGS_PRINT)) \
__acpi_handle_debug(&descriptor, handle, pr_fmt(fmt), \
##__VA_ARGS__); \
} while (0)
#else
#define acpi_handle_debug(handle, fmt, ...) \
({ \
if (0) \
acpi_handle_printk(KERN_DEBUG, handle, fmt, ##__VA_ARGS__); \
0; \
})
#endif
#endif
#endif /*_LINUX_ACPI_H*/

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/*
* ACPI helpers for DMA request / controller
*
* Based on of_dma.h
*
* Copyright (C) 2013, Intel Corporation
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_ACPI_DMA_H
#define __LINUX_ACPI_DMA_H
#include <linux/list.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/dmaengine.h>
/**
* struct acpi_dma_spec - slave device DMA resources
* @chan_id: channel unique id
* @slave_id: request line unique id
* @dev: struct device of the DMA controller to be used in the filter
* function
*/
struct acpi_dma_spec {
int chan_id;
int slave_id;
struct device *dev;
};
/**
* struct acpi_dma - representation of the registered DMAC
* @dma_controllers: linked list node
* @dev: struct device of this controller
* @acpi_dma_xlate: callback function to find a suitable channel
* @data: private data used by a callback function
* @base_request_line: first supported request line (CSRT)
* @end_request_line: last supported request line (CSRT)
*/
struct acpi_dma {
struct list_head dma_controllers;
struct device *dev;
struct dma_chan *(*acpi_dma_xlate)
(struct acpi_dma_spec *, struct acpi_dma *);
void *data;
unsigned short base_request_line;
unsigned short end_request_line;
};
/* Used with acpi_dma_simple_xlate() */
struct acpi_dma_filter_info {
dma_cap_mask_t dma_cap;
dma_filter_fn filter_fn;
};
#ifdef CONFIG_DMA_ACPI
int acpi_dma_controller_register(struct device *dev,
struct dma_chan *(*acpi_dma_xlate)
(struct acpi_dma_spec *, struct acpi_dma *),
void *data);
int acpi_dma_controller_free(struct device *dev);
int devm_acpi_dma_controller_register(struct device *dev,
struct dma_chan *(*acpi_dma_xlate)
(struct acpi_dma_spec *, struct acpi_dma *),
void *data);
void devm_acpi_dma_controller_free(struct device *dev);
struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
size_t index);
struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
const char *name);
struct dma_chan *acpi_dma_simple_xlate(struct acpi_dma_spec *dma_spec,
struct acpi_dma *adma);
#else
static inline int acpi_dma_controller_register(struct device *dev,
struct dma_chan *(*acpi_dma_xlate)
(struct acpi_dma_spec *, struct acpi_dma *),
void *data)
{
return -ENODEV;
}
static inline int acpi_dma_controller_free(struct device *dev)
{
return -ENODEV;
}
static inline int devm_acpi_dma_controller_register(struct device *dev,
struct dma_chan *(*acpi_dma_xlate)
(struct acpi_dma_spec *, struct acpi_dma *),
void *data)
{
return -ENODEV;
}
static inline void devm_acpi_dma_controller_free(struct device *dev)
{
}
static inline struct dma_chan *acpi_dma_request_slave_chan_by_index(
struct device *dev, size_t index)
{
return ERR_PTR(-ENODEV);
}
static inline struct dma_chan *acpi_dma_request_slave_chan_by_name(
struct device *dev, const char *name)
{
return ERR_PTR(-ENODEV);
}
#define acpi_dma_simple_xlate NULL
#endif
#define acpi_dma_request_slave_channel acpi_dma_request_slave_chan_by_index
#endif /* __LINUX_ACPI_DMA_H */

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#ifndef _ACPI_PMTMR_H_
#define _ACPI_PMTMR_H_
#include <linux/clocksource.h>
/* Number of PMTMR ticks expected during calibration run */
#define PMTMR_TICKS_PER_SEC 3579545
/* limit it to 24 bits */
#define ACPI_PM_MASK CLOCKSOURCE_MASK(24)
/* Overrun value */
#define ACPI_PM_OVRRUN (1<<24)
#ifdef CONFIG_X86_PM_TIMER
extern u32 acpi_pm_read_verified(void);
extern u32 pmtmr_ioport;
static inline u32 acpi_pm_read_early(void)
{
if (!pmtmr_ioport)
return 0;
/* mask the output to 24 bits */
return acpi_pm_read_verified() & ACPI_PM_MASK;
}
#else
static inline u32 acpi_pm_read_early(void)
{
return 0;
}
#endif
#endif

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/*
* Definitions for ADB (Apple Desktop Bus) support.
*/
#ifndef __ADB_H
#define __ADB_H
#include <uapi/linux/adb.h>
struct adb_request {
unsigned char data[32];
int nbytes;
unsigned char reply[32];
int reply_len;
unsigned char reply_expected;
unsigned char sent;
unsigned char complete;
void (*done)(struct adb_request *);
void *arg;
struct adb_request *next;
};
struct adb_ids {
int nids;
unsigned char id[16];
};
/* Structure which encapsulates a low-level ADB driver */
struct adb_driver {
char name[16];
int (*probe)(void);
int (*init)(void);
int (*send_request)(struct adb_request *req, int sync);
int (*autopoll)(int devs);
void (*poll)(void);
int (*reset_bus)(void);
};
/* Values for adb_request flags */
#define ADBREQ_REPLY 1 /* expect reply */
#define ADBREQ_SYNC 2 /* poll until done */
#define ADBREQ_NOSEND 4 /* build the request, but don't send it */
/* Messages sent thru the client_list notifier. You should NOT stop
the operation, at least not with this version */
enum adb_message {
ADB_MSG_POWERDOWN, /* Currently called before sleep only */
ADB_MSG_PRE_RESET, /* Called before resetting the bus */
ADB_MSG_POST_RESET /* Called after resetting the bus (re-do init & register) */
};
extern struct blocking_notifier_head adb_client_list;
int adb_request(struct adb_request *req, void (*done)(struct adb_request *),
int flags, int nbytes, ...);
int adb_register(int default_id,int handler_id,struct adb_ids *ids,
void (*handler)(unsigned char *, int, int));
int adb_unregister(int index);
void adb_poll(void);
void adb_input(unsigned char *, int, int);
int adb_reset_bus(void);
int adb_try_handler_change(int address, int new_id);
int adb_get_infos(int address, int *original_address, int *handler_id);
#endif /* __ADB_H */

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#ifndef _ADFS_FS_H
#define _ADFS_FS_H
#include <uapi/linux/adfs_fs.h>
/*
* Calculate the boot block checksum on an ADFS drive. Note that this will
* appear to be correct if the sector contains all zeros, so also check that
* the disk size is non-zero!!!
*/
static inline int adfs_checkbblk(unsigned char *ptr)
{
unsigned int result = 0;
unsigned char *p = ptr + 511;
do {
result = (result & 0xff) + (result >> 8);
result = result + *--p;
} while (p != ptr);
return (result & 0xff) != ptr[511];
}
#endif

67
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/*
* Copyright (C) 2006 Intel Corp.
* Tom Long Nguyen (tom.l.nguyen@intel.com)
* Zhang Yanmin (yanmin.zhang@intel.com)
*/
#ifndef _AER_H_
#define _AER_H_
#include <linux/types.h>
#define AER_NONFATAL 0
#define AER_FATAL 1
#define AER_CORRECTABLE 2
struct pci_dev;
struct aer_header_log_regs {
unsigned int dw0;
unsigned int dw1;
unsigned int dw2;
unsigned int dw3;
};
struct aer_capability_regs {
u32 header;
u32 uncor_status;
u32 uncor_mask;
u32 uncor_severity;
u32 cor_status;
u32 cor_mask;
u32 cap_control;
struct aer_header_log_regs header_log;
u32 root_command;
u32 root_status;
u16 cor_err_source;
u16 uncor_err_source;
};
#if defined(CONFIG_PCIEAER)
/* pci-e port driver needs this function to enable aer */
int pci_enable_pcie_error_reporting(struct pci_dev *dev);
int pci_disable_pcie_error_reporting(struct pci_dev *dev);
int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
#else
static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
{
return -EINVAL;
}
static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev)
{
return -EINVAL;
}
static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
{
return -EINVAL;
}
#endif
void cper_print_aer(struct pci_dev *dev, int cper_severity,
struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
int severity,
struct aer_capability_regs *aer_regs);
#endif //_AER_H_

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/*
* AGPGART backend specific includes. Not for userspace consumption.
*
* Copyright (C) 2004 Silicon Graphics, Inc.
* Copyright (C) 2002-2003 Dave Jones
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _AGP_BACKEND_H
#define _AGP_BACKEND_H 1
#include <linux/list.h>
enum chipset_type {
NOT_SUPPORTED,
SUPPORTED,
};
struct agp_version {
u16 major;
u16 minor;
};
struct agp_kern_info {
struct agp_version version;
struct pci_dev *device;
enum chipset_type chipset;
unsigned long mode;
unsigned long aper_base;
size_t aper_size;
int max_memory; /* In pages */
int current_memory;
bool cant_use_aperture;
unsigned long page_mask;
const struct vm_operations_struct *vm_ops;
};
/*
* The agp_memory structure has information about the block of agp memory
* allocated. A caller may manipulate the next and prev pointers to link
* each allocated item into a list. These pointers are ignored by the backend.
* Everything else should never be written to, but the caller may read any of
* the items to determine the status of this block of agp memory.
*/
struct agp_bridge_data;
struct agp_memory {
struct agp_memory *next;
struct agp_memory *prev;
struct agp_bridge_data *bridge;
struct page **pages;
size_t page_count;
int key;
int num_scratch_pages;
off_t pg_start;
u32 type;
u32 physical;
bool is_bound;
bool is_flushed;
/* list of agp_memory mapped to the aperture */
struct list_head mapped_list;
/* DMA-mapped addresses */
struct scatterlist *sg_list;
int num_sg;
};
#define AGP_NORMAL_MEMORY 0
#define AGP_USER_TYPES (1 << 16)
#define AGP_USER_MEMORY (AGP_USER_TYPES)
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
extern struct agp_bridge_data *agp_bridge;
extern struct list_head agp_bridges;
extern struct agp_bridge_data *(*agp_find_bridge)(struct pci_dev *);
extern void agp_free_memory(struct agp_memory *);
extern struct agp_memory *agp_allocate_memory(struct agp_bridge_data *, size_t, u32);
extern int agp_copy_info(struct agp_bridge_data *, struct agp_kern_info *);
extern int agp_bind_memory(struct agp_memory *, off_t);
extern int agp_unbind_memory(struct agp_memory *);
extern void agp_enable(struct agp_bridge_data *, u32);
extern struct agp_bridge_data *agp_backend_acquire(struct pci_dev *);
extern void agp_backend_release(struct agp_bridge_data *);
#endif /* _AGP_BACKEND_H */

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/*
* AGPGART module version 0.99
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _AGP_H
#define _AGP_H 1
#include <linux/mutex.h>
#include <linux/agp_backend.h>
#include <uapi/linux/agpgart.h>
#define AGPGART_MINOR 175
struct agp_info {
struct agp_version version; /* version of the driver */
u32 bridge_id; /* bridge vendor/device */
u32 agp_mode; /* mode info of bridge */
unsigned long aper_base;/* base of aperture */
size_t aper_size; /* size of aperture */
size_t pg_total; /* max pages (swap + system) */
size_t pg_system; /* max pages (system) */
size_t pg_used; /* current pages used */
};
struct agp_setup {
u32 agp_mode; /* mode info of bridge */
};
/*
* The "prot" down below needs still a "sleep" flag somehow ...
*/
struct agp_segment {
off_t pg_start; /* starting page to populate */
size_t pg_count; /* number of pages */
int prot; /* prot flags for mmap */
};
struct agp_segment_priv {
off_t pg_start;
size_t pg_count;
pgprot_t prot;
};
struct agp_region {
pid_t pid; /* pid of process */
size_t seg_count; /* number of segments */
struct agp_segment *seg_list;
};
struct agp_allocate {
int key; /* tag of allocation */
size_t pg_count; /* number of pages */
u32 type; /* 0 == normal, other devspec */
u32 physical; /* device specific (some devices
* need a phys address of the
* actual page behind the gatt
* table) */
};
struct agp_bind {
int key; /* tag of allocation */
off_t pg_start; /* starting page to populate */
};
struct agp_unbind {
int key; /* tag of allocation */
u32 priority; /* priority for paging out */
};
struct agp_client {
struct agp_client *next;
struct agp_client *prev;
pid_t pid;
int num_segments;
struct agp_segment_priv **segments;
};
struct agp_controller {
struct agp_controller *next;
struct agp_controller *prev;
pid_t pid;
int num_clients;
struct agp_memory *pool;
struct agp_client *clients;
};
#define AGP_FF_ALLOW_CLIENT 0
#define AGP_FF_ALLOW_CONTROLLER 1
#define AGP_FF_IS_CLIENT 2
#define AGP_FF_IS_CONTROLLER 3
#define AGP_FF_IS_VALID 4
struct agp_file_private {
struct agp_file_private *next;
struct agp_file_private *prev;
pid_t my_pid;
unsigned long access_flags; /* long req'd for set_bit --RR */
};
struct agp_front_data {
struct mutex agp_mutex;
struct agp_controller *current_controller;
struct agp_controller *controllers;
struct agp_file_private *file_priv_list;
bool used_by_controller;
bool backend_acquired;
};
#endif /* _AGP_H */

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/*
* AHCI SATA platform driver
*
* Copyright 2004-2005 Red Hat, Inc.
* Jeff Garzik <jgarzik@pobox.com>
* Copyright 2010 MontaVista Software, LLC.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*/
#ifndef _AHCI_PLATFORM_H
#define _AHCI_PLATFORM_H
#include <linux/compiler.h>
struct device;
struct ata_port_info;
struct ahci_host_priv;
struct platform_device;
int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
struct ahci_host_priv *ahci_platform_get_resources(
struct platform_device *pdev);
int ahci_platform_init_host(struct platform_device *pdev,
struct ahci_host_priv *hpriv,
const struct ata_port_info *pi_template);
int ahci_platform_suspend_host(struct device *dev);
int ahci_platform_resume_host(struct device *dev);
int ahci_platform_suspend(struct device *dev);
int ahci_platform_resume(struct device *dev);
#endif /* _AHCI_PLATFORM_H */

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#ifndef __LINUX__AIO_H
#define __LINUX__AIO_H
#include <linux/list.h>
#include <linux/workqueue.h>
#include <linux/aio_abi.h>
#include <linux/uio.h>
#include <linux/rcupdate.h>
#include <linux/atomic.h>
struct kioctx;
struct kiocb;
#define KIOCB_KEY 0
/*
* We use ki_cancel == KIOCB_CANCELLED to indicate that a kiocb has been either
* cancelled or completed (this makes a certain amount of sense because
* successful cancellation - io_cancel() - does deliver the completion to
* userspace).
*
* And since most things don't implement kiocb cancellation and we'd really like
* kiocb completion to be lockless when possible, we use ki_cancel to
* synchronize cancellation and completion - we only set it to KIOCB_CANCELLED
* with xchg() or cmpxchg(), see batch_complete_aio() and kiocb_cancel().
*/
#define KIOCB_CANCELLED ((void *) (~0ULL))
typedef int (kiocb_cancel_fn)(struct kiocb *);
struct kiocb {
struct file *ki_filp;
struct kioctx *ki_ctx; /* NULL for sync ops */
kiocb_cancel_fn *ki_cancel;
void *private;
union {
void __user *user;
struct task_struct *tsk;
} ki_obj;
__u64 ki_user_data; /* user's data for completion */
loff_t ki_pos;
size_t ki_nbytes; /* copy of iocb->aio_nbytes */
struct list_head ki_list; /* the aio core uses this
* for cancellation */
/*
* If the aio_resfd field of the userspace iocb is not zero,
* this is the underlying eventfd context to deliver events to.
*/
struct eventfd_ctx *ki_eventfd;
};
static inline bool is_sync_kiocb(struct kiocb *kiocb)
{
return kiocb->ki_ctx == NULL;
}
static inline void init_sync_kiocb(struct kiocb *kiocb, struct file *filp)
{
*kiocb = (struct kiocb) {
.ki_ctx = NULL,
.ki_filp = filp,
.ki_obj.tsk = current,
};
}
/* prototypes */
#ifdef CONFIG_AIO
extern ssize_t wait_on_sync_kiocb(struct kiocb *iocb);
extern void aio_complete(struct kiocb *iocb, long res, long res2);
struct mm_struct;
extern void exit_aio(struct mm_struct *mm);
extern long do_io_submit(aio_context_t ctx_id, long nr,
struct iocb __user *__user *iocbpp, bool compat);
void kiocb_set_cancel_fn(struct kiocb *req, kiocb_cancel_fn *cancel);
#else
static inline ssize_t wait_on_sync_kiocb(struct kiocb *iocb) { return 0; }
static inline void aio_complete(struct kiocb *iocb, long res, long res2) { }
struct mm_struct;
static inline void exit_aio(struct mm_struct *mm) { }
static inline long do_io_submit(aio_context_t ctx_id, long nr,
struct iocb __user * __user *iocbpp,
bool compat) { return 0; }
static inline void kiocb_set_cancel_fn(struct kiocb *req,
kiocb_cancel_fn *cancel) { }
#endif /* CONFIG_AIO */
static inline struct kiocb *list_kiocb(struct list_head *h)
{
return list_entry(h, struct kiocb, ki_list);
}
/* for sysctl: */
extern unsigned long aio_nr;
extern unsigned long aio_max_nr;
#endif /* __LINUX__AIO_H */

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#ifndef _LINUX_ALARMTIMER_H
#define _LINUX_ALARMTIMER_H
#include <linux/time.h>
#include <linux/hrtimer.h>
#include <linux/timerqueue.h>
#include <linux/rtc.h>
enum alarmtimer_type {
ALARM_REALTIME,
ALARM_BOOTTIME,
ALARM_NUMTYPE,
};
enum alarmtimer_restart {
ALARMTIMER_NORESTART,
ALARMTIMER_RESTART,
};
#define ALARMTIMER_STATE_INACTIVE 0x00
#define ALARMTIMER_STATE_ENQUEUED 0x01
/**
* struct alarm - Alarm timer structure
* @node: timerqueue node for adding to the event list this value
* also includes the expiration time.
* @period: Period for recuring alarms
* @function: Function pointer to be executed when the timer fires.
* @type: Alarm type (BOOTTIME/REALTIME)
* @enabled: Flag that represents if the alarm is set to fire or not
* @data: Internal data value.
*/
struct alarm {
struct timerqueue_node node;
struct hrtimer timer;
enum alarmtimer_restart (*function)(struct alarm *, ktime_t now);
enum alarmtimer_type type;
int state;
void *data;
};
void alarm_init(struct alarm *alarm, enum alarmtimer_type type,
enum alarmtimer_restart (*function)(struct alarm *, ktime_t));
int alarm_start(struct alarm *alarm, ktime_t start);
int alarm_start_relative(struct alarm *alarm, ktime_t start);
void alarm_restart(struct alarm *alarm);
int alarm_try_to_cancel(struct alarm *alarm);
int alarm_cancel(struct alarm *alarm);
u64 alarm_forward(struct alarm *alarm, ktime_t now, ktime_t interval);
u64 alarm_forward_now(struct alarm *alarm, ktime_t interval);
ktime_t alarm_expires_remaining(const struct alarm *alarm);
/* Provide way to access the rtc device being used by alarmtimers */
struct rtc_device *alarmtimer_get_rtcdev(void);
#endif

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/*
* altera_jtaguart.h -- Altera JTAG UART driver defines.
*/
#ifndef __ALTJUART_H
#define __ALTJUART_H
#define ALTERA_JTAGUART_MAJOR 204
#define ALTERA_JTAGUART_MINOR 186
struct altera_jtaguart_platform_uart {
unsigned long mapbase; /* Physical address base */
unsigned int irq; /* Interrupt vector */
};
#endif /* __ALTJUART_H */

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/*
* altera_uart.h -- Altera UART driver defines.
*/
#ifndef __ALTUART_H
#define __ALTUART_H
struct altera_uart_platform_uart {
unsigned long mapbase; /* Physical address base */
unsigned int irq; /* Interrupt vector */
unsigned int uartclk; /* UART clock rate */
unsigned int bus_shift; /* Bus shift (address stride) */
};
#endif /* __ALTUART_H */

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/*
* linux/include/amba/bus.h
*
* This device type deals with ARM PrimeCells and anything else that
* presents a proper CID (0xB105F00D) at the end of the I/O register
* region or that is derived from a PrimeCell.
*
* Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ASMARM_AMBA_H
#define ASMARM_AMBA_H
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/err.h>
#include <linux/resource.h>
#include <linux/regulator/consumer.h>
#define AMBA_NR_IRQS 9
#define AMBA_CID 0xb105f00d
struct clk;
struct amba_device {
struct device dev;
struct resource res;
struct clk *pclk;
unsigned int periphid;
unsigned int irq[AMBA_NR_IRQS];
};
struct amba_driver {
struct device_driver drv;
int (*probe)(struct amba_device *, const struct amba_id *);
int (*remove)(struct amba_device *);
void (*shutdown)(struct amba_device *);
int (*suspend)(struct amba_device *, pm_message_t);
int (*resume)(struct amba_device *);
const struct amba_id *id_table;
};
/*
* Constants for the designer field of the Peripheral ID register. When bit 7
* is set to '1', bits [6:0] should be the JEP106 manufacturer identity code.
*/
enum amba_vendor {
AMBA_VENDOR_ARM = 0x41,
AMBA_VENDOR_ST = 0x80,
AMBA_VENDOR_QCOM = 0x51,
AMBA_VENDOR_LSI = 0xb6,
};
extern struct bus_type amba_bustype;
#define to_amba_device(d) container_of(d, struct amba_device, dev)
#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
int amba_driver_register(struct amba_driver *);
void amba_driver_unregister(struct amba_driver *);
struct amba_device *amba_device_alloc(const char *, resource_size_t, size_t);
void amba_device_put(struct amba_device *);
int amba_device_add(struct amba_device *, struct resource *);
int amba_device_register(struct amba_device *, struct resource *);
struct amba_device *amba_apb_device_add(struct device *parent, const char *name,
resource_size_t base, size_t size,
int irq1, int irq2, void *pdata,
unsigned int periphid);
struct amba_device *amba_ahb_device_add(struct device *parent, const char *name,
resource_size_t base, size_t size,
int irq1, int irq2, void *pdata,
unsigned int periphid);
struct amba_device *
amba_apb_device_add_res(struct device *parent, const char *name,
resource_size_t base, size_t size, int irq1,
int irq2, void *pdata, unsigned int periphid,
struct resource *resbase);
struct amba_device *
amba_ahb_device_add_res(struct device *parent, const char *name,
resource_size_t base, size_t size, int irq1,
int irq2, void *pdata, unsigned int periphid,
struct resource *resbase);
void amba_device_unregister(struct amba_device *);
struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
int amba_request_regions(struct amba_device *, const char *);
void amba_release_regions(struct amba_device *);
#define amba_pclk_enable(d) \
(IS_ERR((d)->pclk) ? 0 : clk_enable((d)->pclk))
#define amba_pclk_disable(d) \
do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
/* Some drivers don't use the struct amba_device */
#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
#define AMBA_PART_BITS(a) ((a) & 0xfff)
#define amba_config(d) AMBA_CONFIG_BITS((d)->periphid)
#define amba_rev(d) AMBA_REV_BITS((d)->periphid)
#define amba_manf(d) AMBA_MANF_BITS((d)->periphid)
#define amba_part(d) AMBA_PART_BITS((d)->periphid)
#define __AMBA_DEV(busid, data, mask) \
{ \
.coherent_dma_mask = mask, \
.init_name = busid, \
.platform_data = data, \
}
/*
* APB devices do not themselves have the ability to address memory,
* so DMA masks should be zero (much like USB peripheral devices.)
* The DMA controller DMA masks should be used instead (much like
* USB host controllers in conventional PCs.)
*/
#define AMBA_APB_DEVICE(name, busid, id, base, irqs, data) \
struct amba_device name##_device = { \
.dev = __AMBA_DEV(busid, data, 0), \
.res = DEFINE_RES_MEM(base, SZ_4K), \
.irq = irqs, \
.periphid = id, \
}
/*
* AHB devices are DMA capable, so set their DMA masks
*/
#define AMBA_AHB_DEVICE(name, busid, id, base, irqs, data) \
struct amba_device name##_device = { \
.dev = __AMBA_DEV(busid, data, ~0ULL), \
.res = DEFINE_RES_MEM(base, SZ_4K), \
.irq = irqs, \
.periphid = id, \
}
/*
* module_amba_driver() - Helper macro for drivers that don't do anything
* special in module init/exit. This eliminates a lot of boilerplate. Each
* module may only use this macro once, and calling it replaces module_init()
* and module_exit()
*/
#define module_amba_driver(__amba_drv) \
module_driver(__amba_drv, amba_driver_register, amba_driver_unregister)
#endif

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/*
* linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
*
* David A Rusling
*
* Copyright (C) 2001 ARM Limited
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/fb.h>
/*
* CLCD Controller Internal Register addresses
*/
#define CLCD_TIM0 0x00000000
#define CLCD_TIM1 0x00000004
#define CLCD_TIM2 0x00000008
#define CLCD_TIM3 0x0000000c
#define CLCD_UBAS 0x00000010
#define CLCD_LBAS 0x00000014
#define CLCD_PL110_IENB 0x00000018
#define CLCD_PL110_CNTL 0x0000001c
#define CLCD_PL110_STAT 0x00000020
#define CLCD_PL110_INTR 0x00000024
#define CLCD_PL110_UCUR 0x00000028
#define CLCD_PL110_LCUR 0x0000002C
#define CLCD_PL111_CNTL 0x00000018
#define CLCD_PL111_IENB 0x0000001c
#define CLCD_PL111_RIS 0x00000020
#define CLCD_PL111_MIS 0x00000024
#define CLCD_PL111_ICR 0x00000028
#define CLCD_PL111_UCUR 0x0000002c
#define CLCD_PL111_LCUR 0x00000030
#define CLCD_PALL 0x00000200
#define CLCD_PALETTE 0x00000200
#define TIM2_CLKSEL (1 << 5)
#define TIM2_IVS (1 << 11)
#define TIM2_IHS (1 << 12)
#define TIM2_IPC (1 << 13)
#define TIM2_IOE (1 << 14)
#define TIM2_BCD (1 << 26)
#define CNTL_LCDEN (1 << 0)
#define CNTL_LCDBPP1 (0 << 1)
#define CNTL_LCDBPP2 (1 << 1)
#define CNTL_LCDBPP4 (2 << 1)
#define CNTL_LCDBPP8 (3 << 1)
#define CNTL_LCDBPP16 (4 << 1)
#define CNTL_LCDBPP16_565 (6 << 1)
#define CNTL_LCDBPP16_444 (7 << 1)
#define CNTL_LCDBPP24 (5 << 1)
#define CNTL_LCDBW (1 << 4)
#define CNTL_LCDTFT (1 << 5)
#define CNTL_LCDMONO8 (1 << 6)
#define CNTL_LCDDUAL (1 << 7)
#define CNTL_BGR (1 << 8)
#define CNTL_BEBO (1 << 9)
#define CNTL_BEPO (1 << 10)
#define CNTL_LCDPWR (1 << 11)
#define CNTL_LCDVCOMP(x) ((x) << 12)
#define CNTL_LDMAFIFOTIME (1 << 15)
#define CNTL_WATERMARK (1 << 16)
enum {
/* individual formats */
CLCD_CAP_RGB444 = (1 << 0),
CLCD_CAP_RGB5551 = (1 << 1),
CLCD_CAP_RGB565 = (1 << 2),
CLCD_CAP_RGB888 = (1 << 3),
CLCD_CAP_BGR444 = (1 << 4),
CLCD_CAP_BGR5551 = (1 << 5),
CLCD_CAP_BGR565 = (1 << 6),
CLCD_CAP_BGR888 = (1 << 7),
/* connection layouts */
CLCD_CAP_444 = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
CLCD_CAP_5551 = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
CLCD_CAP_565 = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
CLCD_CAP_888 = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
/* red/blue ordering */
CLCD_CAP_RGB = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
CLCD_CAP_BGR = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
CLCD_CAP_ALL = CLCD_CAP_BGR | CLCD_CAP_RGB,
};
struct clcd_panel {
struct fb_videomode mode;
signed short width; /* width in mm */
signed short height; /* height in mm */
u32 tim2;
u32 tim3;
u32 cntl;
u32 caps;
unsigned int bpp:8,
fixedtimings:1,
grayscale:1;
unsigned int connector;
};
struct clcd_regs {
u32 tim0;
u32 tim1;
u32 tim2;
u32 tim3;
u32 cntl;
unsigned long pixclock;
};
struct clcd_fb;
/*
* the board-type specific routines
*/
struct clcd_board {
const char *name;
/*
* Optional. Hardware capability flags.
*/
u32 caps;
/*
* Optional. Check whether the var structure is acceptable
* for this display.
*/
int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
/*
* Compulsory. Decode fb->fb.var into regs->*. In the case of
* fixed timing, set regs->* to the register values required.
*/
void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
/*
* Optional. Disable any extra display hardware.
*/
void (*disable)(struct clcd_fb *);
/*
* Optional. Enable any extra display hardware.
*/
void (*enable)(struct clcd_fb *);
/*
* Setup platform specific parts of CLCD driver
*/
int (*setup)(struct clcd_fb *);
/*
* mmap the framebuffer memory
*/
int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
/*
* Remove platform specific parts of CLCD driver
*/
void (*remove)(struct clcd_fb *);
};
struct amba_device;
struct clk;
/* this data structure describes each frame buffer device we find */
struct clcd_fb {
struct fb_info fb;
struct amba_device *dev;
struct clk *clk;
struct clcd_panel *panel;
struct clcd_board *board;
void *board_data;
void __iomem *regs;
u16 off_ienb;
u16 off_cntl;
u32 clcd_cntl;
u32 cmap[16];
bool clk_enabled;
};
static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
{
struct fb_var_screeninfo *var = &fb->fb.var;
u32 val, cpl;
/*
* Program the CLCD controller registers and start the CLCD
*/
val = ((var->xres / 16) - 1) << 2;
val |= (var->hsync_len - 1) << 8;
val |= (var->right_margin - 1) << 16;
val |= (var->left_margin - 1) << 24;
regs->tim0 = val;
val = var->yres;
if (fb->panel->cntl & CNTL_LCDDUAL)
val /= 2;
val -= 1;
val |= (var->vsync_len - 1) << 10;
val |= var->lower_margin << 16;
val |= var->upper_margin << 24;
regs->tim1 = val;
val = fb->panel->tim2;
val |= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
cpl = var->xres_virtual;
if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
/* / 1 */;
else if (!var->grayscale) /* STN color */
cpl = cpl * 8 / 3;
else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
cpl /= 8;
else /* STN monochrome, 4bit */
cpl /= 4;
regs->tim2 = val | ((cpl - 1) << 16);
regs->tim3 = fb->panel->tim3;
val = fb->panel->cntl;
if (var->grayscale)
val |= CNTL_LCDBW;
if (fb->panel->caps && fb->board->caps &&
var->bits_per_pixel >= 16) {
/*
* if board and panel supply capabilities, we can support
* changing BGR/RGB depending on supplied parameters
*/
if (var->red.offset == 0)
val &= ~CNTL_BGR;
else
val |= CNTL_BGR;
}
switch (var->bits_per_pixel) {
case 1:
val |= CNTL_LCDBPP1;
break;
case 2:
val |= CNTL_LCDBPP2;
break;
case 4:
val |= CNTL_LCDBPP4;
break;
case 8:
val |= CNTL_LCDBPP8;
break;
case 16:
/*
* PL110 cannot choose between 5551 and 565 modes in its
* control register. It is possible to use 565 with
* custom external wiring.
*/
if (amba_part(fb->dev) == 0x110 ||
var->green.length == 5)
val |= CNTL_LCDBPP16;
else if (var->green.length == 6)
val |= CNTL_LCDBPP16_565;
else
val |= CNTL_LCDBPP16_444;
break;
case 32:
val |= CNTL_LCDBPP24;
break;
}
regs->cntl = val;
regs->pixclock = var->pixclock;
}
static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
var->xres_virtual = var->xres = (var->xres + 15) & ~15;
var->yres_virtual = var->yres = (var->yres + 1) & ~1;
#define CHECK(e,l,h) (var->e < l || var->e > h)
if (CHECK(right_margin, (5+1), 256) || /* back porch */
CHECK(left_margin, (5+1), 256) || /* front porch */
CHECK(hsync_len, (5+1), 256) ||
var->xres > 4096 ||
var->lower_margin > 255 || /* back porch */
var->upper_margin > 255 || /* front porch */
var->vsync_len > 32 ||
var->yres > 1024)
return -EINVAL;
#undef CHECK
/* single panel mode: PCD = max(PCD, 1) */
/* dual panel mode: PCD = max(PCD, 5) */
/*
* You can't change the grayscale setting, and
* we can only do non-interlaced video.
*/
if (var->grayscale != fb->fb.var.grayscale ||
(var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
#define CHECK(e) (var->e != fb->fb.var.e)
if (fb->panel->fixedtimings &&
(CHECK(xres) ||
CHECK(yres) ||
CHECK(bits_per_pixel) ||
CHECK(pixclock) ||
CHECK(left_margin) ||
CHECK(right_margin) ||
CHECK(upper_margin) ||
CHECK(lower_margin) ||
CHECK(hsync_len) ||
CHECK(vsync_len) ||
CHECK(sync)))
return -EINVAL;
#undef CHECK
var->nonstd = 0;
var->accel_flags = 0;
return 0;
}

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/*
* linux/include/asm-arm/hardware/amba_kmi.h
*
* Internal header file for AMBA KMI ports
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*
* ---------------------------------------------------------------------------
* From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
* Reference Manual - ARM DDI 0143B - see http://www.arm.com/
* ---------------------------------------------------------------------------
*/
#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
#define ASM_ARM_HARDWARE_AMBA_KMI_H
/*
* KMI control register:
* KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
* KMICR_RXINTREN 1 = enable RX interrupts
* KMICR_TXINTREN 1 = enable TX interrupts
* KMICR_EN 1 = enable KMI
* KMICR_FD 1 = force KMI data low
* KMICR_FC 1 = force KMI clock low
*/
#define KMICR (KMI_BASE + 0x00)
#define KMICR_TYPE (1 << 5)
#define KMICR_RXINTREN (1 << 4)
#define KMICR_TXINTREN (1 << 3)
#define KMICR_EN (1 << 2)
#define KMICR_FD (1 << 1)
#define KMICR_FC (1 << 0)
/*
* KMI status register:
* KMISTAT_TXEMPTY 1 = transmitter register empty
* KMISTAT_TXBUSY 1 = currently sending data
* KMISTAT_RXFULL 1 = receiver register ready to be read
* KMISTAT_RXBUSY 1 = currently receiving data
* KMISTAT_RXPARITY parity of last databyte received
* KMISTAT_IC current level of KMI clock input
* KMISTAT_ID current level of KMI data input
*/
#define KMISTAT (KMI_BASE + 0x04)
#define KMISTAT_TXEMPTY (1 << 6)
#define KMISTAT_TXBUSY (1 << 5)
#define KMISTAT_RXFULL (1 << 4)
#define KMISTAT_RXBUSY (1 << 3)
#define KMISTAT_RXPARITY (1 << 2)
#define KMISTAT_IC (1 << 1)
#define KMISTAT_ID (1 << 0)
/*
* KMI data register
*/
#define KMIDATA (KMI_BASE + 0x08)
/*
* KMI clock divisor: to generate 8MHz internal clock
* div = (ref / 8MHz) - 1; 0 <= div <= 15
*/
#define KMICLKDIV (KMI_BASE + 0x0c)
/*
* KMI interrupt register:
* KMIIR_TXINTR 1 = transmit interrupt asserted
* KMIIR_RXINTR 1 = receive interrupt asserted
*/
#define KMIIR (KMI_BASE + 0x10)
#define KMIIR_TXINTR (1 << 1)
#define KMIIR_RXINTR (1 << 0)
/*
* The size of the KMI primecell
*/
#define KMI_SIZE (0x100)
#endif

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/*
* include/linux/amba/mmci.h
*/
#ifndef AMBA_MMCI_H
#define AMBA_MMCI_H
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <linux/mmc/sdio_func.h>
struct embedded_sdio_data {
struct sdio_cis cis;
struct sdio_cccr cccr;
struct sdio_embedded_func *funcs;
int num_funcs;
};
/**
* struct mmci_platform_data - platform configuration for the MMCI
* (also known as PL180) block.
* @ocr_mask: available voltages on the 4 pins from the block, this
* is ignored if a regulator is used, see the MMC_VDD_* masks in
* mmc/host.h
* @ios_handler: a callback function to act on specfic ios changes,
* used for example to control a levelshifter
* mask into a value to be binary (or set some other custom bits
* in MMCIPWR) or:ed and written into the MMCIPWR register of the
* block. May also control external power based on the power_mode.
* @status: if no GPIO read function was given to the block in
* gpio_wp (below) this function will be called to determine
* whether a card is present in the MMC slot or not
* @gpio_wp: read this GPIO pin to see if the card is write protected
* @gpio_cd: read this GPIO pin to detect card insertion
* @cd_invert: true if the gpio_cd pin value is active low
*/
struct mmci_platform_data {
unsigned int ocr_mask;
int (*ios_handler)(struct device *, struct mmc_ios *);
unsigned int (*status)(struct device *);
int gpio_wp;
int gpio_cd;
bool cd_invert;
unsigned int status_irq;
struct embedded_sdio_data *embedded_sdio;
int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
};
#endif

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/*
* include/linux/amba/pl022.h
*
* Copyright (C) 2008-2009 ST-Ericsson AB
* Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
*
* Initial version inspired by:
* linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
* Initial adoption to PL022 by:
* Sachin Verma <sachin.verma@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SSP_PL022_H
#define _SSP_PL022_H
#include <linux/types.h>
/**
* whether SSP is in loopback mode or not
*/
enum ssp_loopback {
LOOPBACK_DISABLED,
LOOPBACK_ENABLED
};
/**
* enum ssp_interface - interfaces allowed for this SSP Controller
* @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
* @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
* interface
* @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
* interface
* @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
* &STn8815 only)
*/
enum ssp_interface {
SSP_INTERFACE_MOTOROLA_SPI,
SSP_INTERFACE_TI_SYNC_SERIAL,
SSP_INTERFACE_NATIONAL_MICROWIRE,
SSP_INTERFACE_UNIDIRECTIONAL
};
/**
* enum ssp_hierarchy - whether SSP is configured as Master or Slave
*/
enum ssp_hierarchy {
SSP_MASTER,
SSP_SLAVE
};
/**
* enum ssp_clock_params - clock parameters, to set SSP clock at a
* desired freq
*/
struct ssp_clock_params {
u8 cpsdvsr; /* value from 2 to 254 (even only!) */
u8 scr; /* value from 0 to 255 */
};
/**
* enum ssp_rx_endian - endianess of Rx FIFO Data
* this feature is only available in ST versionf of PL022
*/
enum ssp_rx_endian {
SSP_RX_MSB,
SSP_RX_LSB
};
/**
* enum ssp_tx_endian - endianess of Tx FIFO Data
*/
enum ssp_tx_endian {
SSP_TX_MSB,
SSP_TX_LSB
};
/**
* enum ssp_data_size - number of bits in one data element
*/
enum ssp_data_size {
SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
SSP_DATA_BITS_31, SSP_DATA_BITS_32
};
/**
* enum ssp_mode - SSP mode of operation (Communication modes)
*/
enum ssp_mode {
INTERRUPT_TRANSFER,
POLLING_TRANSFER,
DMA_TRANSFER
};
/**
* enum ssp_rx_level_trig - receive FIFO watermark level which triggers
* IT: Interrupt fires when _N_ or more elements in RX FIFO.
*/
enum ssp_rx_level_trig {
SSP_RX_1_OR_MORE_ELEM,
SSP_RX_4_OR_MORE_ELEM,
SSP_RX_8_OR_MORE_ELEM,
SSP_RX_16_OR_MORE_ELEM,
SSP_RX_32_OR_MORE_ELEM
};
/**
* Transmit FIFO watermark level which triggers (IT Interrupt fires
* when _N_ or more empty locations in TX FIFO)
*/
enum ssp_tx_level_trig {
SSP_TX_1_OR_MORE_EMPTY_LOC,
SSP_TX_4_OR_MORE_EMPTY_LOC,
SSP_TX_8_OR_MORE_EMPTY_LOC,
SSP_TX_16_OR_MORE_EMPTY_LOC,
SSP_TX_32_OR_MORE_EMPTY_LOC
};
/**
* enum SPI Clock Phase - clock phase (Motorola SPI interface only)
* @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
* @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
*/
enum ssp_spi_clk_phase {
SSP_CLK_FIRST_EDGE,
SSP_CLK_SECOND_EDGE
};
/**
* enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
* @SSP_CLK_POL_IDLE_LOW: Low inactive level
* @SSP_CLK_POL_IDLE_HIGH: High inactive level
*/
enum ssp_spi_clk_pol {
SSP_CLK_POL_IDLE_LOW,
SSP_CLK_POL_IDLE_HIGH
};
/**
* Microwire Conrol Lengths Command size in microwire format
*/
enum ssp_microwire_ctrl_len {
SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
SSP_BITS_31, SSP_BITS_32
};
/**
* enum Microwire Wait State
* @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
* @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
*/
enum ssp_microwire_wait_state {
SSP_MWIRE_WAIT_ZERO,
SSP_MWIRE_WAIT_ONE
};
/**
* enum ssp_duplex - whether Full/Half Duplex on microwire, only
* available in the ST Micro variant.
* @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
* SSPRXD not used
* @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
* an input.
*/
enum ssp_duplex {
SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
};
/**
* enum ssp_clkdelay - an optional clock delay on the feedback clock
* only available in the ST Micro PL023 variant.
* @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
* slave is sampled directly
* @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
* a delay of T-dt
* @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
* @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
* @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
* @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
* @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
* @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
*/
enum ssp_clkdelay {
SSP_FEEDBACK_CLK_DELAY_NONE,
SSP_FEEDBACK_CLK_DELAY_1T,
SSP_FEEDBACK_CLK_DELAY_2T,
SSP_FEEDBACK_CLK_DELAY_3T,
SSP_FEEDBACK_CLK_DELAY_4T,
SSP_FEEDBACK_CLK_DELAY_5T,
SSP_FEEDBACK_CLK_DELAY_6T,
SSP_FEEDBACK_CLK_DELAY_7T
};
/**
* CHIP select/deselect commands
*/
enum ssp_chip_select {
SSP_CHIP_SELECT,
SSP_CHIP_DESELECT
};
struct dma_chan;
/**
* struct pl022_ssp_master - device.platform_data for SPI controller devices.
* @bus_id: identifier for this bus
* @num_chipselect: chipselects are used to distinguish individual
* SPI slaves, and are numbered from zero to num_chipselects - 1.
* each slave has a chipselect signal, but it's common that not
* every chipselect is connected to a slave.
* @enable_dma: if true enables DMA driven transfers.
* @dma_rx_param: parameter to locate an RX DMA channel.
* @dma_tx_param: parameter to locate a TX DMA channel.
* @autosuspend_delay: delay in ms following transfer completion before the
* runtime power management system suspends the device. A setting of 0
* indicates no delay and the device will be suspended immediately.
* @rt: indicates the controller should run the message pump with realtime
* priority to minimise the transfer latency on the bus.
* @chipselects: list of <num_chipselects> chip select gpios
*/
struct pl022_ssp_controller {
u16 bus_id;
u8 num_chipselect;
u8 enable_dma:1;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
void *dma_rx_param;
void *dma_tx_param;
int autosuspend_delay;
bool rt;
int *chipselects;
};
/**
* struct ssp_config_chip - spi_board_info.controller_data for SPI
* slave devices, copied to spi_device.controller_data.
*
* @iface: Interface type(Motorola, TI, Microwire, Universal)
* @hierarchy: sets whether interface is master or slave
* @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
* @clk_freq: Tune freq parameters of SSP(when in master mode)
* @com_mode: communication mode: polling, Interrupt or DMA
* @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
* @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
* @ctrl_len: Microwire interface: Control length
* @wait_state: Microwire interface: Wait state
* @duplex: Microwire interface: Full/Half duplex
* @clkdelay: on the PL023 variant, the delay in feeback clock cycles
* before sampling the incoming line
* @cs_control: function pointer to board-specific function to
* assert/deassert I/O port to control HW generation of devices chip-select.
*/
struct pl022_config_chip {
enum ssp_interface iface;
enum ssp_hierarchy hierarchy;
bool slave_tx_disable;
struct ssp_clock_params clk_freq;
enum ssp_mode com_mode;
enum ssp_rx_level_trig rx_lev_trig;
enum ssp_tx_level_trig tx_lev_trig;
enum ssp_microwire_ctrl_len ctrl_len;
enum ssp_microwire_wait_state wait_state;
enum ssp_duplex duplex;
enum ssp_clkdelay clkdelay;
void (*cs_control) (u32 control);
};
#endif /* _SSP_PL022_H */

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#include <linux/types.h>
/* platform data for the PL061 GPIO driver */
struct pl061_platform_data {
/* number of the first GPIO */
unsigned gpio_base;
/* number of the first IRQ.
* If the IRQ functionality in not desired this must be set to 0.
*/
unsigned irq_base;
u8 directions; /* startup directions, 1: out, 0: in */
u8 values; /* startup values */
};

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/* include/linux/amba/pl080.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* ARM PrimeCell PL080 DMA controller
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Note, there are some Samsung updates to this controller block which
* make it not entierly compatible with the PL080 specification from
* ARM. When in doubt, check the Samsung documentation first.
*
* The Samsung defines are PL080S, and add an extra control register,
* the ability to move more than 2^11 counts of data and some extra
* OneNAND features.
*/
#ifndef ASM_PL080_H
#define ASM_PL080_H
#define PL080_INT_STATUS (0x00)
#define PL080_TC_STATUS (0x04)
#define PL080_TC_CLEAR (0x08)
#define PL080_ERR_STATUS (0x0C)
#define PL080_ERR_CLEAR (0x10)
#define PL080_RAW_TC_STATUS (0x14)
#define PL080_RAW_ERR_STATUS (0x18)
#define PL080_EN_CHAN (0x1c)
#define PL080_SOFT_BREQ (0x20)
#define PL080_SOFT_SREQ (0x24)
#define PL080_SOFT_LBREQ (0x28)
#define PL080_SOFT_LSREQ (0x2C)
#define PL080_CONFIG (0x30)
#define PL080_CONFIG_M2_BE (1 << 2)
#define PL080_CONFIG_M1_BE (1 << 1)
#define PL080_CONFIG_ENABLE (1 << 0)
#define PL080_SYNC (0x34)
/* Per channel configuration registers */
#define PL080_Cx_STRIDE (0x20)
#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
#define PL080_CH_SRC_ADDR (0x00)
#define PL080_CH_DST_ADDR (0x04)
#define PL080_CH_LLI (0x08)
#define PL080_CH_CONTROL (0x0C)
#define PL080_CH_CONFIG (0x10)
#define PL080S_CH_CONTROL2 (0x10)
#define PL080S_CH_CONFIG (0x14)
#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
#define PL080_LLI_ADDR_SHIFT (2)
#define PL080_LLI_LM_AHB2 (1 << 0)
#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
#define PL080_CONTROL_PROT_MASK (0x7 << 28)
#define PL080_CONTROL_PROT_SHIFT (28)
#define PL080_CONTROL_PROT_CACHE (1 << 30)
#define PL080_CONTROL_PROT_BUFF (1 << 29)
#define PL080_CONTROL_PROT_SYS (1 << 28)
#define PL080_CONTROL_DST_INCR (1 << 27)
#define PL080_CONTROL_SRC_INCR (1 << 26)
#define PL080_CONTROL_DST_AHB2 (1 << 25)
#define PL080_CONTROL_SRC_AHB2 (1 << 24)
#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
#define PL080_CONTROL_DWIDTH_SHIFT (21)
#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
#define PL080_CONTROL_SWIDTH_SHIFT (18)
#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
#define PL080_CONTROL_DB_SIZE_SHIFT (15)
#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
#define PL080_CONTROL_SB_SIZE_SHIFT (12)
#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
#define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0)
#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
#define PL080_BSIZE_1 (0x0)
#define PL080_BSIZE_4 (0x1)
#define PL080_BSIZE_8 (0x2)
#define PL080_BSIZE_16 (0x3)
#define PL080_BSIZE_32 (0x4)
#define PL080_BSIZE_64 (0x5)
#define PL080_BSIZE_128 (0x6)
#define PL080_BSIZE_256 (0x7)
#define PL080_WIDTH_8BIT (0x0)
#define PL080_WIDTH_16BIT (0x1)
#define PL080_WIDTH_32BIT (0x2)
#define PL080N_CONFIG_ITPROT (1 << 20)
#define PL080N_CONFIG_SECPROT (1 << 19)
#define PL080_CONFIG_HALT (1 << 18)
#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
#define PL080_CONFIG_LOCK (1 << 16)
#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
#define PL080_CONFIG_DST_SEL_SHIFT (6)
#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
#define PL080_CONFIG_SRC_SEL_SHIFT (1)
#define PL080_CONFIG_ENABLE (1 << 0)
#define PL080_FLOW_MEM2MEM (0x0)
#define PL080_FLOW_MEM2PER (0x1)
#define PL080_FLOW_PER2MEM (0x2)
#define PL080_FLOW_SRC2DST (0x3)
#define PL080_FLOW_SRC2DST_DST (0x4)
#define PL080_FLOW_MEM2PER_PER (0x5)
#define PL080_FLOW_PER2MEM_PER (0x6)
#define PL080_FLOW_SRC2DST_SRC (0x7)
/* DMA linked list chain structure */
struct pl080_lli {
u32 src_addr;
u32 dst_addr;
u32 next_lli;
u32 control0;
};
struct pl080s_lli {
u32 src_addr;
u32 dst_addr;
u32 next_lli;
u32 control0;
u32 control1;
};
#endif /* ASM_PL080_H */

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/*
* linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
*
* Copyright (C) 2005 ARM Ltd
* Copyright (C) 2010 ST-Ericsson SA
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* pl08x information required by platform code
*
* Please credit ARM.com
* Documentation: ARM DDI 0196D
*/
#ifndef AMBA_PL08X_H
#define AMBA_PL08X_H
/* We need sizes of structs from this header */
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
struct pl08x_driver_data;
struct pl08x_phy_chan;
struct pl08x_txd;
/* Bitmasks for selecting AHB ports for DMA transfers */
enum {
PL08X_AHB1 = (1 << 0),
PL08X_AHB2 = (1 << 1)
};
/**
* struct pl08x_channel_data - data structure to pass info between
* platform and PL08x driver regarding channel configuration
* @bus_id: name of this device channel, not just a device name since
* devices may have more than one channel e.g. "foo_tx"
* @min_signal: the minimum DMA signal number to be muxed in for this
* channel (for platforms supporting muxed signals). If you have
* static assignments, make sure this is set to the assigned signal
* number, PL08x have 16 possible signals in number 0 thru 15 so
* when these are not enough they often get muxed (in hardware)
* disabling simultaneous use of the same channel for two devices.
* @max_signal: the maximum DMA signal number to be muxed in for
* the channel. Set to the same as min_signal for
* devices with static assignments
* @muxval: a number usually used to poke into some mux regiser to
* mux in the signal to this channel
* @cctl_memcpy: options for the channel control register for memcpy
* *** not used for slave channels ***
* @addr: source/target address in physical memory for this DMA channel,
* can be the address of a FIFO register for burst requests for example.
* This can be left undefined if the PrimeCell API is used for configuring
* this.
* @single: the device connected to this channel will request single DMA
* transfers, not bursts. (Bursts are default.)
* @periph_buses: the device connected to this channel is accessible via
* these buses (use PL08X_AHB1 | PL08X_AHB2).
*/
struct pl08x_channel_data {
const char *bus_id;
int min_signal;
int max_signal;
u32 muxval;
u32 cctl_memcpy;
dma_addr_t addr;
bool single;
u8 periph_buses;
};
/**
* struct pl08x_platform_data - the platform configuration for the PL08x
* PrimeCells.
* @slave_channels: the channels defined for the different devices on the
* platform, all inclusive, including multiplexed channels. The available
* physical channels will be multiplexed around these signals as they are
* requested, just enumerate all possible channels.
* @get_xfer_signal: request a physical signal to be used for a DMA transfer
* immediately: if there is some multiplexing or similar blocking the use
* of the channel the transfer can be denied by returning less than zero,
* else it returns the allocated signal number
* @put_xfer_signal: indicate to the platform that this physical signal is not
* running any DMA transfer and multiplexing can be recycled
* @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
* @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
*/
struct pl08x_platform_data {
const struct pl08x_channel_data *slave_channels;
unsigned int num_slave_channels;
struct pl08x_channel_data memcpy_channel;
int (*get_xfer_signal)(const struct pl08x_channel_data *);
void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
u8 lli_buses;
u8 mem_buses;
};
#ifdef CONFIG_AMBA_PL08X
bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
#else
static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
{
return false;
}
#endif
#endif /* AMBA_PL08X_H */

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/* linux/amba/pl093.h
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* AMBA PL093 SSMC (synchronous static memory controller)
* See DDI0236.pdf (r0p4) for more details
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
/* Offsets for SMBxxxxRy registers */
#define SMBIDCYR (0x00)
#define SMBWSTRDR (0x04)
#define SMBWSTWRR (0x08)
#define SMBWSTOENR (0x0C)
#define SMBWSTWENR (0x10)
#define SMBCR (0x14)
#define SMBSR (0x18)
#define SMBWSTBRDR (0x1C)
/* Masks for SMB registers */
#define IDCY_MASK (0xf)
#define WSTRD_MASK (0xf)
#define WSTWR_MASK (0xf)
#define WSTOEN_MASK (0xf)
#define WSTWEN_MASK (0xf)
/* Notes from datasheet:
* WSTOEN <= WSTRD
* WSTWEN <= WSTWR
*
* WSTOEN is not used with nWAIT
*/
/* SMBCR bit definitions */
#define SMBCR_BIWRITEEN (1 << 21)
#define SMBCR_ADDRVALIDWRITEEN (1 << 20)
#define SMBCR_SYNCWRITE (1 << 17)
#define SMBCR_BMWRITE (1 << 16)
#define SMBCR_WRAPREAD (1 << 14)
#define SMBCR_BIREADEN (1 << 13)
#define SMBCR_ADDRVALIDREADEN (1 << 12)
#define SMBCR_SYNCREAD (1 << 9)
#define SMBCR_BMREAD (1 << 8)
#define SMBCR_SMBLSPOL (1 << 6)
#define SMBCR_WP (1 << 3)
#define SMBCR_WAITEN (1 << 2)
#define SMBCR_WAITPOL (1 << 1)
#define SMBCR_RBLE (1 << 0)
#define SMBCR_BURSTLENWRITE_MASK (3 << 18)
#define SMBCR_BURSTLENWRITE_4 (0 << 18)
#define SMBCR_BURSTLENWRITE_8 (1 << 18)
#define SMBCR_BURSTLENWRITE_RESERVED (2 << 18)
#define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18)
#define SMBCR_BURSTLENREAD_MASK (3 << 10)
#define SMBCR_BURSTLENREAD_4 (0 << 10)
#define SMBCR_BURSTLENREAD_8 (1 << 10)
#define SMBCR_BURSTLENREAD_16 (2 << 10)
#define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10)
#define SMBCR_MW_MASK (3 << 4)
#define SMBCR_MW_8BIT (0 << 4)
#define SMBCR_MW_16BIT (1 << 4)
#define SMBCR_MW_M32BIT (2 << 4)
/* SSMC status registers */
#define SSMCCSR (0x200)
#define SSMCCR (0x204)
#define SSMCITCR (0x208)
#define SSMCITIP (0x20C)
#define SSMCITIOP (0x210)

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/* linux/include/linux/amba/pl330.h
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __AMBA_PL330_H_
#define __AMBA_PL330_H_
#include <linux/dmaengine.h>
struct dma_pl330_platdata {
/*
* Number of valid peripherals connected to DMAC.
* This may be different from the value read from
* CR0, as the PL330 implementation might have 'holes'
* in the peri list or the peri could also be reached
* from another DMAC which the platform prefers.
*/
u8 nr_valid_peri;
/* Array of valid peripherals */
u8 *peri_id;
/* Operational capabilities */
dma_cap_mask_t cap_mask;
/* Bytes to allocate for MC buffer */
unsigned mcbuf_sz;
};
extern bool pl330_filter(struct dma_chan *chan, void *param);
extern int pl330_dma_getposition(struct dma_chan *chan,
dma_addr_t *src, dma_addr_t *dst);
#endif /* __AMBA_PL330_H_ */

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/*
* linux/include/asm-arm/hardware/serial_amba.h
*
* Internal header file for AMBA serial ports
*
* Copyright (C) ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
#include <linux/types.h>
/* -------------------------------------------------------------------------------
* From AMBA UART (PL010) Block Specification
* -------------------------------------------------------------------------------
* UART Register Offsets.
*/
#define UART01x_DR 0x00 /* Data read or written from the interface. */
#define UART01x_RSR 0x04 /* Receive status register (Read). */
#define UART01x_ECR 0x04 /* Error clear register (Write). */
#define UART010_LCRH 0x08 /* Line control register, high byte. */
#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
#define UART010_LCRM 0x0C /* Line control register, middle byte. */
#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
#define UART010_LCRL 0x10 /* Line control register, low byte. */
#define UART010_CR 0x14 /* Control register. */
#define UART01x_FR 0x18 /* Flag register (Read only). */
#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
#define UART011_LCRH 0x2c /* Line control register. */
#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
#define UART011_CR 0x30 /* Control register. */
#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
#define UART011_IMSC 0x38 /* Interrupt mask. */
#define UART011_RIS 0x3c /* Raw interrupt status. */
#define UART011_MIS 0x40 /* Masked interrupt status. */
#define UART011_ICR 0x44 /* Interrupt clear register. */
#define UART011_DMACR 0x48 /* DMA control register. */
#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
#define ST_UART011_XON1 0x54 /* XON1 register. */
#define ST_UART011_XON2 0x58 /* XON2 register. */
#define ST_UART011_XOFF1 0x5C /* XON1 register. */
#define ST_UART011_XOFF2 0x60 /* XON2 register. */
#define ST_UART011_ITCR 0x80 /* Integration test control register. */
#define ST_UART011_ITIP 0x84 /* Integration test input register. */
#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
#define UART011_DR_OE (1 << 11)
#define UART011_DR_BE (1 << 10)
#define UART011_DR_PE (1 << 9)
#define UART011_DR_FE (1 << 8)
#define UART01x_RSR_OE 0x08
#define UART01x_RSR_BE 0x04
#define UART01x_RSR_PE 0x02
#define UART01x_RSR_FE 0x01
#define UART011_FR_RI 0x100
#define UART011_FR_TXFE 0x080
#define UART011_FR_RXFF 0x040
#define UART01x_FR_TXFF 0x020
#define UART01x_FR_RXFE 0x010
#define UART01x_FR_BUSY 0x008
#define UART01x_FR_DCD 0x004
#define UART01x_FR_DSR 0x002
#define UART01x_FR_CTS 0x001
#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
#define UART011_CR_OUT2 0x2000 /* OUT2 */
#define UART011_CR_OUT1 0x1000 /* OUT1 */
#define UART011_CR_RTS 0x0800 /* RTS */
#define UART011_CR_DTR 0x0400 /* DTR */
#define UART011_CR_RXE 0x0200 /* receive enable */
#define UART011_CR_TXE 0x0100 /* transmit enable */
#define UART011_CR_LBE 0x0080 /* loopback enable */
#define UART010_CR_RTIE 0x0040
#define UART010_CR_TIE 0x0020
#define UART010_CR_RIE 0x0010
#define UART010_CR_MSIE 0x0008
#define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */
#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
#define UART01x_CR_SIREN 0x0002 /* SIR enable */
#define UART01x_CR_UARTEN 0x0001 /* UART enable */
#define UART011_LCRH_SPS 0x80
#define UART01x_LCRH_WLEN_8 0x60
#define UART01x_LCRH_WLEN_7 0x40
#define UART01x_LCRH_WLEN_6 0x20
#define UART01x_LCRH_WLEN_5 0x00
#define UART01x_LCRH_FEN 0x10
#define UART01x_LCRH_STP2 0x08
#define UART01x_LCRH_EPS 0x04
#define UART01x_LCRH_PEN 0x02
#define UART01x_LCRH_BRK 0x01
#define ST_UART011_DMAWM_RX_1 (0 << 3)
#define ST_UART011_DMAWM_RX_2 (1 << 3)
#define ST_UART011_DMAWM_RX_4 (2 << 3)
#define ST_UART011_DMAWM_RX_8 (3 << 3)
#define ST_UART011_DMAWM_RX_16 (4 << 3)
#define ST_UART011_DMAWM_RX_32 (5 << 3)
#define ST_UART011_DMAWM_RX_48 (6 << 3)
#define ST_UART011_DMAWM_TX_1 0
#define ST_UART011_DMAWM_TX_2 1
#define ST_UART011_DMAWM_TX_4 2
#define ST_UART011_DMAWM_TX_8 3
#define ST_UART011_DMAWM_TX_16 4
#define ST_UART011_DMAWM_TX_32 5
#define ST_UART011_DMAWM_TX_48 6
#define UART010_IIR_RTIS 0x08
#define UART010_IIR_TIS 0x04
#define UART010_IIR_RIS 0x02
#define UART010_IIR_MIS 0x01
#define UART011_IFLS_RX1_8 (0 << 3)
#define UART011_IFLS_RX2_8 (1 << 3)
#define UART011_IFLS_RX4_8 (2 << 3)
#define UART011_IFLS_RX6_8 (3 << 3)
#define UART011_IFLS_RX7_8 (4 << 3)
#define UART011_IFLS_TX1_8 (0 << 0)
#define UART011_IFLS_TX2_8 (1 << 0)
#define UART011_IFLS_TX4_8 (2 << 0)
#define UART011_IFLS_TX6_8 (3 << 0)
#define UART011_IFLS_TX7_8 (4 << 0)
/* special values for ST vendor with deeper fifo */
#define UART011_IFLS_RX_HALF (5 << 3)
#define UART011_IFLS_TX_HALF (5 << 0)
#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
#define UART011_BEIM (1 << 9) /* break error interrupt mask */
#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
#define UART011_RXIM (1 << 4) /* receive interrupt mask */
#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
#define UART011_BEIS (1 << 9) /* break error interrupt status */
#define UART011_PEIS (1 << 8) /* parity error interrupt status */
#define UART011_FEIS (1 << 7) /* framing error interrupt status */
#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
#define UART011_TXIS (1 << 5) /* transmit interrupt status */
#define UART011_RXIS (1 << 4) /* receive interrupt status */
#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
#define UART011_RIMIS (1 << 0) /* RI interrupt status */
#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
#define UART011_BEIC (1 << 9) /* break error interrupt clear */
#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
#define UART011_RXIC (1 << 4) /* receive interrupt clear */
#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
#define UART011_DMAONERR (1 << 2) /* disable dma on error */
#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
#define UART011_RXDMAE (1 << 0) /* enable receive dma */
#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
#ifndef __ASSEMBLY__
struct amba_device; /* in uncompress this is included but amba/bus.h is not */
struct amba_pl010_data {
void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
};
struct dma_chan;
struct amba_pl011_data {
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
void *dma_rx_param;
void *dma_tx_param;
bool dma_rx_poll_enable;
unsigned int dma_rx_poll_rate;
unsigned int dma_rx_poll_timeout;
void (*init) (void);
void (*exit) (void);
};
#endif
#endif

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/*
* ARM PrimeXsys System Controller SP810 header file
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __AMBA_SP810_H
#define __AMBA_SP810_H
#include <linux/io.h>
/* sysctl registers offset */
#define SCCTRL 0x000
#define SCSYSSTAT 0x004
#define SCIMCTRL 0x008
#define SCIMSTAT 0x00C
#define SCXTALCTRL 0x010
#define SCPLLCTRL 0x014
#define SCPLLFCTRL 0x018
#define SCPERCTRL0 0x01C
#define SCPERCTRL1 0x020
#define SCPEREN 0x024
#define SCPERDIS 0x028
#define SCPERCLKEN 0x02C
#define SCPERSTAT 0x030
#define SCSYSID0 0xEE0
#define SCSYSID1 0xEE4
#define SCSYSID2 0xEE8
#define SCSYSID3 0xEEC
#define SCITCR 0xF00
#define SCITIR0 0xF04
#define SCITIR1 0xF08
#define SCITOR 0xF0C
#define SCCNTCTRL 0xF10
#define SCCNTDATA 0xF14
#define SCCNTSTEP 0xF18
#define SCPERIPHID0 0xFE0
#define SCPERIPHID1 0xFE4
#define SCPERIPHID2 0xFE8
#define SCPERIPHID3 0xFEC
#define SCPCELLID0 0xFF0
#define SCPCELLID1 0xFF4
#define SCPCELLID2 0xFF8
#define SCPCELLID3 0xFFC
#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
static inline void sysctl_soft_reset(void __iomem *base)
{
/* switch to slow mode */
writel(0x2, base + SCCTRL);
/* writing any value to SCSYSSTAT reg will reset system */
writel(0, base + SCSYSSTAT);
}
#endif /* __AMBA_SP810_H */

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/*
* Xilinx DMA Engine drivers support header file
*
* Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DMA_XILINX_DMA_H
#define __DMA_XILINX_DMA_H
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
/**
* struct xilinx_vdma_config - VDMA Configuration structure
* @frm_dly: Frame delay
* @gen_lock: Whether in gen-lock mode
* @master: Master that it syncs to
* @frm_cnt_en: Enable frame count enable
* @park: Whether wants to park
* @park_frm: Frame to park on
* @coalesc: Interrupt coalescing threshold
* @delay: Delay counter
* @reset: Reset Channel
* @ext_fsync: External Frame Sync source
*/
struct xilinx_vdma_config {
int frm_dly;
int gen_lock;
int master;
int frm_cnt_en;
int park;
int park_frm;
int coalesc;
int delay;
int reset;
int ext_fsync;
};
int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
struct xilinx_vdma_config *cfg);
#endif

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/*
* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
* Author: Joerg Roedel <joerg.roedel@amd.com>
* Leo Duran <leo.duran@amd.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_X86_AMD_IOMMU_H
#define _ASM_X86_AMD_IOMMU_H
#include <linux/types.h>
#ifdef CONFIG_AMD_IOMMU
struct task_struct;
struct pci_dev;
extern int amd_iommu_detect(void);
extern int amd_iommu_init_hardware(void);
/**
* amd_iommu_enable_device_erratum() - Enable erratum workaround for device
* in the IOMMUv2 driver
* @pdev: The PCI device the workaround is necessary for
* @erratum: The erratum workaround to enable
*
* The function needs to be called before amd_iommu_init_device().
* Possible values for the erratum number are for now:
* - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
* is enabled
* - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
* requests to one
*/
#define AMD_PRI_DEV_ERRATUM_ENABLE_RESET 0
#define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE 1
extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
/**
* amd_iommu_init_device() - Init device for use with IOMMUv2 driver
* @pdev: The PCI device to initialize
* @pasids: Number of PASIDs to support for this device
*
* This function does all setup for the device pdev so that it can be
* used with IOMMUv2.
* Returns 0 on success or negative value on error.
*/
extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
/**
* amd_iommu_free_device() - Free all IOMMUv2 related device resources
* and disable IOMMUv2 usage for this device
* @pdev: The PCI device to disable IOMMUv2 usage for'
*/
extern void amd_iommu_free_device(struct pci_dev *pdev);
/**
* amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
* @pdev: The PCI device to bind the task to
* @pasid: The PASID on the device the task should be bound to
* @task: the task to bind
*
* The function returns 0 on success or a negative value on error.
*/
extern int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
struct task_struct *task);
/**
* amd_iommu_unbind_pasid() - Unbind a PASID from its task on
* a device
* @pdev: The device of the PASID
* @pasid: The PASID to unbind
*
* When this function returns the device is no longer using the PASID
* and the PASID is no longer bound to its task.
*/
extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid);
/**
* amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
* PRI requests
* @pdev: The PCI device the call-back should be registered for
* @cb: The call-back function
*
* The IOMMUv2 driver invokes this call-back when it is unable to
* successfully handle a PRI request. The device driver can then decide
* which PRI response the device should see. Possible return values for
* the call-back are:
*
* - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
* - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
* - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
* the device is required to disable
* PRI when it receives this response
*
* The function returns 0 on success or negative value on error.
*/
#define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
#define AMD_IOMMU_INV_PRI_RSP_INVALID 1
#define AMD_IOMMU_INV_PRI_RSP_FAIL 2
typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
int pasid,
unsigned long address,
u16);
extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
amd_iommu_invalid_ppr_cb cb);
#define PPR_FAULT_EXEC (1 << 1)
#define PPR_FAULT_READ (1 << 2)
#define PPR_FAULT_WRITE (1 << 5)
#define PPR_FAULT_USER (1 << 6)
#define PPR_FAULT_RSVD (1 << 7)
#define PPR_FAULT_GN (1 << 8)
/**
* amd_iommu_device_info() - Get information about IOMMUv2 support of a
* PCI device
* @pdev: PCI device to query information from
* @info: A pointer to an amd_iommu_device_info structure which will contain
* the information about the PCI device
*
* Returns 0 on success, negative value on error
*/
#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
on memory pages */
#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
super-user privileges */
struct amd_iommu_device_info {
int max_pasids;
u32 flags;
};
extern int amd_iommu_device_info(struct pci_dev *pdev,
struct amd_iommu_device_info *info);
/**
* amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
* a pasid context. This call-back is
* invoked when the IOMMUv2 driver needs to
* invalidate a PASID context, for example
* because the task that is bound to that
* context is about to exit.
*
* @pdev: The PCI device the call-back should be registered for
* @cb: The call-back function
*/
typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, int pasid);
extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
amd_iommu_invalidate_ctx cb);
#else
static inline int amd_iommu_detect(void) { return -ENODEV; }
#endif
#endif /* _ASM_X86_AMD_IOMMU_H */

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#ifndef _AMIFD_H
#define _AMIFD_H
/* Definitions for the Amiga floppy driver */
#include <linux/fd.h>
#define FD_MAX_UNITS 4 /* Max. Number of drives */
#define FLOPPY_MAX_SECTORS 22 /* Max. Number of sectors per track */
#ifndef ASSEMBLER
struct fd_data_type {
char *name; /* description of data type */
int sects; /* sectors per track */
#ifdef __STDC__
int (*read_fkt)(int);
void (*write_fkt)(int);
#else
int (*read_fkt)(); /* read whole track */
void (*write_fkt)(); /* write whole track */
#endif
};
/*
** Floppy type descriptions
*/
struct fd_drive_type {
unsigned long code; /* code returned from drive */
char *name; /* description of drive */
unsigned int tracks; /* number of tracks */
unsigned int heads; /* number of heads */
unsigned int read_size; /* raw read size for one track */
unsigned int write_size; /* raw write size for one track */
unsigned int sect_mult; /* sectors and gap multiplier (HD = 2) */
unsigned int precomp1; /* start track for precomp 1 */
unsigned int precomp2; /* start track for precomp 2 */
unsigned int step_delay; /* time (in ms) for delay after step */
unsigned int settle_time; /* time to settle after dir change */
unsigned int side_time; /* time needed to change sides */
};
struct amiga_floppy_struct {
struct fd_drive_type *type; /* type of floppy for this unit */
struct fd_data_type *dtype; /* type of floppy for this unit */
int track; /* current track (-1 == unknown) */
unsigned char *trackbuf; /* current track (kmaloc()'d */
int blocks; /* total # blocks on disk */
int changed; /* true when not known */
int disk; /* disk in drive (-1 == unknown) */
int motor; /* true when motor is at speed */
int busy; /* true when drive is active */
int dirty; /* true when trackbuf is not on disk */
int status; /* current error code for unit */
struct gendisk *gendisk;
};
#endif
#endif

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#ifndef _LINUX_AMIFDREG_H
#define _LINUX_AMIFDREG_H
/*
** CIAAPRA bits (read only)
*/
#define DSKRDY (0x1<<5) /* disk ready when low */
#define DSKTRACK0 (0x1<<4) /* head at track zero when low */
#define DSKPROT (0x1<<3) /* disk protected when low */
#define DSKCHANGE (0x1<<2) /* low when disk removed */
/*
** CIAAPRB bits (read/write)
*/
#define DSKMOTOR (0x1<<7) /* motor on when low */
#define DSKSEL3 (0x1<<6) /* select drive 3 when low */
#define DSKSEL2 (0x1<<5) /* select drive 2 when low */
#define DSKSEL1 (0x1<<4) /* select drive 1 when low */
#define DSKSEL0 (0x1<<3) /* select drive 0 when low */
#define DSKSIDE (0x1<<2) /* side selection: 0 = upper, 1 = lower */
#define DSKDIREC (0x1<<1) /* step direction: 0=in, 1=out (to trk 0) */
#define DSKSTEP (0x1) /* pulse low to step head 1 track */
/*
** DSKBYTR bits (read only)
*/
#define DSKBYT (1<<15) /* register contains valid byte when set */
#define DMAON (1<<14) /* disk DMA enabled */
#define DISKWRITE (1<<13) /* disk write bit in DSKLEN enabled */
#define WORDEQUAL (1<<12) /* DSKSYNC register match when true */
/* bits 7-0 are data */
/*
** ADKCON/ADKCONR bits
*/
#ifndef SETCLR
#define ADK_SETCLR (1<<15) /* control bit */
#endif
#define ADK_PRECOMP1 (1<<14) /* precompensation selection */
#define ADK_PRECOMP0 (1<<13) /* 00=none, 01=140ns, 10=280ns, 11=500ns */
#define ADK_MFMPREC (1<<12) /* 0=GCR precomp., 1=MFM precomp. */
#define ADK_WORDSYNC (1<<10) /* enable DSKSYNC auto DMA */
#define ADK_MSBSYNC (1<<9) /* when 1, enable sync on MSbit (for GCR) */
#define ADK_FAST (1<<8) /* bit cell: 0=2us (GCR), 1=1us (MFM) */
/*
** DSKLEN bits
*/
#define DSKLEN_DMAEN (1<<15)
#define DSKLEN_WRITE (1<<14)
/*
** INTENA/INTREQ bits
*/
#define DSKINDEX (0x1<<4) /* DSKINDEX bit */
/*
** Misc
*/
#define MFM_SYNC 0x4489 /* standard MFM sync value */
/* Values for FD_COMMAND */
#define FD_RECALIBRATE 0x07 /* move to track 0 */
#define FD_SEEK 0x0F /* seek track */
#define FD_READ 0xE6 /* read with MT, MFM, SKip deleted */
#define FD_WRITE 0xC5 /* write with MT, MFM */
#define FD_SENSEI 0x08 /* Sense Interrupt Status */
#define FD_SPECIFY 0x03 /* specify HUT etc */
#define FD_FORMAT 0x4D /* format one track */
#define FD_VERSION 0x10 /* get version code */
#define FD_CONFIGURE 0x13 /* configure FIFO operation */
#define FD_PERPENDICULAR 0x12 /* perpendicular r/w mode */
#endif /* _LINUX_AMIFDREG_H */

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#ifndef AMIGAFFS_H
#define AMIGAFFS_H
#include <linux/types.h>
#include <asm/byteorder.h>
#define FS_OFS 0x444F5300
#define FS_FFS 0x444F5301
#define FS_INTLOFS 0x444F5302
#define FS_INTLFFS 0x444F5303
#define FS_DCOFS 0x444F5304
#define FS_DCFFS 0x444F5305
#define MUFS_FS 0x6d754653 /* 'muFS' */
#define MUFS_OFS 0x6d754600 /* 'muF\0' */
#define MUFS_FFS 0x6d754601 /* 'muF\1' */
#define MUFS_INTLOFS 0x6d754602 /* 'muF\2' */
#define MUFS_INTLFFS 0x6d754603 /* 'muF\3' */
#define MUFS_DCOFS 0x6d754604 /* 'muF\4' */
#define MUFS_DCFFS 0x6d754605 /* 'muF\5' */
#define T_SHORT 2
#define T_LIST 16
#define T_DATA 8
#define ST_LINKFILE -4
#define ST_FILE -3
#define ST_ROOT 1
#define ST_USERDIR 2
#define ST_SOFTLINK 3
#define ST_LINKDIR 4
#define AFFS_ROOT_BMAPS 25
struct affs_date {
__be32 days;
__be32 mins;
__be32 ticks;
};
struct affs_short_date {
__be16 days;
__be16 mins;
__be16 ticks;
};
struct affs_root_head {
__be32 ptype;
__be32 spare1;
__be32 spare2;
__be32 hash_size;
__be32 spare3;
__be32 checksum;
__be32 hashtable[1];
};
struct affs_root_tail {
__be32 bm_flag;
__be32 bm_blk[AFFS_ROOT_BMAPS];
__be32 bm_ext;
struct affs_date root_change;
u8 disk_name[32];
__be32 spare1;
__be32 spare2;
struct affs_date disk_change;
struct affs_date disk_create;
__be32 spare3;
__be32 spare4;
__be32 dcache;
__be32 stype;
};
struct affs_head {
__be32 ptype;
__be32 key;
__be32 block_count;
__be32 spare1;
__be32 first_data;
__be32 checksum;
__be32 table[1];
};
struct affs_tail {
__be32 spare1;
__be16 uid;
__be16 gid;
__be32 protect;
__be32 size;
u8 comment[92];
struct affs_date change;
u8 name[32];
__be32 spare2;
__be32 original;
__be32 link_chain;
__be32 spare[5];
__be32 hash_chain;
__be32 parent;
__be32 extension;
__be32 stype;
};
struct slink_front
{
__be32 ptype;
__be32 key;
__be32 spare1[3];
__be32 checksum;
u8 symname[1]; /* depends on block size */
};
struct affs_data_head
{
__be32 ptype;
__be32 key;
__be32 sequence;
__be32 size;
__be32 next;
__be32 checksum;
u8 data[1]; /* depends on block size */
};
/* Permission bits */
#define FIBF_OTR_READ 0x8000
#define FIBF_OTR_WRITE 0x4000
#define FIBF_OTR_EXECUTE 0x2000
#define FIBF_OTR_DELETE 0x1000
#define FIBF_GRP_READ 0x0800
#define FIBF_GRP_WRITE 0x0400
#define FIBF_GRP_EXECUTE 0x0200
#define FIBF_GRP_DELETE 0x0100
#define FIBF_HIDDEN 0x0080
#define FIBF_SCRIPT 0x0040
#define FIBF_PURE 0x0020 /* no use under linux */
#define FIBF_ARCHIVED 0x0010 /* never set, always cleared on write */
#define FIBF_NOREAD 0x0008 /* 0 means allowed */
#define FIBF_NOWRITE 0x0004 /* 0 means allowed */
#define FIBF_NOEXECUTE 0x0002 /* 0 means allowed, ignored under linux */
#define FIBF_NODELETE 0x0001 /* 0 means allowed */
#define FIBF_OWNER 0x000F /* Bits pertaining to owner */
#define FIBF_MASK 0xEE0E /* Bits modified by Linux */
#endif

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/* include/linux/android_aid.h
*
* Copyright (C) 2008 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _LINUX_ANDROID_AID_H
#define _LINUX_ANDROID_AID_H
/* AIDs that the kernel treats differently */
#define AID_SYSTEM KGIDT_INIT(1000) /* system server */
#define AID_OBSOLETE_000 KGIDT_INIT(3001) /* was NET_BT_ADMIN */
#define AID_OBSOLETE_001 KGIDT_INIT(3002) /* was NET_BT */
#define AID_INET KGIDT_INIT(3003)
#define AID_NET_RAW KGIDT_INIT(3004)
#define AID_NET_ADMIN KGIDT_INIT(3005)
#define AID_NET_BW_STATS KGIDT_INIT(3006) /* read bandwidth statistics */
#define AID_NET_BW_ACCT KGIDT_INIT(3007) /* change bandwidth statistics accounting */
#endif

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/*
* include/linux/anon_inodes.h
*
* Copyright (C) 2007 Davide Libenzi <davidel@xmailserver.org>
*
*/
#ifndef _LINUX_ANON_INODES_H
#define _LINUX_ANON_INODES_H
struct file_operations;
struct file *anon_inode_getfile(const char *name,
const struct file_operations *fops,
void *priv, int flags);
int anon_inode_getfd(const char *name, const struct file_operations *fops,
void *priv, int flags);
#endif /* _LINUX_ANON_INODES_H */

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/* -*- linux-c -*-
*
* (C) 2003 zecke@handhelds.org
*
* GPL version 2
*
* based on arch/arm/kernel/apm.c
* factor out the information needed by architectures to provide
* apm status
*/
#ifndef __LINUX_APM_EMULATION_H
#define __LINUX_APM_EMULATION_H
#include <linux/apm_bios.h>
/*
* This structure gets filled in by the machine specific 'get_power_status'
* implementation. Any fields which are not set default to a safe value.
*/
struct apm_power_info {
unsigned char ac_line_status;
#define APM_AC_OFFLINE 0
#define APM_AC_ONLINE 1
#define APM_AC_BACKUP 2
#define APM_AC_UNKNOWN 0xff
unsigned char battery_status;
#define APM_BATTERY_STATUS_HIGH 0
#define APM_BATTERY_STATUS_LOW 1
#define APM_BATTERY_STATUS_CRITICAL 2
#define APM_BATTERY_STATUS_CHARGING 3
#define APM_BATTERY_STATUS_NOT_PRESENT 4
#define APM_BATTERY_STATUS_UNKNOWN 0xff
unsigned char battery_flag;
#define APM_BATTERY_FLAG_HIGH (1 << 0)
#define APM_BATTERY_FLAG_LOW (1 << 1)
#define APM_BATTERY_FLAG_CRITICAL (1 << 2)
#define APM_BATTERY_FLAG_CHARGING (1 << 3)
#define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7)
#define APM_BATTERY_FLAG_UNKNOWN 0xff
int battery_life;
int time;
int units;
#define APM_UNITS_MINS 0
#define APM_UNITS_SECS 1
#define APM_UNITS_UNKNOWN -1
};
/*
* This allows machines to provide their own "apm get power status" function.
*/
extern void (*apm_get_power_status)(struct apm_power_info *);
/*
* Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
*/
void apm_queue_event(apm_event_t event);
#endif /* __LINUX_APM_EMULATION_H */

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/* arch/arm64/mach-exynos/include/mach/apm-exynos.h
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* APM register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_APM_H
#define __ASM_ARCH_REGS_APM_H __FILE__
#include <linux/regmap.h>
#include <linux/types.h>
#include <linux/file.h>
#include <linux/fs.h>
/* Margin related variables */
#define MARGIN_0MV (0)
#define MARGIN_6_25MV (1)
#define MARGIN_12_5MV (2)
#define MARGIN_18_75MV (3)
#define MARGIN_25MV (4)
#define MARGIN_31_25MV (5)
#define MARGIN_37_5MV (6)
#define MARGIN_43_75MV (7)
#define MARGIN_50MV (8)
#define MARGIN_56_25MV (9)
#define MARGIN_62_5MV (0xA)
#define MARGIN_68_75MV (0xB)
#define MARGIN_75MV (0xC)
#define MARGIN_81_25MV (0xD)
#define MARGIN_87_5MV (0xE)
#define MARGIN_93_75MV (0xF)
/* PERIOD related variables */
#define PERIOD_1MS (0)
#define PERIOD_5MS (1)
/* APM Protocol related variables */
/* Notifier variables */
#define APM_READY (0x0001)
#define APM_SLEEP (0x0002)
#define APM_TIMEOUT (0x0003)
#define CL_ENABLE (0x0004)
#define CL_DISABLE (0x0005)
/* Shift variables */
#define CL_DVFS_SHIFT (29)
#define COMMAND_SHIFT (27)
#define PM_SECTION_SHIFT (26)
#define MASK_SHIFT (25)
#define INIT_MODE_SHIFT (22)
#define ASV_MODE_SHIFT (21)
#define CL_ALL_STOP_SHIFT (30)
#define CL_ALL_START_SHIFT (31)
#define MULTI_BYTE_SHIFT (16)
#define CL_DOMAIN_SHIFT (14)
#define MULTI_BYTE_CNT_SHIFT (16)
#define ATLAS_SHIFT (0)
#define APOLLO_SHIFT (4)
#define G3D_SHIFT (8)
#define MIF_SHIFT (12)
#define PERIOD_SHIFT (16)
#define BYTE_SHIFT (8)
#define BYTE_MASK (0xFF)
#define WRITE_MODE (0)
#define READ_MODE (1)
#define NONE (2)
#define TX_INTERRUPT_ENABLE (1)
#define MASK (1)
#define BYTE_4 (4)
#define INIT_SET (1)
#define ASV_SET (1)
#define DEBUG_COUNT (10)
/* Mask variables */
#define CL_DVFS_MASK (1)
#define COMMAND_MASK (0x3)
#define MULTI_BYTE_MASK (0xF)
#define CL_DVFS (CL_DVFS_MASK << CL_DVFS_SHIFT)
#define CL_DVFS_OFF (0)
#define COMMAND (COMMAND_MASK << COMMAND_SHIFT)
#define MULTI_BYTE (MULTI_BYTE_MASK << MULTI_BYTE_SHIFT)
/* Error variable */
#define APM_RET_SUCESS (0xa)
#define APM_GPIO_ERR (0xFFFFFFFF)
#define PMIC_NO_ACK_ERR (0xEEEEEEEE)
#define ERR_TIMEOUT (1)
#define ERR_RETRY (2)
#define ERR_OUT (3)
#define RETRY_ERR (-0xFF)
/* apm related variables */
#define G3D_LV_OFFSET (3)
#define MBOX_LEN (4)
#define TIMEOUT (500) /* timeout 500 msec */
#define TX (0)
#define RX (1)
#define HSI2C_MODE (0)
#define APM_MODE (1)
#define APM_TIMOUT (2)
#define CL_ON (1)
#define CL_OFF (0)
#define APM_OFF (0)
#define APM_ON (1)
#define APM_WFI_TIMEOUT (2)
#define EXYNOS_PMU_CORTEXM3_APM_CONFIGURATION (0x2500)
#define EXYNOS_PMU_CORTEXM3_APM_STATUS (0x2504)
#define EXYNOS_PMU_CORTEXM3_APM_OPTION (0x2508)
#define EXYNOS_PMU_CORTEXM3_APM_DURATION0 (0x2510)
#define EXYNOS_PMU_CORTEXM3_APM_DURATION1 (0x2514)
#define EXYNOS_PMU_CORTEXM3_APM_DURATION2 (0x2518)
#define EXYNOS_PMU_CORTEXM3_APM_DURATION3 (0x251C)
/* CORTEX M3 */
#define ENABLE_APM (0x1 << 15)
#define APM_STATUS_MASK (0x1)
#define STANDBYWFI (28)
#define STANDBYWFI_MASK (0x1)
#define APM_LOCAL_PWR_CFG_RUN (0x1 << 0)
#define APM_LOCAL_PWR_CFG_RESET (~(0x1 << 0))
struct apm_ops {
int (*apm_update_bits) (unsigned int type, unsigned int reg,
unsigned int mask, unsigned int value);
int (*apm_write) (unsigned int type, unsigned int reg, unsigned int value);
int (*apm_bulk_write) (unsigned int type, unsigned char reg,
unsigned char *buf, unsigned int count);
int (*apm_read) (unsigned int type, unsigned int reg, unsigned int *val);
int (*apm_bulk_read) (unsigned int type, unsigned char reg,
unsigned char *buf, unsigned int count);
};
struct cl_ops {
void (*apm_reset) (void);
void (*apm_power_up) (void);
void (*apm_power_down) (void);
int (*cl_dvfs_setup) (unsigned int atlas_cl_limit, unsigned int apollo_cl_limit,
unsigned int g3d_cl_limit, unsigned int mif_cl_limit, unsigned int cl_period);
int (*cl_dvfs_start) (unsigned int cl_domain);
int (*cl_dvfs_stop) (unsigned int cl_domain, unsigned int level);
int (*cl_dvfs_enable) (void);
int (*cl_dvfs_disable) (void);
int (*g3d_power_on) (void);
int (*g3d_power_down) (void);
int (*enter_wfi) (void);
};
struct debug_data {
u32 buf[DEBUG_COUNT][5];
s64 time[DEBUG_COUNT];
char* name[DEBUG_COUNT];
unsigned int cnt;
#ifdef CONFIG_EXYNOS_APM_VOLTAGE_DEBUG
u32 vol[DEBUG_COUNT][4];
u32 atl_value;
u32 apo_value;
u32 g3d_value;
u32 mif_value;
#endif
};
struct cl_init_data {
u32 atlas_margin;
u32 apollo_margin;
u32 g3d_margin;
u32 mif_margin;
u32 period;
u32 cl_status;
u32 apm_status;
};
extern void cl_dvfs_lock(void);
extern void cl_dvfs_unlock(void);
extern int cm3_status_open(struct inode *inode, struct file *file);
extern struct apm_ops exynos_apm_function_ops;
extern int register_apm_notifier(struct notifier_block *nb);
extern int unregister_apm_notifier(struct notifier_block *nb);
extern int apm_notifier_call_chain(unsigned long val);
extern void exynos_apm_reset_release(void);
extern void exynos_apm_power_up(void);
extern void exynos_apm_power_down(void);
extern int exynos_cl_dvfs_setup(unsigned int atlas_cl_limit, unsigned int apollo_cl_limit, unsigned int g3d_cl_limit,
unsigned int mif_cl_limit, unsigned int cl_period);
extern int exynos_cl_dvfs_start(unsigned int cl_domain);
extern int exynos_cl_dvfs_stop(unsigned int cl_domain, unsigned int level);
extern int exynos_cl_dvfs_mode_enable(void);
extern int exynos_cl_dvfs_mode_disable(void);
extern int exynos_g3d_power_on_noti_apm(void);
extern int exynos_g3d_power_down_noti_apm(void);
extern int exynos_apm_enter_wfi(void);
extern int exynos_apm_update_bits(unsigned int type, unsigned int reg, unsigned int mask, unsigned int value);
extern int exynos_apm_write(unsigned int type, unsigned int address, unsigned int value);
extern int exynos_apm_bulk_write(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
extern int exynos_apm_read(unsigned int type, unsigned int reg, unsigned int *val);
extern int exynos_apm_bulk_read(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
#define exynos7890_cl_dvfs_start(a) exynos7420_cl_dvfs_start(a)
#define exynos7890_cl_dvfs_stop(a, b) exynos7420_cl_dvfs_stop(a, b)
#define exynos7890_cl_dvfs_mode_enable() exynos7420_cl_dvfs_mode_enable()
#define exynos7890_cl_dvfs_mode_disable() exynos7420_cl_dvfs_mode_disable()
#define exynos7890_g3d_power_on_noti_apm() exynos7420_g3d_power_on_noti_apm()
#define exynos7890_g3d_power_down_noti_apm() exynos7420_g3d_power_down_noti_apm()
#define exynos7890_apm_enter_wfi() exynos7420_apm_enter_wfi()
#define exynos7890_apm_update_bits(a, b, c, d) exynos7420_apm_update_bits(a, b, c, d)
#define exynos7890_apm_write(a, b, c) exynos7420_apm_write(a, b, c)
#define exynos7890_apm_bulk_write(a, b, c, d) exynos7420_apm_bulk_write(a, b, c, d)
#define exynos7890_apm_read(a, b, c) exynos7420_apm_read(a, b, c)
#define exynos7890_apm_bulk_read(a, b, c, d) exynos7420_apm_bulk_read(a, b, c, d)
unsigned int exynos_cortexm3_pmu_read(unsigned int offset);
void exynos_cortexm3_pmu_write(unsigned int val, unsigned int offset);
unsigned int exynos_mailbox_reg_read(unsigned int offset);
void exynos_mailbox_reg_write(unsigned int val, unsigned int offset);
#endif

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/*
* Include file for the interface to an APM BIOS
* Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#ifndef _LINUX_APM_H
#define _LINUX_APM_H
#include <uapi/linux/apm_bios.h>
#define APM_CS (GDT_ENTRY_APMBIOS_BASE * 8)
#define APM_CS_16 (APM_CS + 8)
#define APM_DS (APM_CS_16 + 8)
/* Results of APM Installation Check */
#define APM_16_BIT_SUPPORT 0x0001
#define APM_32_BIT_SUPPORT 0x0002
#define APM_IDLE_SLOWS_CLOCK 0x0004
#define APM_BIOS_DISABLED 0x0008
#define APM_BIOS_DISENGAGED 0x0010
/*
* Data for APM that is persistent across module unload/load
*/
struct apm_info {
struct apm_bios_info bios;
unsigned short connection_version;
int get_power_status_broken;
int get_power_status_swabinminutes;
int allow_ints;
int forbid_idle;
int realmode_power_off;
int disabled;
};
/*
* The APM function codes
*/
#define APM_FUNC_INST_CHECK 0x5300
#define APM_FUNC_REAL_CONN 0x5301
#define APM_FUNC_16BIT_CONN 0x5302
#define APM_FUNC_32BIT_CONN 0x5303
#define APM_FUNC_DISCONN 0x5304
#define APM_FUNC_IDLE 0x5305
#define APM_FUNC_BUSY 0x5306
#define APM_FUNC_SET_STATE 0x5307
#define APM_FUNC_ENABLE_PM 0x5308
#define APM_FUNC_RESTORE_BIOS 0x5309
#define APM_FUNC_GET_STATUS 0x530a
#define APM_FUNC_GET_EVENT 0x530b
#define APM_FUNC_GET_STATE 0x530c
#define APM_FUNC_ENABLE_DEV_PM 0x530d
#define APM_FUNC_VERSION 0x530e
#define APM_FUNC_ENGAGE_PM 0x530f
#define APM_FUNC_GET_CAP 0x5310
#define APM_FUNC_RESUME_TIMER 0x5311
#define APM_FUNC_RESUME_ON_RING 0x5312
#define APM_FUNC_TIMER 0x5313
/*
* Function code for APM_FUNC_RESUME_TIMER
*/
#define APM_FUNC_DISABLE_TIMER 0
#define APM_FUNC_GET_TIMER 1
#define APM_FUNC_SET_TIMER 2
/*
* Function code for APM_FUNC_RESUME_ON_RING
*/
#define APM_FUNC_DISABLE_RING 0
#define APM_FUNC_ENABLE_RING 1
#define APM_FUNC_GET_RING 2
/*
* Function code for APM_FUNC_TIMER_STATUS
*/
#define APM_FUNC_TIMER_DISABLE 0
#define APM_FUNC_TIMER_ENABLE 1
#define APM_FUNC_TIMER_GET 2
/*
* in arch/i386/kernel/setup.c
*/
extern struct apm_info apm_info;
/*
* This is the "All Devices" ID communicated to the BIOS
*/
#define APM_DEVICE_BALL ((apm_info.connection_version > 0x0100) ? \
APM_DEVICE_ALL : APM_DEVICE_OLD_ALL)
#endif /* LINUX_APM_H */

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/*
* apple_bl exported symbols
*/
#ifndef _LINUX_APPLE_BL_H
#define _LINUX_APPLE_BL_H
#if defined(CONFIG_BACKLIGHT_APPLE) || defined(CONFIG_BACKLIGHT_APPLE_MODULE)
extern int apple_bl_register(void);
extern void apple_bl_unregister(void);
#else /* !CONFIG_BACKLIGHT_APPLE */
static inline int apple_bl_register(void)
{
return 0;
}
static inline void apple_bl_unregister(void)
{
}
#endif /* !CONFIG_BACKLIGHT_APPLE */
#endif /* _LINUX_APPLE_BL_H */

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/*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. NET is implemented using the BSD Socket
* interface as the means of communication with the user level.
*
* Definitions used by the ARCnet driver.
*
* Authors: Avery Pennarun and David Woodhouse
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#ifndef _LINUX_ARCDEVICE_H
#define _LINUX_ARCDEVICE_H
#include <asm/timex.h>
#include <linux/if_arcnet.h>
#ifdef __KERNEL__
#include <linux/irqreturn.h>
/*
* RECON_THRESHOLD is the maximum number of RECON messages to receive
* within one minute before printing a "cabling problem" warning. The
* default value should be fine.
*
* After that, a "cabling restored" message will be printed on the next IRQ
* if no RECON messages have been received for 10 seconds.
*
* Do not define RECON_THRESHOLD at all if you want to disable this feature.
*/
#define RECON_THRESHOLD 30
/*
* Define this to the minimum "timeout" value. If a transmit takes longer
* than TX_TIMEOUT jiffies, Linux will abort the TX and retry. On a large
* network, or one with heavy network traffic, this timeout may need to be
* increased. The larger it is, though, the longer it will be between
* necessary transmits - don't set this too high.
*/
#define TX_TIMEOUT (HZ * 200 / 1000)
/* Display warnings about the driver being an ALPHA version. */
#undef ALPHA_WARNING
/*
* Debugging bitflags: each option can be enabled individually.
*
* Note: only debug flags included in the ARCNET_DEBUG_MAX define will
* actually be available. GCC will (at least, GCC 2.7.0 will) notice
* lines using a BUGLVL not in ARCNET_DEBUG_MAX and automatically optimize
* them out.
*/
#define D_NORMAL 1 /* important operational info */
#define D_EXTRA 2 /* useful, but non-vital information */
#define D_INIT 4 /* show init/probe messages */
#define D_INIT_REASONS 8 /* show reasons for discarding probes */
#define D_RECON 32 /* print a message whenever token is lost */
#define D_PROTO 64 /* debug auto-protocol support */
/* debug levels below give LOTS of output during normal operation! */
#define D_DURING 128 /* trace operations (including irq's) */
#define D_TX 256 /* show tx packets */
#define D_RX 512 /* show rx packets */
#define D_SKB 1024 /* show skb's */
#define D_SKB_SIZE 2048 /* show skb sizes */
#define D_TIMING 4096 /* show time needed to copy buffers to card */
#define D_DEBUG 8192 /* Very detailed debug line for line */
#ifndef ARCNET_DEBUG_MAX
#define ARCNET_DEBUG_MAX (127) /* change to ~0 if you want detailed debugging */
#endif
#ifndef ARCNET_DEBUG
#define ARCNET_DEBUG (D_NORMAL|D_EXTRA)
#endif
extern int arcnet_debug;
/* macros to simplify debug checking */
#define BUGLVL(x) if ((ARCNET_DEBUG_MAX)&arcnet_debug&(x))
#define BUGMSG2(x,msg,args...) do { BUGLVL(x) printk(msg, ## args); } while (0)
#define BUGMSG(x,msg,args...) \
BUGMSG2(x, "%s%6s: " msg, \
x==D_NORMAL ? KERN_WARNING \
: x < D_DURING ? KERN_INFO : KERN_DEBUG, \
dev->name , ## args)
/* see how long a function call takes to run, expressed in CPU cycles */
#define TIME(name, bytes, call) BUGLVL(D_TIMING) { \
unsigned long _x, _y; \
_x = get_cycles(); \
call; \
_y = get_cycles(); \
BUGMSG(D_TIMING, \
"%s: %d bytes in %lu cycles == " \
"%lu Kbytes/100Mcycle\n",\
name, bytes, _y - _x, \
100000000 / 1024 * bytes / (_y - _x + 1));\
} \
else { \
call;\
}
/*
* Time needed to reset the card - in ms (milliseconds). This works on my
* SMC PC100. I can't find a reference that tells me just how long I
* should wait.
*/
#define RESETtime (300)
/*
* These are the max/min lengths of packet payload, not including the
* arc_hardware header, but definitely including the soft header.
*
* Note: packet sizes 254, 255, 256 are impossible because of the way
* ARCnet registers work That's why RFC1201 defines "exception" packets.
* In non-RFC1201 protocols, we have to just tack some extra bytes on the
* end.
*/
#define MTU 253 /* normal packet max size */
#define MinTU 257 /* extended packet min size */
#define XMTU 508 /* extended packet max size */
/* status/interrupt mask bit fields */
#define TXFREEflag 0x01 /* transmitter available */
#define TXACKflag 0x02 /* transmitted msg. ackd */
#define RECONflag 0x04 /* network reconfigured */
#define TESTflag 0x08 /* test flag */
#define EXCNAKflag 0x08 /* excesive nak flag */
#define RESETflag 0x10 /* power-on-reset */
#define RES1flag 0x20 /* reserved - usually set by jumper */
#define RES2flag 0x40 /* reserved - usually set by jumper */
#define NORXflag 0x80 /* receiver inhibited */
/* Flags used for IO-mapped memory operations */
#define AUTOINCflag 0x40 /* Increase location with each access */
#define IOMAPflag 0x02 /* (for 90xx) Use IO mapped memory, not mmap */
#define ENABLE16flag 0x80 /* (for 90xx) Enable 16-bit mode */
/* in the command register, the following bits have these meanings:
* 0-2 command
* 3-4 page number (for enable rcv/xmt command)
* 7 receive broadcasts
*/
#define NOTXcmd 0x01 /* disable transmitter */
#define NORXcmd 0x02 /* disable receiver */
#define TXcmd 0x03 /* enable transmitter */
#define RXcmd 0x04 /* enable receiver */
#define CONFIGcmd 0x05 /* define configuration */
#define CFLAGScmd 0x06 /* clear flags */
#define TESTcmd 0x07 /* load test flags */
/* flags for "clear flags" command */
#define RESETclear 0x08 /* power-on-reset */
#define CONFIGclear 0x10 /* system reconfigured */
#define EXCNAKclear 0x0E /* Clear and acknowledge the excive nak bit */
/* flags for "load test flags" command */
#define TESTload 0x08 /* test flag (diagnostic) */
/* byte deposited into first address of buffers on reset */
#define TESTvalue 0321 /* that's octal for 0xD1 :) */
/* for "enable receiver" command */
#define RXbcasts 0x80 /* receive broadcasts */
/* flags for "define configuration" command */
#define NORMALconf 0x00 /* 1-249 byte packets */
#define EXTconf 0x08 /* 250-504 byte packets */
/* card feature flags, set during auto-detection.
* (currently only used by com20020pci)
*/
#define ARC_IS_5MBIT 1 /* card default speed is 5MBit */
#define ARC_CAN_10MBIT 2 /* card uses COM20022, supporting 10MBit,
but default is 2.5MBit. */
/* information needed to define an encapsulation driver */
struct ArcProto {
char suffix; /* a for RFC1201, e for ether-encap, etc. */
int mtu; /* largest possible packet */
int is_ip; /* This is a ip plugin - not a raw thing */
void (*rx) (struct net_device * dev, int bufnum,
struct archdr * pkthdr, int length);
int (*build_header) (struct sk_buff * skb, struct net_device *dev,
unsigned short ethproto, uint8_t daddr);
/* these functions return '1' if the skb can now be freed */
int (*prepare_tx) (struct net_device * dev, struct archdr * pkt, int length,
int bufnum);
int (*continue_tx) (struct net_device * dev, int bufnum);
int (*ack_tx) (struct net_device * dev, int acked);
};
extern struct ArcProto *arc_proto_map[256], *arc_proto_default,
*arc_bcast_proto, *arc_raw_proto;
/*
* "Incoming" is information needed for each address that could be sending
* to us. Mostly for partially-received split packets.
*/
struct Incoming {
struct sk_buff *skb; /* packet data buffer */
__be16 sequence; /* sequence number of assembly */
uint8_t lastpacket, /* number of last packet (from 1) */
numpackets; /* number of packets in split */
};
/* only needed for RFC1201 */
struct Outgoing {
struct ArcProto *proto; /* protocol driver that owns this:
* if NULL, no packet is pending.
*/
struct sk_buff *skb; /* buffer from upper levels */
struct archdr *pkt; /* a pointer into the skb */
uint16_t length, /* bytes total */
dataleft, /* bytes left */
segnum, /* segment being sent */
numsegs; /* number of segments */
};
struct arcnet_local {
uint8_t config, /* current value of CONFIG register */
timeout, /* Extended timeout for COM20020 */
backplane, /* Backplane flag for COM20020 */
clockp, /* COM20020 clock divider */
clockm, /* COM20020 clock multiplier flag */
setup, /* Contents of setup1 register */
setup2, /* Contents of setup2 register */
intmask; /* current value of INTMASK register */
uint8_t default_proto[256]; /* default encap to use for each host */
int cur_tx, /* buffer used by current transmit, or -1 */
next_tx, /* buffer where a packet is ready to send */
cur_rx; /* current receive buffer */
int lastload_dest, /* can last loaded packet be acked? */
lasttrans_dest; /* can last TX'd packet be acked? */
int timed_out; /* need to process TX timeout and drop packet */
unsigned long last_timeout; /* time of last reported timeout */
char *card_name; /* card ident string */
int card_flags; /* special card features */
/* On preemtive and SMB a lock is needed */
spinlock_t lock;
/*
* Buffer management: an ARCnet card has 4 x 512-byte buffers, each of
* which can be used for either sending or receiving. The new dynamic
* buffer management routines use a simple circular queue of available
* buffers, and take them as they're needed. This way, we simplify
* situations in which we (for example) want to pre-load a transmit
* buffer, or start receiving while we copy a received packet to
* memory.
*
* The rules: only the interrupt handler is allowed to _add_ buffers to
* the queue; thus, this doesn't require a lock. Both the interrupt
* handler and the transmit function will want to _remove_ buffers, so
* we need to handle the situation where they try to do it at the same
* time.
*
* If next_buf == first_free_buf, the queue is empty. Since there are
* only four possible buffers, the queue should never be full.
*/
atomic_t buf_lock;
int buf_queue[5];
int next_buf, first_free_buf;
/* network "reconfiguration" handling */
unsigned long first_recon; /* time of "first" RECON message to count */
unsigned long last_recon; /* time of most recent RECON */
int num_recons; /* number of RECONs between first and last. */
int network_down; /* do we think the network is down? */
int excnak_pending; /* We just got an excesive nak interrupt */
struct {
uint16_t sequence; /* sequence number (incs with each packet) */
__be16 aborted_seq;
struct Incoming incoming[256]; /* one from each address */
} rfc1201;
/* really only used by rfc1201, but we'll pretend it's not */
struct Outgoing outgoing; /* packet currently being sent */
/* hardware-specific functions */
struct {
struct module *owner;
void (*command) (struct net_device * dev, int cmd);
int (*status) (struct net_device * dev);
void (*intmask) (struct net_device * dev, int mask);
int (*reset) (struct net_device * dev, int really_reset);
void (*open) (struct net_device * dev);
void (*close) (struct net_device * dev);
void (*copy_to_card) (struct net_device * dev, int bufnum, int offset,
void *buf, int count);
void (*copy_from_card) (struct net_device * dev, int bufnum, int offset,
void *buf, int count);
} hw;
void __iomem *mem_start; /* pointer to ioremap'ed MMIO */
};
#define ARCRESET(x) (lp->hw.reset(dev, (x)))
#define ACOMMAND(x) (lp->hw.command(dev, (x)))
#define ASTATUS() (lp->hw.status(dev))
#define AINTMASK(x) (lp->hw.intmask(dev, (x)))
#if ARCNET_DEBUG_MAX & D_SKB
void arcnet_dump_skb(struct net_device *dev, struct sk_buff *skb, char *desc);
#else
#define arcnet_dump_skb(dev,skb,desc) ;
#endif
void arcnet_unregister_proto(struct ArcProto *proto);
irqreturn_t arcnet_interrupt(int irq, void *dev_id);
struct net_device *alloc_arcdev(const char *name);
int arcnet_open(struct net_device *dev);
int arcnet_close(struct net_device *dev);
netdev_tx_t arcnet_send_packet(struct sk_buff *skb,
struct net_device *dev);
void arcnet_timeout(struct net_device *dev);
#endif /* __KERNEL__ */
#endif /* _LINUX_ARCDEVICE_H */

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/*
* CCI cache coherent interconnect support
*
* Copyright (C) 2013 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_ARM_CCI_H
#define __LINUX_ARM_CCI_H
#include <linux/errno.h>
#include <linux/types.h>
struct device_node;
#ifdef CONFIG_ARM_CCI
extern bool cci_probed(void);
extern int cci_ace_get_port(struct device_node *dn);
extern int cci_disable_port_by_cpu(u64 mpidr);
extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
extern int __cci_control_port_by_index(u32 port, bool enable);
#else
static inline bool cci_probed(void) { return false; }
static inline int cci_ace_get_port(struct device_node *dn)
{
return -ENODEV;
}
static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
static inline int __cci_control_port_by_device(struct device_node *dn,
bool enable)
{
return -ENODEV;
}
static inline int __cci_control_port_by_index(u32 port, bool enable)
{
return -ENODEV;
}
#endif
#define cci_disable_port_by_device(dev) \
__cci_control_port_by_device(dev, false)
#define cci_enable_port_by_device(dev) \
__cci_control_port_by_device(dev, true)
#define cci_disable_port_by_index(dev) \
__cci_control_port_by_index(dev, false)
#define cci_enable_port_by_index(dev) \
__cci_control_port_by_index(dev, true)
#endif

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/* ASN.1 BER/DER/CER encoding definitions
*
* Copyright (C) 2012 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _LINUX_ASN1_H
#define _LINUX_ASN1_H
/* Class */
enum asn1_class {
ASN1_UNIV = 0, /* Universal */
ASN1_APPL = 1, /* Application */
ASN1_CONT = 2, /* Context */
ASN1_PRIV = 3 /* Private */
};
#define ASN1_CLASS_BITS 0xc0
enum asn1_method {
ASN1_PRIM = 0, /* Primitive */
ASN1_CONS = 1 /* Constructed */
};
#define ASN1_CONS_BIT 0x20
/* Tag */
enum asn1_tag {
ASN1_EOC = 0, /* End Of Contents or N/A */
ASN1_BOOL = 1, /* Boolean */
ASN1_INT = 2, /* Integer */
ASN1_BTS = 3, /* Bit String */
ASN1_OTS = 4, /* Octet String */
ASN1_NULL = 5, /* Null */
ASN1_OID = 6, /* Object Identifier */
ASN1_ODE = 7, /* Object Description */
ASN1_EXT = 8, /* External */
ASN1_REAL = 9, /* Real float */
ASN1_ENUM = 10, /* Enumerated */
ASN1_EPDV = 11, /* Embedded PDV */
ASN1_UTF8STR = 12, /* UTF8 String */
ASN1_RELOID = 13, /* Relative OID */
/* 14 - Reserved */
/* 15 - Reserved */
ASN1_SEQ = 16, /* Sequence and Sequence of */
ASN1_SET = 17, /* Set and Set of */
ASN1_NUMSTR = 18, /* Numerical String */
ASN1_PRNSTR = 19, /* Printable String */
ASN1_TEXSTR = 20, /* T61 String / Teletext String */
ASN1_VIDSTR = 21, /* Videotex String */
ASN1_IA5STR = 22, /* IA5 String */
ASN1_UNITIM = 23, /* Universal Time */
ASN1_GENTIM = 24, /* General Time */
ASN1_GRASTR = 25, /* Graphic String */
ASN1_VISSTR = 26, /* Visible String */
ASN1_GENSTR = 27, /* General String */
ASN1_UNISTR = 28, /* Universal String */
ASN1_CHRSTR = 29, /* Character String */
ASN1_BMPSTR = 30, /* BMP String */
ASN1_LONG_TAG = 31 /* Long form tag */
};
#define ASN1_INDEFINITE_LENGTH 0x80
#endif /* _LINUX_ASN1_H */

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/* ASN.1 BER/DER/CER parsing state machine internal definitions
*
* Copyright (C) 2012 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _LINUX_ASN1_BER_BYTECODE_H
#define _LINUX_ASN1_BER_BYTECODE_H
#ifdef __KERNEL__
#include <linux/types.h>
#endif
#include <linux/asn1.h>
typedef int (*asn1_action_t)(void *context,
size_t hdrlen, /* In case of ANY type */
unsigned char tag, /* In case of ANY type */
const void *value, size_t vlen);
struct asn1_decoder {
const unsigned char *machine;
size_t machlen;
const asn1_action_t *actions;
};
enum asn1_opcode {
/* The tag-matching ops come first and the odd-numbered slots
* are for OR_SKIP ops.
*/
#define ASN1_OP_MATCH__SKIP 0x01
#define ASN1_OP_MATCH__ACT 0x02
#define ASN1_OP_MATCH__JUMP 0x04
#define ASN1_OP_MATCH__ANY 0x08
#define ASN1_OP_MATCH__COND 0x10
ASN1_OP_MATCH = 0x00,
ASN1_OP_MATCH_OR_SKIP = 0x01,
ASN1_OP_MATCH_ACT = 0x02,
ASN1_OP_MATCH_ACT_OR_SKIP = 0x03,
ASN1_OP_MATCH_JUMP = 0x04,
ASN1_OP_MATCH_JUMP_OR_SKIP = 0x05,
ASN1_OP_MATCH_ANY = 0x08,
ASN1_OP_MATCH_ANY_ACT = 0x0a,
/* Everything before here matches unconditionally */
ASN1_OP_COND_MATCH_OR_SKIP = 0x11,
ASN1_OP_COND_MATCH_ACT_OR_SKIP = 0x13,
ASN1_OP_COND_MATCH_JUMP_OR_SKIP = 0x15,
ASN1_OP_COND_MATCH_ANY = 0x18,
ASN1_OP_COND_MATCH_ANY_ACT = 0x1a,
/* Everything before here will want a tag from the data */
#define ASN1_OP__MATCHES_TAG ASN1_OP_COND_MATCH_ANY_ACT
/* These are here to help fill up space */
ASN1_OP_COND_FAIL = 0x1b,
ASN1_OP_COMPLETE = 0x1c,
ASN1_OP_ACT = 0x1d,
ASN1_OP_RETURN = 0x1e,
/* The following eight have bit 0 -> SET, 1 -> OF, 2 -> ACT */
ASN1_OP_END_SEQ = 0x20,
ASN1_OP_END_SET = 0x21,
ASN1_OP_END_SEQ_OF = 0x22,
ASN1_OP_END_SET_OF = 0x23,
ASN1_OP_END_SEQ_ACT = 0x24,
ASN1_OP_END_SET_ACT = 0x25,
ASN1_OP_END_SEQ_OF_ACT = 0x26,
ASN1_OP_END_SET_OF_ACT = 0x27,
#define ASN1_OP_END__SET 0x01
#define ASN1_OP_END__OF 0x02
#define ASN1_OP_END__ACT 0x04
ASN1_OP__NR
};
#define _tag(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | ASN1_##TAG)
#define _tagn(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | TAG)
#define _jump_target(N) (N)
#define _action(N) (N)
#endif /* _LINUX_ASN1_BER_BYTECODE_H */

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/* ASN.1 decoder
*
* Copyright (C) 2012 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _LINUX_ASN1_DECODER_H
#define _LINUX_ASN1_DECODER_H
#include <linux/asn1.h>
struct asn1_decoder;
extern int asn1_ber_decoder(const struct asn1_decoder *decoder,
void *context,
const unsigned char *data,
size_t datalen);
#endif /* _LINUX_ASN1_DECODER_H */

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/* Generic associative array implementation.
*
* See Documentation/assoc_array.txt for information.
*
* Copyright (C) 2013 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _LINUX_ASSOC_ARRAY_H
#define _LINUX_ASSOC_ARRAY_H
#ifdef CONFIG_ASSOCIATIVE_ARRAY
#include <linux/types.h>
#define ASSOC_ARRAY_KEY_CHUNK_SIZE BITS_PER_LONG /* Key data retrieved in chunks of this size */
/*
* Generic associative array.
*/
struct assoc_array {
struct assoc_array_ptr *root; /* The node at the root of the tree */
unsigned long nr_leaves_on_tree;
};
/*
* Operations on objects and index keys for use by array manipulation routines.
*/
struct assoc_array_ops {
/* Method to get a chunk of an index key from caller-supplied data */
unsigned long (*get_key_chunk)(const void *index_key, int level);
/* Method to get a piece of an object's index key */
unsigned long (*get_object_key_chunk)(const void *object, int level);
/* Is this the object we're looking for? */
bool (*compare_object)(const void *object, const void *index_key);
/* How different is an object from an index key, to a bit position in
* their keys? (or -1 if they're the same)
*/
int (*diff_objects)(const void *object, const void *index_key);
/* Method to free an object. */
void (*free_object)(void *object);
};
/*
* Access and manipulation functions.
*/
struct assoc_array_edit;
static inline void assoc_array_init(struct assoc_array *array)
{
array->root = NULL;
array->nr_leaves_on_tree = 0;
}
extern int assoc_array_iterate(const struct assoc_array *array,
int (*iterator)(const void *object,
void *iterator_data),
void *iterator_data);
extern void *assoc_array_find(const struct assoc_array *array,
const struct assoc_array_ops *ops,
const void *index_key);
extern void assoc_array_destroy(struct assoc_array *array,
const struct assoc_array_ops *ops);
extern struct assoc_array_edit *assoc_array_insert(struct assoc_array *array,
const struct assoc_array_ops *ops,
const void *index_key,
void *object);
extern void assoc_array_insert_set_object(struct assoc_array_edit *edit,
void *object);
extern struct assoc_array_edit *assoc_array_delete(struct assoc_array *array,
const struct assoc_array_ops *ops,
const void *index_key);
extern struct assoc_array_edit *assoc_array_clear(struct assoc_array *array,
const struct assoc_array_ops *ops);
extern void assoc_array_apply_edit(struct assoc_array_edit *edit);
extern void assoc_array_cancel_edit(struct assoc_array_edit *edit);
extern int assoc_array_gc(struct assoc_array *array,
const struct assoc_array_ops *ops,
bool (*iterator)(void *object, void *iterator_data),
void *iterator_data);
#endif /* CONFIG_ASSOCIATIVE_ARRAY */
#endif /* _LINUX_ASSOC_ARRAY_H */

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/* Private definitions for the generic associative array implementation.
*
* See Documentation/assoc_array.txt for information.
*
* Copyright (C) 2013 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _LINUX_ASSOC_ARRAY_PRIV_H
#define _LINUX_ASSOC_ARRAY_PRIV_H
#ifdef CONFIG_ASSOCIATIVE_ARRAY
#include <linux/assoc_array.h>
#define ASSOC_ARRAY_FAN_OUT 16 /* Number of slots per node */
#define ASSOC_ARRAY_FAN_MASK (ASSOC_ARRAY_FAN_OUT - 1)
#define ASSOC_ARRAY_LEVEL_STEP (ilog2(ASSOC_ARRAY_FAN_OUT))
#define ASSOC_ARRAY_LEVEL_STEP_MASK (ASSOC_ARRAY_LEVEL_STEP - 1)
#define ASSOC_ARRAY_KEY_CHUNK_MASK (ASSOC_ARRAY_KEY_CHUNK_SIZE - 1)
#define ASSOC_ARRAY_KEY_CHUNK_SHIFT (ilog2(BITS_PER_LONG))
/*
* Undefined type representing a pointer with type information in the bottom
* two bits.
*/
struct assoc_array_ptr;
/*
* An N-way node in the tree.
*
* Each slot contains one of four things:
*
* (1) Nothing (NULL).
*
* (2) A leaf object (pointer types 0).
*
* (3) A next-level node (pointer type 1, subtype 0).
*
* (4) A shortcut (pointer type 1, subtype 1).
*
* The tree is optimised for search-by-ID, but permits reasonable iteration
* also.
*
* The tree is navigated by constructing an index key consisting of an array of
* segments, where each segment is ilog2(ASSOC_ARRAY_FAN_OUT) bits in size.
*
* The segments correspond to levels of the tree (the first segment is used at
* level 0, the second at level 1, etc.).
*/
struct assoc_array_node {
struct assoc_array_ptr *back_pointer;
u8 parent_slot;
struct assoc_array_ptr *slots[ASSOC_ARRAY_FAN_OUT];
unsigned long nr_leaves_on_branch;
};
/*
* A shortcut through the index space out to where a collection of nodes/leaves
* with the same IDs live.
*/
struct assoc_array_shortcut {
struct assoc_array_ptr *back_pointer;
int parent_slot;
int skip_to_level;
struct assoc_array_ptr *next_node;
unsigned long index_key[];
};
/*
* Preallocation cache.
*/
struct assoc_array_edit {
struct rcu_head rcu;
struct assoc_array *array;
const struct assoc_array_ops *ops;
const struct assoc_array_ops *ops_for_excised_subtree;
struct assoc_array_ptr *leaf;
struct assoc_array_ptr **leaf_p;
struct assoc_array_ptr *dead_leaf;
struct assoc_array_ptr *new_meta[3];
struct assoc_array_ptr *excised_meta[1];
struct assoc_array_ptr *excised_subtree;
struct assoc_array_ptr **set_backpointers[ASSOC_ARRAY_FAN_OUT];
struct assoc_array_ptr *set_backpointers_to;
struct assoc_array_node *adjust_count_on;
long adjust_count_by;
struct {
struct assoc_array_ptr **ptr;
struct assoc_array_ptr *to;
} set[2];
struct {
u8 *p;
u8 to;
} set_parent_slot[1];
u8 segment_cache[ASSOC_ARRAY_FAN_OUT + 1];
};
/*
* Internal tree member pointers are marked in the bottom one or two bits to
* indicate what type they are so that we don't have to look behind every
* pointer to see what it points to.
*
* We provide functions to test type annotations and to create and translate
* the annotated pointers.
*/
#define ASSOC_ARRAY_PTR_TYPE_MASK 0x1UL
#define ASSOC_ARRAY_PTR_LEAF_TYPE 0x0UL /* Points to leaf (or nowhere) */
#define ASSOC_ARRAY_PTR_META_TYPE 0x1UL /* Points to node or shortcut */
#define ASSOC_ARRAY_PTR_SUBTYPE_MASK 0x2UL
#define ASSOC_ARRAY_PTR_NODE_SUBTYPE 0x0UL
#define ASSOC_ARRAY_PTR_SHORTCUT_SUBTYPE 0x2UL
static inline bool assoc_array_ptr_is_meta(const struct assoc_array_ptr *x)
{
return (unsigned long)x & ASSOC_ARRAY_PTR_TYPE_MASK;
}
static inline bool assoc_array_ptr_is_leaf(const struct assoc_array_ptr *x)
{
return !assoc_array_ptr_is_meta(x);
}
static inline bool assoc_array_ptr_is_shortcut(const struct assoc_array_ptr *x)
{
return (unsigned long)x & ASSOC_ARRAY_PTR_SUBTYPE_MASK;
}
static inline bool assoc_array_ptr_is_node(const struct assoc_array_ptr *x)
{
return !assoc_array_ptr_is_shortcut(x);
}
static inline void *assoc_array_ptr_to_leaf(const struct assoc_array_ptr *x)
{
return (void *)((unsigned long)x & ~ASSOC_ARRAY_PTR_TYPE_MASK);
}
static inline
unsigned long __assoc_array_ptr_to_meta(const struct assoc_array_ptr *x)
{
return (unsigned long)x &
~(ASSOC_ARRAY_PTR_SUBTYPE_MASK | ASSOC_ARRAY_PTR_TYPE_MASK);
}
static inline
struct assoc_array_node *assoc_array_ptr_to_node(const struct assoc_array_ptr *x)
{
return (struct assoc_array_node *)__assoc_array_ptr_to_meta(x);
}
static inline
struct assoc_array_shortcut *assoc_array_ptr_to_shortcut(const struct assoc_array_ptr *x)
{
return (struct assoc_array_shortcut *)__assoc_array_ptr_to_meta(x);
}
static inline
struct assoc_array_ptr *__assoc_array_x_to_ptr(const void *p, unsigned long t)
{
return (struct assoc_array_ptr *)((unsigned long)p | t);
}
static inline
struct assoc_array_ptr *assoc_array_leaf_to_ptr(const void *p)
{
return __assoc_array_x_to_ptr(p, ASSOC_ARRAY_PTR_LEAF_TYPE);
}
static inline
struct assoc_array_ptr *assoc_array_node_to_ptr(const struct assoc_array_node *p)
{
return __assoc_array_x_to_ptr(
p, ASSOC_ARRAY_PTR_META_TYPE | ASSOC_ARRAY_PTR_NODE_SUBTYPE);
}
static inline
struct assoc_array_ptr *assoc_array_shortcut_to_ptr(const struct assoc_array_shortcut *p)
{
return __assoc_array_x_to_ptr(
p, ASSOC_ARRAY_PTR_META_TYPE | ASSOC_ARRAY_PTR_SHORTCUT_SUBTYPE);
}
#endif /* CONFIG_ASSOCIATIVE_ARRAY */
#endif /* _LINUX_ASSOC_ARRAY_PRIV_H */

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/*
* async.h: Asynchronous function calls for boot performance
*
* (C) Copyright 2009 Intel Corporation
* Author: Arjan van de Ven <arjan@linux.intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef __ASYNC_H__
#define __ASYNC_H__
#include <linux/types.h>
#include <linux/list.h>
typedef u64 async_cookie_t;
typedef void (*async_func_t) (void *data, async_cookie_t cookie);
struct async_domain {
struct list_head pending;
unsigned registered:1;
};
/*
* domain participates in global async_synchronize_full
*/
#define ASYNC_DOMAIN(_name) \
struct async_domain _name = { .pending = LIST_HEAD_INIT(_name.pending), \
.registered = 1 }
/*
* domain is free to go out of scope as soon as all pending work is
* complete, this domain does not participate in async_synchronize_full
*/
#define ASYNC_DOMAIN_EXCLUSIVE(_name) \
struct async_domain _name = { .pending = LIST_HEAD_INIT(_name.pending), \
.registered = 0 }
extern async_cookie_t async_schedule(async_func_t func, void *data);
extern async_cookie_t async_schedule_domain(async_func_t func, void *data,
struct async_domain *domain);
void async_unregister_domain(struct async_domain *domain);
extern void async_synchronize_full(void);
extern void async_synchronize_full_domain(struct async_domain *domain);
extern void async_synchronize_cookie(async_cookie_t cookie);
extern void async_synchronize_cookie_domain(async_cookie_t cookie,
struct async_domain *domain);
extern bool current_is_async(void);
#endif

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/*
* Copyright © 2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef _ASYNC_TX_H_
#define _ASYNC_TX_H_
#include <linux/dmaengine.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
/* on architectures without dma-mapping capabilities we need to ensure
* that the asynchronous path compiles away
*/
#ifdef CONFIG_HAS_DMA
#define __async_inline
#else
#define __async_inline __always_inline
#endif
/**
* dma_chan_ref - object used to manage dma channels received from the
* dmaengine core.
* @chan - the channel being tracked
* @node - node for the channel to be placed on async_tx_master_list
* @rcu - for list_del_rcu
* @count - number of times this channel is listed in the pool
* (for channels with multiple capabiities)
*/
struct dma_chan_ref {
struct dma_chan *chan;
struct list_head node;
struct rcu_head rcu;
atomic_t count;
};
/**
* async_tx_flags - modifiers for the async_* calls
* @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the
* the destination address is not a source. The asynchronous case handles this
* implicitly, the synchronous case needs to zero the destination block.
* @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is
* also one of the source addresses. In the synchronous case the destination
* address is an implied source, whereas the asynchronous case it must be listed
* as a source. The destination address must be the first address in the source
* array.
* @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a
* dependency chain
* @ASYNC_TX_FENCE: specify that the next operation in the dependency
* chain uses this operation's result as an input
*/
enum async_tx_flags {
ASYNC_TX_XOR_ZERO_DST = (1 << 0),
ASYNC_TX_XOR_DROP_DST = (1 << 1),
ASYNC_TX_ACK = (1 << 2),
ASYNC_TX_FENCE = (1 << 3),
};
/**
* struct async_submit_ctl - async_tx submission/completion modifiers
* @flags: submission modifiers
* @depend_tx: parent dependency of the current operation being submitted
* @cb_fn: callback routine to run at operation completion
* @cb_param: parameter for the callback routine
* @scribble: caller provided space for dma/page address conversions
*/
struct async_submit_ctl {
enum async_tx_flags flags;
struct dma_async_tx_descriptor *depend_tx;
dma_async_tx_callback cb_fn;
void *cb_param;
void *scribble;
};
#ifdef CONFIG_DMA_ENGINE
#define async_tx_issue_pending_all dma_issue_pending_all
/**
* async_tx_issue_pending - send pending descriptor to the hardware channel
* @tx: descriptor handle to retrieve hardware context
*
* Note: any dependent operations will have already been issued by
* async_tx_channel_switch, or (in the case of no channel switch) will
* be already pending on this channel.
*/
static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx)
{
if (likely(tx)) {
struct dma_chan *chan = tx->chan;
struct dma_device *dma = chan->device;
dma->device_issue_pending(chan);
}
}
#ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL
#include <asm/async_tx.h>
#else
#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
__async_tx_find_channel(dep, type)
struct dma_chan *
__async_tx_find_channel(struct async_submit_ctl *submit,
enum dma_transaction_type tx_type);
#endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */
#else
static inline void async_tx_issue_pending_all(void)
{
do { } while (0);
}
static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx)
{
do { } while (0);
}
static inline struct dma_chan *
async_tx_find_channel(struct async_submit_ctl *submit,
enum dma_transaction_type tx_type, struct page **dst,
int dst_count, struct page **src, int src_count,
size_t len)
{
return NULL;
}
#endif
/**
* async_tx_sync_epilog - actions to take if an operation is run synchronously
* @cb_fn: function to call when the transaction completes
* @cb_fn_param: parameter to pass to the callback routine
*/
static inline void
async_tx_sync_epilog(struct async_submit_ctl *submit)
{
if (submit->cb_fn)
submit->cb_fn(submit->cb_param);
}
typedef union {
unsigned long addr;
struct page *page;
dma_addr_t dma;
} addr_conv_t;
static inline void
init_async_submit(struct async_submit_ctl *args, enum async_tx_flags flags,
struct dma_async_tx_descriptor *tx,
dma_async_tx_callback cb_fn, void *cb_param,
addr_conv_t *scribble)
{
args->flags = flags;
args->depend_tx = tx;
args->cb_fn = cb_fn;
args->cb_param = cb_param;
args->scribble = scribble;
}
void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_xor(struct page *dest, struct page **src_list, unsigned int offset,
int src_cnt, size_t len, struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_xor_val(struct page *dest, struct page **src_list, unsigned int offset,
int src_cnt, size_t len, enum sum_check_flags *result,
struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset,
unsigned int src_offset, size_t len,
struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *async_trigger_callback(struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_gen_syndrome(struct page **blocks, unsigned int offset, int src_cnt,
size_t len, struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_syndrome_val(struct page **blocks, unsigned int offset, int src_cnt,
size_t len, enum sum_check_flags *pqres, struct page *spare,
struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_raid6_2data_recov(int src_num, size_t bytes, int faila, int failb,
struct page **ptrs, struct async_submit_ctl *submit);
struct dma_async_tx_descriptor *
async_raid6_datap_recov(int src_num, size_t bytes, int faila,
struct page **ptrs, struct async_submit_ctl *submit);
void async_tx_quiesce(struct dma_async_tx_descriptor **tx);
#endif /* _ASYNC_TX_H_ */

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#ifndef __LINUX_ATA_PLATFORM_H
#define __LINUX_ATA_PLATFORM_H
struct pata_platform_info {
/*
* I/O port shift, for platforms with ports that are
* constantly spaced and need larger than the 1-byte
* spacing used by ata_std_ports().
*/
unsigned int ioport_shift;
};
extern int __pata_platform_probe(struct device *dev,
struct resource *io_res,
struct resource *ctl_res,
struct resource *irq_res,
unsigned int ioport_shift,
int __pio_mask);
/*
* Marvell SATA private data
*/
struct mv_sata_platform_data {
int n_ports; /* number of sata ports */
};
#endif /* __LINUX_ATA_PLATFORM_H */

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#ifndef __LINUX_ATALK_H__
#define __LINUX_ATALK_H__
#include <net/sock.h>
#include <uapi/linux/atalk.h>
struct atalk_route {
struct net_device *dev;
struct atalk_addr target;
struct atalk_addr gateway;
int flags;
struct atalk_route *next;
};
/**
* struct atalk_iface - AppleTalk Interface
* @dev - Network device associated with this interface
* @address - Our address
* @status - What are we doing?
* @nets - Associated direct netrange
* @next - next element in the list of interfaces
*/
struct atalk_iface {
struct net_device *dev;
struct atalk_addr address;
int status;
#define ATIF_PROBE 1 /* Probing for an address */
#define ATIF_PROBE_FAIL 2 /* Probe collided */
struct atalk_netrange nets;
struct atalk_iface *next;
};
struct atalk_sock {
/* struct sock has to be the first member of atalk_sock */
struct sock sk;
__be16 dest_net;
__be16 src_net;
unsigned char dest_node;
unsigned char src_node;
unsigned char dest_port;
unsigned char src_port;
};
static inline struct atalk_sock *at_sk(struct sock *sk)
{
return (struct atalk_sock *)sk;
}
struct ddpehdr {
__be16 deh_len_hops; /* lower 10 bits are length, next 4 - hops */
__be16 deh_sum;
__be16 deh_dnet;
__be16 deh_snet;
__u8 deh_dnode;
__u8 deh_snode;
__u8 deh_dport;
__u8 deh_sport;
/* And netatalk apps expect to stick the type in themselves */
};
static __inline__ struct ddpehdr *ddp_hdr(struct sk_buff *skb)
{
return (struct ddpehdr *)skb_transport_header(skb);
}
/* AppleTalk AARP headers */
struct elapaarp {
__be16 hw_type;
#define AARP_HW_TYPE_ETHERNET 1
#define AARP_HW_TYPE_TOKENRING 2
__be16 pa_type;
__u8 hw_len;
__u8 pa_len;
#define AARP_PA_ALEN 4
__be16 function;
#define AARP_REQUEST 1
#define AARP_REPLY 2
#define AARP_PROBE 3
__u8 hw_src[ETH_ALEN];
__u8 pa_src_zero;
__be16 pa_src_net;
__u8 pa_src_node;
__u8 hw_dst[ETH_ALEN];
__u8 pa_dst_zero;
__be16 pa_dst_net;
__u8 pa_dst_node;
} __attribute__ ((packed));
static __inline__ struct elapaarp *aarp_hdr(struct sk_buff *skb)
{
return (struct elapaarp *)skb_transport_header(skb);
}
/* Not specified - how long till we drop a resolved entry */
#define AARP_EXPIRY_TIME (5 * 60 * HZ)
/* Size of hash table */
#define AARP_HASH_SIZE 16
/* Fast retransmission timer when resolving */
#define AARP_TICK_TIME (HZ / 5)
/* Send 10 requests then give up (2 seconds) */
#define AARP_RETRANSMIT_LIMIT 10
/*
* Some value bigger than total retransmit time + a bit for last reply to
* appear and to stop continual requests
*/
#define AARP_RESOLVE_TIME (10 * HZ)
extern struct datalink_proto *ddp_dl, *aarp_dl;
extern void aarp_proto_init(void);
/* Inter module exports */
/* Give a device find its atif control structure */
static inline struct atalk_iface *atalk_find_dev(struct net_device *dev)
{
return dev->atalk_ptr;
}
extern struct atalk_addr *atalk_find_dev_addr(struct net_device *dev);
extern struct net_device *atrtr_get_dev(struct atalk_addr *sa);
extern int aarp_send_ddp(struct net_device *dev,
struct sk_buff *skb,
struct atalk_addr *sa, void *hwaddr);
extern void aarp_device_down(struct net_device *dev);
extern void aarp_probe_network(struct atalk_iface *atif);
extern int aarp_proxy_probe_network(struct atalk_iface *atif,
struct atalk_addr *sa);
extern void aarp_proxy_remove(struct net_device *dev,
struct atalk_addr *sa);
extern void aarp_cleanup_module(void);
extern struct hlist_head atalk_sockets;
extern rwlock_t atalk_sockets_lock;
extern struct atalk_route *atalk_routes;
extern rwlock_t atalk_routes_lock;
extern struct atalk_iface *atalk_interfaces;
extern rwlock_t atalk_interfaces_lock;
extern struct atalk_route atrtr_default;
extern const struct file_operations atalk_seq_arp_fops;
extern int sysctl_aarp_expiry_time;
extern int sysctl_aarp_tick_time;
extern int sysctl_aarp_retransmit_limit;
extern int sysctl_aarp_resolve_time;
#ifdef CONFIG_SYSCTL
extern void atalk_register_sysctl(void);
extern void atalk_unregister_sysctl(void);
#else
#define atalk_register_sysctl() do { } while(0)
#define atalk_unregister_sysctl() do { } while(0)
#endif
#ifdef CONFIG_PROC_FS
extern int atalk_proc_init(void);
extern void atalk_proc_exit(void);
#else
#define atalk_proc_init() ({ 0; })
#define atalk_proc_exit() do { } while(0)
#endif /* CONFIG_PROC_FS */
#endif /* __LINUX_ATALK_H__ */

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/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _LINUX_ATH9K_PLATFORM_H
#define _LINUX_ATH9K_PLATFORM_H
#define ATH9K_PLAT_EEP_MAX_WORDS 2048
struct ath9k_platform_data {
const char *eeprom_name;
u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS];
u8 *macaddr;
int led_pin;
u32 gpio_mask;
u32 gpio_val;
bool is_clk_25mhz;
bool tx_gain_buffalo;
int (*get_mac_revision)(void);
int (*external_reset)(void);
bool use_eeprom;
};
#endif /* _LINUX_ATH9K_PLATFORM_H */

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/* atm.h - general ATM declarations */
#ifndef _LINUX_ATM_H
#define _LINUX_ATM_H
#include <uapi/linux/atm.h>
#ifdef CONFIG_COMPAT
#include <linux/compat.h>
struct compat_atmif_sioc {
int number;
int length;
compat_uptr_t arg;
};
#endif
#endif

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/* atm_suni.h - Driver-specific declarations of the SUNI driver (for use by
driver-specific utilities) */
/* Written 1998,2000 by Werner Almesberger, EPFL ICA */
#ifndef LINUX_ATM_SUNI_H
#define LINUX_ATM_SUNI_H
/* everything obsoleted */
#endif

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/* atm_tcp.h - Driver-specific declarations of the ATMTCP driver (for use by
driver-specific utilities) */
/* Written 1997-2000 by Werner Almesberger, EPFL LRC/ICA */
#ifndef LINUX_ATM_TCP_H
#define LINUX_ATM_TCP_H
#include <uapi/linux/atm_tcp.h>
struct atm_tcp_ops {
int (*attach)(struct atm_vcc *vcc,int itf);
int (*create_persistent)(int itf);
int (*remove_persistent)(int itf);
struct module *owner;
};
extern struct atm_tcp_ops atm_tcp_ops;
#endif

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/* atmdev.h - ATM device driver declarations and various related items */
#ifndef LINUX_ATMDEV_H
#define LINUX_ATMDEV_H
#include <linux/wait.h> /* wait_queue_head_t */
#include <linux/time.h> /* struct timeval */
#include <linux/net.h>
#include <linux/bug.h>
#include <linux/skbuff.h> /* struct sk_buff */
#include <linux/uio.h>
#include <net/sock.h>
#include <linux/atomic.h>
#include <uapi/linux/atmdev.h>
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
extern struct proc_dir_entry *atm_proc_root;
#endif
#ifdef CONFIG_COMPAT
#include <linux/compat.h>
struct compat_atm_iobuf {
int length;
compat_uptr_t buffer;
};
#endif
struct k_atm_aal_stats {
#define __HANDLE_ITEM(i) atomic_t i
__AAL_STAT_ITEMS
#undef __HANDLE_ITEM
};
struct k_atm_dev_stats {
struct k_atm_aal_stats aal0;
struct k_atm_aal_stats aal34;
struct k_atm_aal_stats aal5;
};
struct device;
enum {
ATM_VF_ADDR, /* Address is in use. Set by anybody, cleared
by device driver. */
ATM_VF_READY, /* VC is ready to transfer data. Set by device
driver, cleared by anybody. */
ATM_VF_PARTIAL, /* resources are bound to PVC (partial PVC
setup), controlled by socket layer */
ATM_VF_REGIS, /* registered with demon, controlled by SVC
socket layer */
ATM_VF_BOUND, /* local SAP is set, controlled by SVC socket
layer */
ATM_VF_RELEASED, /* demon has indicated/requested release,
controlled by SVC socket layer */
ATM_VF_HASQOS, /* QOS parameters have been set */
ATM_VF_LISTEN, /* socket is used for listening */
ATM_VF_META, /* SVC socket isn't used for normal data
traffic and doesn't depend on signaling
to be available */
ATM_VF_SESSION, /* VCC is p2mp session control descriptor */
ATM_VF_HASSAP, /* SAP has been set */
ATM_VF_CLOSE, /* asynchronous close - treat like VF_RELEASED*/
ATM_VF_WAITING, /* waiting for reply from sigd */
ATM_VF_IS_CLIP, /* in use by CLIP protocol */
};
#define ATM_VF2VS(flags) \
(test_bit(ATM_VF_READY,&(flags)) ? ATM_VS_CONNECTED : \
test_bit(ATM_VF_RELEASED,&(flags)) ? ATM_VS_CLOSING : \
test_bit(ATM_VF_LISTEN,&(flags)) ? ATM_VS_LISTEN : \
test_bit(ATM_VF_REGIS,&(flags)) ? ATM_VS_INUSE : \
test_bit(ATM_VF_BOUND,&(flags)) ? ATM_VS_BOUND : ATM_VS_IDLE)
enum {
ATM_DF_REMOVED, /* device was removed from atm_devs list */
};
#define ATM_PHY_SIG_LOST 0 /* no carrier/light */
#define ATM_PHY_SIG_UNKNOWN 1 /* carrier/light status is unknown */
#define ATM_PHY_SIG_FOUND 2 /* carrier/light okay */
#define ATM_ATMOPT_CLP 1 /* set CLP bit */
struct atm_vcc {
/* struct sock has to be the first member of atm_vcc */
struct sock sk;
unsigned long flags; /* VCC flags (ATM_VF_*) */
short vpi; /* VPI and VCI (types must be equal */
/* with sockaddr) */
int vci;
unsigned long aal_options; /* AAL layer options */
unsigned long atm_options; /* ATM layer options */
struct atm_dev *dev; /* device back pointer */
struct atm_qos qos; /* QOS */
struct atm_sap sap; /* SAP */
void (*release_cb)(struct atm_vcc *vcc); /* release_sock callback */
void (*push)(struct atm_vcc *vcc,struct sk_buff *skb);
void (*pop)(struct atm_vcc *vcc,struct sk_buff *skb); /* optional */
int (*push_oam)(struct atm_vcc *vcc,void *cell);
int (*send)(struct atm_vcc *vcc,struct sk_buff *skb);
void *dev_data; /* per-device data */
void *proto_data; /* per-protocol data */
struct k_atm_aal_stats *stats; /* pointer to AAL stats group */
struct module *owner; /* owner of ->push function */
/* SVC part --- may move later ------------------------------------- */
short itf; /* interface number */
struct sockaddr_atmsvc local;
struct sockaddr_atmsvc remote;
/* Multipoint part ------------------------------------------------- */
struct atm_vcc *session; /* session VCC descriptor */
/* Other stuff ----------------------------------------------------- */
void *user_back; /* user backlink - not touched by */
/* native ATM stack. Currently used */
/* by CLIP and sch_atm. */
};
static inline struct atm_vcc *atm_sk(struct sock *sk)
{
return (struct atm_vcc *)sk;
}
static inline struct atm_vcc *ATM_SD(struct socket *sock)
{
return atm_sk(sock->sk);
}
static inline struct sock *sk_atm(struct atm_vcc *vcc)
{
return (struct sock *)vcc;
}
struct atm_dev_addr {
struct sockaddr_atmsvc addr; /* ATM address */
struct list_head entry; /* next address */
};
enum atm_addr_type_t { ATM_ADDR_LOCAL, ATM_ADDR_LECS };
struct atm_dev {
const struct atmdev_ops *ops; /* device operations; NULL if unused */
const struct atmphy_ops *phy; /* PHY operations, may be undefined */
/* (NULL) */
const char *type; /* device type name */
int number; /* device index */
void *dev_data; /* per-device data */
void *phy_data; /* private PHY date */
unsigned long flags; /* device flags (ATM_DF_*) */
struct list_head local; /* local ATM addresses */
struct list_head lecs; /* LECS ATM addresses learned via ILMI */
unsigned char esi[ESI_LEN]; /* ESI ("MAC" addr) */
struct atm_cirange ci_range; /* VPI/VCI range */
struct k_atm_dev_stats stats; /* statistics */
char signal; /* signal status (ATM_PHY_SIG_*) */
int link_rate; /* link rate (default: OC3) */
atomic_t refcnt; /* reference count */
spinlock_t lock; /* protect internal members */
#ifdef CONFIG_PROC_FS
struct proc_dir_entry *proc_entry; /* proc entry */
char *proc_name; /* proc entry name */
#endif
struct device class_dev; /* sysfs device */
struct list_head dev_list; /* linkage */
};
/* OF: send_Oam Flags */
#define ATM_OF_IMMED 1 /* Attempt immediate delivery */
#define ATM_OF_INRATE 2 /* Attempt in-rate delivery */
/*
* ioctl, getsockopt, and setsockopt are optional and can be set to NULL.
*/
struct atmdev_ops { /* only send is required */
void (*dev_close)(struct atm_dev *dev);
int (*open)(struct atm_vcc *vcc);
void (*close)(struct atm_vcc *vcc);
int (*ioctl)(struct atm_dev *dev,unsigned int cmd,void __user *arg);
#ifdef CONFIG_COMPAT
int (*compat_ioctl)(struct atm_dev *dev,unsigned int cmd,
void __user *arg);
#endif
int (*getsockopt)(struct atm_vcc *vcc,int level,int optname,
void __user *optval,int optlen);
int (*setsockopt)(struct atm_vcc *vcc,int level,int optname,
void __user *optval,unsigned int optlen);
int (*send)(struct atm_vcc *vcc,struct sk_buff *skb);
int (*send_oam)(struct atm_vcc *vcc,void *cell,int flags);
void (*phy_put)(struct atm_dev *dev,unsigned char value,
unsigned long addr);
unsigned char (*phy_get)(struct atm_dev *dev,unsigned long addr);
int (*change_qos)(struct atm_vcc *vcc,struct atm_qos *qos,int flags);
int (*proc_read)(struct atm_dev *dev,loff_t *pos,char *page);
struct module *owner;
};
struct atmphy_ops {
int (*start)(struct atm_dev *dev);
int (*ioctl)(struct atm_dev *dev,unsigned int cmd,void __user *arg);
void (*interrupt)(struct atm_dev *dev);
int (*stop)(struct atm_dev *dev);
};
struct atm_skb_data {
struct atm_vcc *vcc; /* ATM VCC */
unsigned long atm_options; /* ATM layer options */
};
#define VCC_HTABLE_SIZE 32
extern struct hlist_head vcc_hash[VCC_HTABLE_SIZE];
extern rwlock_t vcc_sklist_lock;
#define ATM_SKB(skb) (((struct atm_skb_data *) (skb)->cb))
struct atm_dev *atm_dev_register(const char *type, struct device *parent,
const struct atmdev_ops *ops,
int number, /* -1 == pick first available */
unsigned long *flags);
struct atm_dev *atm_dev_lookup(int number);
void atm_dev_deregister(struct atm_dev *dev);
/* atm_dev_signal_change
*
* Propagate lower layer signal change in atm_dev->signal to netdevice.
* The event will be sent via a notifier call chain.
*/
void atm_dev_signal_change(struct atm_dev *dev, char signal);
void vcc_insert_socket(struct sock *sk);
void atm_dev_release_vccs(struct atm_dev *dev);
static inline void atm_force_charge(struct atm_vcc *vcc,int truesize)
{
atomic_add(truesize, &sk_atm(vcc)->sk_rmem_alloc);
}
static inline void atm_return(struct atm_vcc *vcc,int truesize)
{
atomic_sub(truesize, &sk_atm(vcc)->sk_rmem_alloc);
}
static inline int atm_may_send(struct atm_vcc *vcc,unsigned int size)
{
return (size + atomic_read(&sk_atm(vcc)->sk_wmem_alloc)) <
sk_atm(vcc)->sk_sndbuf;
}
static inline void atm_dev_hold(struct atm_dev *dev)
{
atomic_inc(&dev->refcnt);
}
static inline void atm_dev_put(struct atm_dev *dev)
{
if (atomic_dec_and_test(&dev->refcnt)) {
BUG_ON(!test_bit(ATM_DF_REMOVED, &dev->flags));
if (dev->ops->dev_close)
dev->ops->dev_close(dev);
put_device(&dev->class_dev);
}
}
int atm_charge(struct atm_vcc *vcc,int truesize);
struct sk_buff *atm_alloc_charge(struct atm_vcc *vcc,int pdu_size,
gfp_t gfp_flags);
int atm_pcr_goal(const struct atm_trafprm *tp);
void vcc_release_async(struct atm_vcc *vcc, int reply);
struct atm_ioctl {
struct module *owner;
/* A module reference is kept if appropriate over this call.
* Return -ENOIOCTLCMD if you don't handle it. */
int (*ioctl)(struct socket *, unsigned int cmd, unsigned long arg);
struct list_head list;
};
/**
* register_atm_ioctl - register handler for ioctl operations
*
* Special (non-device) handlers of ioctl's should
* register here. If you're a normal device, you should
* set .ioctl in your atmdev_ops instead.
*/
void register_atm_ioctl(struct atm_ioctl *);
/**
* deregister_atm_ioctl - remove the ioctl handler
*/
void deregister_atm_ioctl(struct atm_ioctl *);
/* register_atmdevice_notifier - register atm_dev notify events
*
* Clients like br2684 will register notify events
* Currently we notify of signal found/lost
*/
int register_atmdevice_notifier(struct notifier_block *nb);
void unregister_atmdevice_notifier(struct notifier_block *nb);
#endif

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#ifndef __LINUX_ATMEL_MCI_H
#define __LINUX_ATMEL_MCI_H
#include <linux/types.h>
#define ATMCI_MAX_NR_SLOTS 2
/**
* struct mci_slot_pdata - board-specific per-slot configuration
* @bus_width: Number of data lines wired up the slot
* @detect_pin: GPIO pin wired to the card detect switch
* @wp_pin: GPIO pin wired to the write protect sensor
* @detect_is_active_high: The state of the detect pin when it is active
*
* If a given slot is not present on the board, @bus_width should be
* set to 0. The other fields are ignored in this case.
*
* Any pins that aren't available should be set to a negative value.
*
* Note that support for multiple slots is experimental -- some cards
* might get upset if we don't get the clock management exactly right.
* But in most cases, it should work just fine.
*/
struct mci_slot_pdata {
unsigned int bus_width;
int detect_pin;
int wp_pin;
bool detect_is_active_high;
};
/**
* struct mci_platform_data - board-specific MMC/SDcard configuration
* @dma_slave: DMA slave interface to use in data transfers.
* @slot: Per-slot configuration data.
*/
struct mci_platform_data {
struct mci_dma_data *dma_slave;
struct mci_slot_pdata slot[ATMCI_MAX_NR_SLOTS];
};
#endif /* __LINUX_ATMEL_MCI_H */

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#ifndef __INCLUDE_ATMEL_SSC_H
#define __INCLUDE_ATMEL_SSC_H
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/io.h>
struct atmel_ssc_platform_data {
int use_dma;
int has_fslen_ext;
};
struct ssc_device {
struct list_head list;
dma_addr_t phybase;
void __iomem *regs;
struct platform_device *pdev;
struct atmel_ssc_platform_data *pdata;
struct clk *clk;
int user;
int irq;
bool clk_from_rk_pin;
};
struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
void ssc_free(struct ssc_device *ssc);
/* SSC register offsets */
/* SSC Control Register */
#define SSC_CR 0x00000000
#define SSC_CR_RXDIS_SIZE 1
#define SSC_CR_RXDIS_OFFSET 1
#define SSC_CR_RXEN_SIZE 1
#define SSC_CR_RXEN_OFFSET 0
#define SSC_CR_SWRST_SIZE 1
#define SSC_CR_SWRST_OFFSET 15
#define SSC_CR_TXDIS_SIZE 1
#define SSC_CR_TXDIS_OFFSET 9
#define SSC_CR_TXEN_SIZE 1
#define SSC_CR_TXEN_OFFSET 8
/* SSC Clock Mode Register */
#define SSC_CMR 0x00000004
#define SSC_CMR_DIV_SIZE 12
#define SSC_CMR_DIV_OFFSET 0
/* SSC Receive Clock Mode Register */
#define SSC_RCMR 0x00000010
#define SSC_RCMR_CKG_SIZE 2
#define SSC_RCMR_CKG_OFFSET 6
#define SSC_RCMR_CKI_SIZE 1
#define SSC_RCMR_CKI_OFFSET 5
#define SSC_RCMR_CKO_SIZE 3
#define SSC_RCMR_CKO_OFFSET 2
#define SSC_RCMR_CKS_SIZE 2
#define SSC_RCMR_CKS_OFFSET 0
#define SSC_RCMR_PERIOD_SIZE 8
#define SSC_RCMR_PERIOD_OFFSET 24
#define SSC_RCMR_START_SIZE 4
#define SSC_RCMR_START_OFFSET 8
#define SSC_RCMR_STOP_SIZE 1
#define SSC_RCMR_STOP_OFFSET 12
#define SSC_RCMR_STTDLY_SIZE 8
#define SSC_RCMR_STTDLY_OFFSET 16
/* SSC Receive Frame Mode Register */
#define SSC_RFMR 0x00000014
#define SSC_RFMR_DATLEN_SIZE 5
#define SSC_RFMR_DATLEN_OFFSET 0
#define SSC_RFMR_DATNB_SIZE 4
#define SSC_RFMR_DATNB_OFFSET 8
#define SSC_RFMR_FSEDGE_SIZE 1
#define SSC_RFMR_FSEDGE_OFFSET 24
/*
* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
* at91sam9g20, and at91sam9g45 and newer SoCs
*/
#define SSC_RFMR_FSLEN_EXT_SIZE 4
#define SSC_RFMR_FSLEN_EXT_OFFSET 28
#define SSC_RFMR_FSLEN_SIZE 4
#define SSC_RFMR_FSLEN_OFFSET 16
#define SSC_RFMR_FSOS_SIZE 4
#define SSC_RFMR_FSOS_OFFSET 20
#define SSC_RFMR_LOOP_SIZE 1
#define SSC_RFMR_LOOP_OFFSET 5
#define SSC_RFMR_MSBF_SIZE 1
#define SSC_RFMR_MSBF_OFFSET 7
/* SSC Transmit Clock Mode Register */
#define SSC_TCMR 0x00000018
#define SSC_TCMR_CKG_SIZE 2
#define SSC_TCMR_CKG_OFFSET 6
#define SSC_TCMR_CKI_SIZE 1
#define SSC_TCMR_CKI_OFFSET 5
#define SSC_TCMR_CKO_SIZE 3
#define SSC_TCMR_CKO_OFFSET 2
#define SSC_TCMR_CKS_SIZE 2
#define SSC_TCMR_CKS_OFFSET 0
#define SSC_TCMR_PERIOD_SIZE 8
#define SSC_TCMR_PERIOD_OFFSET 24
#define SSC_TCMR_START_SIZE 4
#define SSC_TCMR_START_OFFSET 8
#define SSC_TCMR_STTDLY_SIZE 8
#define SSC_TCMR_STTDLY_OFFSET 16
/* SSC Transmit Frame Mode Register */
#define SSC_TFMR 0x0000001c
#define SSC_TFMR_DATDEF_SIZE 1
#define SSC_TFMR_DATDEF_OFFSET 5
#define SSC_TFMR_DATLEN_SIZE 5
#define SSC_TFMR_DATLEN_OFFSET 0
#define SSC_TFMR_DATNB_SIZE 4
#define SSC_TFMR_DATNB_OFFSET 8
#define SSC_TFMR_FSDEN_SIZE 1
#define SSC_TFMR_FSDEN_OFFSET 23
#define SSC_TFMR_FSEDGE_SIZE 1
#define SSC_TFMR_FSEDGE_OFFSET 24
/*
* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
* at91sam9g20, and at91sam9g45 and newer SoCs
*/
#define SSC_TFMR_FSLEN_EXT_SIZE 4
#define SSC_TFMR_FSLEN_EXT_OFFSET 28
#define SSC_TFMR_FSLEN_SIZE 4
#define SSC_TFMR_FSLEN_OFFSET 16
#define SSC_TFMR_FSOS_SIZE 3
#define SSC_TFMR_FSOS_OFFSET 20
#define SSC_TFMR_MSBF_SIZE 1
#define SSC_TFMR_MSBF_OFFSET 7
/* SSC Receive Hold Register */
#define SSC_RHR 0x00000020
#define SSC_RHR_RDAT_SIZE 32
#define SSC_RHR_RDAT_OFFSET 0
/* SSC Transmit Hold Register */
#define SSC_THR 0x00000024
#define SSC_THR_TDAT_SIZE 32
#define SSC_THR_TDAT_OFFSET 0
/* SSC Receive Sync. Holding Register */
#define SSC_RSHR 0x00000030
#define SSC_RSHR_RSDAT_SIZE 16
#define SSC_RSHR_RSDAT_OFFSET 0
/* SSC Transmit Sync. Holding Register */
#define SSC_TSHR 0x00000034
#define SSC_TSHR_TSDAT_SIZE 16
#define SSC_TSHR_RSDAT_OFFSET 0
/* SSC Receive Compare 0 Register */
#define SSC_RC0R 0x00000038
#define SSC_RC0R_CP0_SIZE 16
#define SSC_RC0R_CP0_OFFSET 0
/* SSC Receive Compare 1 Register */
#define SSC_RC1R 0x0000003c
#define SSC_RC1R_CP1_SIZE 16
#define SSC_RC1R_CP1_OFFSET 0
/* SSC Status Register */
#define SSC_SR 0x00000040
#define SSC_SR_CP0_SIZE 1
#define SSC_SR_CP0_OFFSET 8
#define SSC_SR_CP1_SIZE 1
#define SSC_SR_CP1_OFFSET 9
#define SSC_SR_ENDRX_SIZE 1
#define SSC_SR_ENDRX_OFFSET 6
#define SSC_SR_ENDTX_SIZE 1
#define SSC_SR_ENDTX_OFFSET 2
#define SSC_SR_OVRUN_SIZE 1
#define SSC_SR_OVRUN_OFFSET 5
#define SSC_SR_RXBUFF_SIZE 1
#define SSC_SR_RXBUFF_OFFSET 7
#define SSC_SR_RXEN_SIZE 1
#define SSC_SR_RXEN_OFFSET 17
#define SSC_SR_RXRDY_SIZE 1
#define SSC_SR_RXRDY_OFFSET 4
#define SSC_SR_RXSYN_SIZE 1
#define SSC_SR_RXSYN_OFFSET 11
#define SSC_SR_TXBUFE_SIZE 1
#define SSC_SR_TXBUFE_OFFSET 3
#define SSC_SR_TXEMPTY_SIZE 1
#define SSC_SR_TXEMPTY_OFFSET 1
#define SSC_SR_TXEN_SIZE 1
#define SSC_SR_TXEN_OFFSET 16
#define SSC_SR_TXRDY_SIZE 1
#define SSC_SR_TXRDY_OFFSET 0
#define SSC_SR_TXSYN_SIZE 1
#define SSC_SR_TXSYN_OFFSET 10
/* SSC Interrupt Enable Register */
#define SSC_IER 0x00000044
#define SSC_IER_CP0_SIZE 1
#define SSC_IER_CP0_OFFSET 8
#define SSC_IER_CP1_SIZE 1
#define SSC_IER_CP1_OFFSET 9
#define SSC_IER_ENDRX_SIZE 1
#define SSC_IER_ENDRX_OFFSET 6
#define SSC_IER_ENDTX_SIZE 1
#define SSC_IER_ENDTX_OFFSET 2
#define SSC_IER_OVRUN_SIZE 1
#define SSC_IER_OVRUN_OFFSET 5
#define SSC_IER_RXBUFF_SIZE 1
#define SSC_IER_RXBUFF_OFFSET 7
#define SSC_IER_RXRDY_SIZE 1
#define SSC_IER_RXRDY_OFFSET 4
#define SSC_IER_RXSYN_SIZE 1
#define SSC_IER_RXSYN_OFFSET 11
#define SSC_IER_TXBUFE_SIZE 1
#define SSC_IER_TXBUFE_OFFSET 3
#define SSC_IER_TXEMPTY_SIZE 1
#define SSC_IER_TXEMPTY_OFFSET 1
#define SSC_IER_TXRDY_SIZE 1
#define SSC_IER_TXRDY_OFFSET 0
#define SSC_IER_TXSYN_SIZE 1
#define SSC_IER_TXSYN_OFFSET 10
/* SSC Interrupt Disable Register */
#define SSC_IDR 0x00000048
#define SSC_IDR_CP0_SIZE 1
#define SSC_IDR_CP0_OFFSET 8
#define SSC_IDR_CP1_SIZE 1
#define SSC_IDR_CP1_OFFSET 9
#define SSC_IDR_ENDRX_SIZE 1
#define SSC_IDR_ENDRX_OFFSET 6
#define SSC_IDR_ENDTX_SIZE 1
#define SSC_IDR_ENDTX_OFFSET 2
#define SSC_IDR_OVRUN_SIZE 1
#define SSC_IDR_OVRUN_OFFSET 5
#define SSC_IDR_RXBUFF_SIZE 1
#define SSC_IDR_RXBUFF_OFFSET 7
#define SSC_IDR_RXRDY_SIZE 1
#define SSC_IDR_RXRDY_OFFSET 4
#define SSC_IDR_RXSYN_SIZE 1
#define SSC_IDR_RXSYN_OFFSET 11
#define SSC_IDR_TXBUFE_SIZE 1
#define SSC_IDR_TXBUFE_OFFSET 3
#define SSC_IDR_TXEMPTY_SIZE 1
#define SSC_IDR_TXEMPTY_OFFSET 1
#define SSC_IDR_TXRDY_SIZE 1
#define SSC_IDR_TXRDY_OFFSET 0
#define SSC_IDR_TXSYN_SIZE 1
#define SSC_IDR_TXSYN_OFFSET 10
/* SSC Interrupt Mask Register */
#define SSC_IMR 0x0000004c
#define SSC_IMR_CP0_SIZE 1
#define SSC_IMR_CP0_OFFSET 8
#define SSC_IMR_CP1_SIZE 1
#define SSC_IMR_CP1_OFFSET 9
#define SSC_IMR_ENDRX_SIZE 1
#define SSC_IMR_ENDRX_OFFSET 6
#define SSC_IMR_ENDTX_SIZE 1
#define SSC_IMR_ENDTX_OFFSET 2
#define SSC_IMR_OVRUN_SIZE 1
#define SSC_IMR_OVRUN_OFFSET 5
#define SSC_IMR_RXBUFF_SIZE 1
#define SSC_IMR_RXBUFF_OFFSET 7
#define SSC_IMR_RXRDY_SIZE 1
#define SSC_IMR_RXRDY_OFFSET 4
#define SSC_IMR_RXSYN_SIZE 1
#define SSC_IMR_RXSYN_OFFSET 11
#define SSC_IMR_TXBUFE_SIZE 1
#define SSC_IMR_TXBUFE_OFFSET 3
#define SSC_IMR_TXEMPTY_SIZE 1
#define SSC_IMR_TXEMPTY_OFFSET 1
#define SSC_IMR_TXRDY_SIZE 1
#define SSC_IMR_TXRDY_OFFSET 0
#define SSC_IMR_TXSYN_SIZE 1
#define SSC_IMR_TXSYN_OFFSET 10
/* SSC PDC Receive Pointer Register */
#define SSC_PDC_RPR 0x00000100
/* SSC PDC Receive Counter Register */
#define SSC_PDC_RCR 0x00000104
/* SSC PDC Transmit Pointer Register */
#define SSC_PDC_TPR 0x00000108
/* SSC PDC Receive Next Pointer Register */
#define SSC_PDC_RNPR 0x00000110
/* SSC PDC Receive Next Counter Register */
#define SSC_PDC_RNCR 0x00000114
/* SSC PDC Transmit Counter Register */
#define SSC_PDC_TCR 0x0000010c
/* SSC PDC Transmit Next Pointer Register */
#define SSC_PDC_TNPR 0x00000118
/* SSC PDC Transmit Next Counter Register */
#define SSC_PDC_TNCR 0x0000011c
/* SSC PDC Transfer Control Register */
#define SSC_PDC_PTCR 0x00000120
#define SSC_PDC_PTCR_RXTDIS_SIZE 1
#define SSC_PDC_PTCR_RXTDIS_OFFSET 1
#define SSC_PDC_PTCR_RXTEN_SIZE 1
#define SSC_PDC_PTCR_RXTEN_OFFSET 0
#define SSC_PDC_PTCR_TXTDIS_SIZE 1
#define SSC_PDC_PTCR_TXTDIS_OFFSET 9
#define SSC_PDC_PTCR_TXTEN_SIZE 1
#define SSC_PDC_PTCR_TXTEN_OFFSET 8
/* SSC PDC Transfer Status Register */
#define SSC_PDC_PTSR 0x00000124
#define SSC_PDC_PTSR_RXTEN_SIZE 1
#define SSC_PDC_PTSR_RXTEN_OFFSET 0
#define SSC_PDC_PTSR_TXTEN_SIZE 1
#define SSC_PDC_PTSR_TXTEN_OFFSET 8
/* Bit manipulation macros */
#define SSC_BIT(name) \
(1 << SSC_##name##_OFFSET)
#define SSC_BF(name, value) \
(((value) & ((1 << SSC_##name##_SIZE) - 1)) \
<< SSC_##name##_OFFSET)
#define SSC_BFEXT(name, value) \
(((value) >> SSC_##name##_OFFSET) \
& ((1 << SSC_##name##_SIZE) - 1))
#define SSC_BFINS(name, value, old) \
(((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
<< SSC_##name##_OFFSET)) | SSC_BF(name, value))
/* Register access macros */
#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
#endif /* __INCLUDE_ATMEL_SSC_H */

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/*
* include/linux/atmel_pdc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Peripheral Data Controller (PDC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef ATMEL_PDC_H
#define ATMEL_PDC_H
#define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
#define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
#define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
#define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
#define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
#define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
#define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
#define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
#define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
#define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
#define ATMEL_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
#define ATMEL_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
#define ATMEL_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
#define ATMEL_PDC_PTSR 0x124 /* Transfer Status Register */
#define ATMEL_PDC_SCND_BUF_OFF 0x10 /* Offset between first and second buffer registers */
#endif

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/*
* include/linux/atmel_serial.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* USART registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef ATMEL_SERIAL_H
#define ATMEL_SERIAL_H
#define ATMEL_US_CR 0x00 /* Control Register */
#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
#define ATMEL_US_SENDA (1 << 12) /* Send Address */
#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
#define ATMEL_US_MR 0x04 /* Mode Register */
#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
#define ATMEL_US_USMODE_NORMAL 0
#define ATMEL_US_USMODE_RS485 1
#define ATMEL_US_USMODE_HWHS 2
#define ATMEL_US_USMODE_MODEM 3
#define ATMEL_US_USMODE_ISO7816_T0 4
#define ATMEL_US_USMODE_ISO7816_T1 6
#define ATMEL_US_USMODE_IRDA 8
#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
#define ATMEL_US_USCLKS_MCK (0 << 4)
#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
#define ATMEL_US_USCLKS_SCK (3 << 4)
#define ATMEL_US_CHRL (3 << 6) /* Character Length */
#define ATMEL_US_CHRL_5 (0 << 6)
#define ATMEL_US_CHRL_6 (1 << 6)
#define ATMEL_US_CHRL_7 (2 << 6)
#define ATMEL_US_CHRL_8 (3 << 6)
#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
#define ATMEL_US_PAR (7 << 9) /* Parity Type */
#define ATMEL_US_PAR_EVEN (0 << 9)
#define ATMEL_US_PAR_ODD (1 << 9)
#define ATMEL_US_PAR_SPACE (2 << 9)
#define ATMEL_US_PAR_MARK (3 << 9)
#define ATMEL_US_PAR_NONE (4 << 9)
#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
#define ATMEL_US_NBSTOP_1 (0 << 12)
#define ATMEL_US_NBSTOP_1_5 (1 << 12)
#define ATMEL_US_NBSTOP_2 (2 << 12)
#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
#define ATMEL_US_CHMODE_NORMAL (0 << 14)
#define ATMEL_US_CHMODE_ECHO (1 << 14)
#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
#define ATMEL_US_PARE (1 << 7) /* Parity Error */
#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
#define ATMEL_US_RI (1 << 20) /* RI */
#define ATMEL_US_DSR (1 << 21) /* DSR */
#define ATMEL_US_DCD (1 << 22) /* DCD */
#define ATMEL_US_CTS (1 << 23) /* CTS */
#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
#define ATMEL_US_CSR 0x14 /* Channel Status Register */
#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
#define ATMEL_US_NER 0x44 /* Number of Errors Register */
#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
#define ATMEL_US_NAME 0xf0 /* Ip Name */
#define ATMEL_US_VERSION 0xfc /* Ip Version */
#endif

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/*
* Timer/Counter Unit (TC) registers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef ATMEL_TC_H
#define ATMEL_TC_H
#include <linux/compiler.h>
#include <linux/list.h>
/*
* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
* three general-purpose 16-bit timers. These timers share one register bank.
* Depending on the SOC, each timer may have its own clock and IRQ, or those
* may be shared by the whole TC block.
*
* These TC blocks may have up to nine external pins: TCLK0..2 signals for
* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
* or triggering. Those pins need to be set up for use with the TC block,
* else they will be used as GPIOs or for a different controller.
*
* Although we expect each TC block to have a platform_device node, those
* nodes are not what drivers bind to. Instead, they ask for a specific
* TC block, by number ... which is a common approach on systems with many
* timers. Then they use clk_get() and platform_get_irq() to get clock and
* IRQ resources.
*/
struct clk;
/**
* struct atmel_tcb_config - SoC data for a Timer/Counter Block
* @counter_width: size in bits of a timer counter register
*/
struct atmel_tcb_config {
size_t counter_width;
};
/**
* struct atmel_tc - information about a Timer/Counter Block
* @pdev: physical device
* @regs: mapping through which the I/O registers can be accessed
* @id: block id
* @tcb_config: configuration data from SoC
* @irq: irq for each of the three channels
* @clk: internal clock source for each of the three channels
* @node: list node, for tclib internal use
* @allocated: if already used, for tclib internal use
*
* On some platforms, each TC channel has its own clocks and IRQs,
* while on others, all TC channels share the same clock and IRQ.
* Drivers should clk_enable() all the clocks they need even though
* all the entries in @clk may point to the same physical clock.
* Likewise, drivers should request irqs independently for each
* channel, but they must use IRQF_SHARED in case some of the entries
* in @irq are actually the same IRQ.
*/
struct atmel_tc {
struct platform_device *pdev;
void __iomem *regs;
int id;
const struct atmel_tcb_config *tcb_config;
int irq[3];
struct clk *clk[3];
struct list_head node;
bool allocated;
};
extern struct atmel_tc *atmel_tc_alloc(unsigned block);
extern void atmel_tc_free(struct atmel_tc *tc);
/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
extern const u8 atmel_tc_divisors[5];
/*
* Two registers have block-wide controls. These are: configuring the three
* "external" clocks (or event sources) used by the timer channels; and
* synchronizing the timers by resetting them all at once.
*
* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
* signals. Or, it can mean "external to timer", using the TIOA output from
* one of the other two timers that's being run in waveform mode.
*/
#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
/*
* Each TC block has three "channels", each with one counter and controls.
*
* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
* when it's not "external") is silicon-specific. AT91 platforms use one
* set of definitions; AVR32 platforms use a different set. Don't hard-wire
* such knowledge into your code, use the global "atmel_tc_divisors" ...
* where index N is the divisor for clock N+1, else zero to indicate it uses
* the 32 KiHz clock.
*
* The timers can be chained in various ways, and operated in "waveform"
* generation mode (including PWM) or "capture" mode (to time events). In
* both modes, behavior can be configured in many ways.
*
* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
* uses them only as inputs.
*/
#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
/* Both modes share some CMR bits */
#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
#define ATMEL_TC_XC0 (5 << 0)
#define ATMEL_TC_XC1 (6 << 0)
#define ATMEL_TC_XC2 (7 << 0)
#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
#define ATMEL_TC_BURST (3 << 4) /* clock gating */
#define ATMEL_TC_GATE_NONE (0 << 4)
#define ATMEL_TC_GATE_XC0 (1 << 4)
#define ATMEL_TC_GATE_XC1 (2 << 4)
#define ATMEL_TC_GATE_XC2 (3 << 4)
#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
/* CAPTURE mode CMR bits */
#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
#define ATMEL_TC_LDRA_NONE (0 << 16)
#define ATMEL_TC_LDRA_RISING (1 << 16)
#define ATMEL_TC_LDRA_FALLING (2 << 16)
#define ATMEL_TC_LDRA_BOTH (3 << 16)
#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
#define ATMEL_TC_LDRB_NONE (0 << 18)
#define ATMEL_TC_LDRB_RISING (1 << 18)
#define ATMEL_TC_LDRB_FALLING (2 << 18)
#define ATMEL_TC_LDRB_BOTH (3 << 18)
/* WAVEFORM mode CMR bits */
#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
#define ATMEL_TC_EEVT (3 << 10) /* external event source */
#define ATMEL_TC_EEVT_TIOB (0 << 10)
#define ATMEL_TC_EEVT_XC0 (1 << 10)
#define ATMEL_TC_EEVT_XC1 (2 << 10)
#define ATMEL_TC_EEVT_XC2 (3 << 10)
#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
#define ATMEL_TC_WAVESEL_UP (0 << 13)
#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
#define ATMEL_TC_ACPA_NONE (0 << 16)
#define ATMEL_TC_ACPA_SET (1 << 16)
#define ATMEL_TC_ACPA_CLEAR (2 << 16)
#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
#define ATMEL_TC_ACPC_NONE (0 << 18)
#define ATMEL_TC_ACPC_SET (1 << 18)
#define ATMEL_TC_ACPC_CLEAR (2 << 18)
#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
#define ATMEL_TC_AEEVT_NONE (0 << 20)
#define ATMEL_TC_AEEVT_SET (1 << 20)
#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
#define ATMEL_TC_ASWTRG_NONE (0 << 22)
#define ATMEL_TC_ASWTRG_SET (1 << 22)
#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
#define ATMEL_TC_BCPB_NONE (0 << 24)
#define ATMEL_TC_BCPB_SET (1 << 24)
#define ATMEL_TC_BCPB_CLEAR (2 << 24)
#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
#define ATMEL_TC_BCPC_NONE (0 << 26)
#define ATMEL_TC_BCPC_SET (1 << 26)
#define ATMEL_TC_BCPC_CLEAR (2 << 26)
#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
#define ATMEL_TC_BEEVT_NONE (0 << 28)
#define ATMEL_TC_BEEVT_SET (1 << 28)
#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
#define ATMEL_TC_BSWTRG_NONE (0 << 30)
#define ATMEL_TC_BSWTRG_SET (1 << 30)
#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
#define ATMEL_TC_CV 0x10 /* counter Value */
#define ATMEL_TC_RA 0x14 /* register A */
#define ATMEL_TC_RB 0x18 /* register B */
#define ATMEL_TC_RC 0x1c /* register C */
#define ATMEL_TC_SR 0x20 /* status (read-only) */
/* Status-only flags */
#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
/* Status and IRQ flags */
#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
#define ATMEL_TC_ALL_IRQ (ATMEL_TC_COVFS | ATMEL_TC_LOVRS | \
ATMEL_TC_CPAS | ATMEL_TC_CPBS | \
ATMEL_TC_CPCS | ATMEL_TC_LDRAS | \
ATMEL_TC_LDRBS | ATMEL_TC_ETRGS) \
/* all IRQs */
#endif

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/* Atomic operations usable in machine independent code */
#ifndef _LINUX_ATOMIC_H
#define _LINUX_ATOMIC_H
#include <asm/atomic.h>
/**
* atomic_add_unless - add unless the number is already a given value
* @v: pointer of type atomic_t
* @a: the amount to add to v...
* @u: ...unless v is equal to u.
*
* Atomically adds @a to @v, so long as @v was not already @u.
* Returns non-zero if @v was not @u, and zero otherwise.
*/
static inline int atomic_add_unless(atomic_t *v, int a, int u)
{
return __atomic_add_unless(v, a, u) != u;
}
/**
* atomic_inc_not_zero - increment unless the number is zero
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1, so long as @v is non-zero.
* Returns non-zero if @v was non-zero, and zero otherwise.
*/
#ifndef atomic_inc_not_zero
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
#endif
/**
* atomic_inc_not_zero_hint - increment if not null
* @v: pointer of type atomic_t
* @hint: probable value of the atomic before the increment
*
* This version of atomic_inc_not_zero() gives a hint of probable
* value of the atomic. This helps processor to not read the memory
* before doing the atomic read/modify/write cycle, lowering
* number of bus transactions on some arches.
*
* Returns: 0 if increment was not done, 1 otherwise.
*/
#ifndef atomic_inc_not_zero_hint
static inline int atomic_inc_not_zero_hint(atomic_t *v, int hint)
{
int val, c = hint;
/* sanity test, should be removed by compiler if hint is a constant */
if (!hint)
return atomic_inc_not_zero(v);
do {
val = atomic_cmpxchg(v, c, c + 1);
if (val == c)
return 1;
c = val;
} while (c);
return 0;
}
#endif
#ifndef atomic_inc_unless_negative
static inline int atomic_inc_unless_negative(atomic_t *p)
{
int v, v1;
for (v = 0; v >= 0; v = v1) {
v1 = atomic_cmpxchg(p, v, v + 1);
if (likely(v1 == v))
return 1;
}
return 0;
}
#endif
#ifndef atomic_dec_unless_positive
static inline int atomic_dec_unless_positive(atomic_t *p)
{
int v, v1;
for (v = 0; v <= 0; v = v1) {
v1 = atomic_cmpxchg(p, v, v - 1);
if (likely(v1 == v))
return 1;
}
return 0;
}
#endif
/*
* atomic_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic_t
*
* The function returns the old value of *v minus 1, even if
* the atomic variable, v, was not decremented.
*/
#ifndef atomic_dec_if_positive
static inline int atomic_dec_if_positive(atomic_t *v)
{
int c, old, dec;
c = atomic_read(v);
for (;;) {
dec = c - 1;
if (unlikely(dec < 0))
break;
old = atomic_cmpxchg((v), c, dec);
if (likely(old == c))
break;
c = old;
}
return dec;
}
#endif
#ifndef CONFIG_ARCH_HAS_ATOMIC_OR
static inline void atomic_or(int i, atomic_t *v)
{
int old;
int new;
do {
old = atomic_read(v);
new = old | i;
} while (atomic_cmpxchg(v, old, new) != old);
}
#endif /* #ifndef CONFIG_ARCH_HAS_ATOMIC_OR */
#include <asm-generic/atomic-long.h>
#ifdef CONFIG_GENERIC_ATOMIC64
#include <asm-generic/atomic64.h>
#endif
#endif /* _LINUX_ATOMIC_H */

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/*
* attribute_container.h - a generic container for all classes
*
* Copyright (c) 2005 - James Bottomley <James.Bottomley@steeleye.com>
*
* This file is licensed under GPLv2
*/
#ifndef _ATTRIBUTE_CONTAINER_H_
#define _ATTRIBUTE_CONTAINER_H_
#include <linux/list.h>
#include <linux/klist.h>
struct device;
struct attribute_container {
struct list_head node;
struct klist containers;
struct class *class;
const struct attribute_group *grp;
struct device_attribute **attrs;
int (*match)(struct attribute_container *, struct device *);
#define ATTRIBUTE_CONTAINER_NO_CLASSDEVS 0x01
unsigned long flags;
};
static inline int
attribute_container_no_classdevs(struct attribute_container *atc)
{
return atc->flags & ATTRIBUTE_CONTAINER_NO_CLASSDEVS;
}
static inline void
attribute_container_set_no_classdevs(struct attribute_container *atc)
{
atc->flags |= ATTRIBUTE_CONTAINER_NO_CLASSDEVS;
}
int attribute_container_register(struct attribute_container *cont);
int __must_check attribute_container_unregister(struct attribute_container *cont);
void attribute_container_create_device(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
struct device *));
void attribute_container_add_device(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
struct device *));
void attribute_container_remove_device(struct device *dev,
void (*fn)(struct attribute_container *,
struct device *,
struct device *));
void attribute_container_device_trigger(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
struct device *));
void attribute_container_trigger(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *));
int attribute_container_add_attrs(struct device *classdev);
int attribute_container_add_class_device(struct device *classdev);
int attribute_container_add_class_device_adapter(struct attribute_container *cont,
struct device *dev,
struct device *classdev);
void attribute_container_remove_attrs(struct device *classdev);
void attribute_container_class_device_del(struct device *classdev);
struct attribute_container *attribute_container_classdev_to_container(struct device *);
struct device *attribute_container_find_class_device(struct attribute_container *, struct device *);
struct device_attribute **attribute_container_classdev_to_attrs(const struct device *classdev);
#endif

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/* audit.h -- Auditing support
*
* Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Written by Rickard E. (Rik) Faith <faith@redhat.com>
*
*/
#ifndef _LINUX_AUDIT_H_
#define _LINUX_AUDIT_H_
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <uapi/linux/audit.h>
struct audit_sig_info {
uid_t uid;
pid_t pid;
char ctx[0];
};
struct audit_buffer;
struct audit_context;
struct inode;
struct netlink_skb_parms;
struct path;
struct linux_binprm;
struct mq_attr;
struct mqstat;
struct audit_watch;
struct audit_tree;
struct sk_buff;
struct audit_krule {
int vers_ops;
u32 pflags;
u32 flags;
u32 listnr;
u32 action;
u32 mask[AUDIT_BITMASK_SIZE];
u32 buflen; /* for data alloc on list rules */
u32 field_count;
char *filterkey; /* ties events to rules */
struct audit_field *fields;
struct audit_field *arch_f; /* quick access to arch field */
struct audit_field *inode_f; /* quick access to an inode field */
struct audit_watch *watch; /* associated watch */
struct audit_tree *tree; /* associated watched tree */
struct list_head rlist; /* entry in audit_{watch,tree}.rules list */
struct list_head list; /* for AUDIT_LIST* purposes only */
u64 prio;
};
/* Flag to indicate legacy AUDIT_LOGINUID unset usage */
#define AUDIT_LOGINUID_LEGACY 0x1
struct audit_field {
u32 type;
union {
u32 val;
kuid_t uid;
kgid_t gid;
struct {
char *lsm_str;
void *lsm_rule;
};
};
u32 op;
};
extern int is_audit_feature_set(int which);
extern int __init audit_register_class(int class, unsigned *list);
extern int audit_classify_syscall(int abi, unsigned syscall);
extern int audit_classify_arch(int arch);
/* only for compat system calls */
extern unsigned compat_write_class[];
extern unsigned compat_read_class[];
extern unsigned compat_dir_class[];
extern unsigned compat_chattr_class[];
extern unsigned compat_signal_class[];
extern int audit_classify_compat_syscall(int abi, unsigned syscall);
/* audit_names->type values */
#define AUDIT_TYPE_UNKNOWN 0 /* we don't know yet */
#define AUDIT_TYPE_NORMAL 1 /* a "normal" audit record */
#define AUDIT_TYPE_PARENT 2 /* a parent audit record */
#define AUDIT_TYPE_CHILD_DELETE 3 /* a child being deleted */
#define AUDIT_TYPE_CHILD_CREATE 4 /* a child being created */
/* maximized args number that audit_socketcall can process */
#define AUDITSC_ARGS 6
struct filename;
extern void audit_log_session_info(struct audit_buffer *ab);
#ifdef CONFIG_AUDIT_COMPAT_GENERIC
#define audit_is_compat(arch) (!((arch) & __AUDIT_ARCH_64BIT))
#else
#define audit_is_compat(arch) false
#endif
#ifdef CONFIG_AUDITSYSCALL
#include <asm/syscall.h> /* for syscall_get_arch() */
/* These are defined in auditsc.c */
/* Public API */
extern int audit_alloc(struct task_struct *task);
extern void __audit_free(struct task_struct *task);
extern void __audit_syscall_entry(int major, unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3);
extern void __audit_syscall_exit(int ret_success, long ret_value);
extern struct filename *__audit_reusename(const __user char *uptr);
extern void __audit_getname(struct filename *name);
extern void audit_putname(struct filename *name);
#define AUDIT_INODE_PARENT 1 /* dentry represents the parent */
#define AUDIT_INODE_HIDDEN 2 /* audit record should be hidden */
extern void __audit_inode(struct filename *name, const struct dentry *dentry,
unsigned int flags);
extern void __audit_inode_child(const struct inode *parent,
const struct dentry *dentry,
const unsigned char type);
extern void __audit_seccomp(unsigned long syscall, long signr, int code);
extern void __audit_ptrace(struct task_struct *t);
static inline int audit_dummy_context(void)
{
void *p = current->audit_context;
return !p || *(int *)p;
}
static inline void audit_free(struct task_struct *task)
{
if (unlikely(task->audit_context))
__audit_free(task);
}
static inline void audit_syscall_entry(int major, unsigned long a0,
unsigned long a1, unsigned long a2,
unsigned long a3)
{
if (unlikely(current->audit_context))
__audit_syscall_entry(major, a0, a1, a2, a3);
}
static inline void audit_syscall_exit(void *pt_regs)
{
if (unlikely(current->audit_context)) {
int success = is_syscall_success(pt_regs);
long return_code = regs_return_value(pt_regs);
__audit_syscall_exit(success, return_code);
}
}
static inline struct filename *audit_reusename(const __user char *name)
{
if (unlikely(!audit_dummy_context()))
return __audit_reusename(name);
return NULL;
}
static inline void audit_getname(struct filename *name)
{
if (unlikely(!audit_dummy_context()))
__audit_getname(name);
}
static inline void audit_inode(struct filename *name,
const struct dentry *dentry,
unsigned int parent) {
if (unlikely(!audit_dummy_context())) {
unsigned int flags = 0;
if (parent)
flags |= AUDIT_INODE_PARENT;
__audit_inode(name, dentry, flags);
}
}
static inline void audit_inode_parent_hidden(struct filename *name,
const struct dentry *dentry)
{
if (unlikely(!audit_dummy_context()))
__audit_inode(name, dentry,
AUDIT_INODE_PARENT | AUDIT_INODE_HIDDEN);
}
static inline void audit_inode_child(const struct inode *parent,
const struct dentry *dentry,
const unsigned char type) {
if (unlikely(!audit_dummy_context()))
__audit_inode_child(parent, dentry, type);
}
void audit_core_dumps(long signr);
static inline void audit_seccomp(unsigned long syscall, long signr, int code)
{
/* Force a record to be reported if a signal was delivered. */
if (signr || unlikely(!audit_dummy_context()))
__audit_seccomp(syscall, signr, code);
}
static inline void audit_ptrace(struct task_struct *t)
{
if (unlikely(!audit_dummy_context()))
__audit_ptrace(t);
}
/* Private API (for audit.c only) */
extern unsigned int audit_serial(void);
extern int auditsc_get_stamp(struct audit_context *ctx,
struct timespec *t, unsigned int *serial);
extern int audit_set_loginuid(kuid_t loginuid);
static inline kuid_t audit_get_loginuid(struct task_struct *tsk)
{
return tsk->loginuid;
}
static inline unsigned int audit_get_sessionid(struct task_struct *tsk)
{
return tsk->sessionid;
}
extern void __audit_ipc_obj(struct kern_ipc_perm *ipcp);
extern void __audit_ipc_set_perm(unsigned long qbytes, uid_t uid, gid_t gid, umode_t mode);
extern void __audit_bprm(struct linux_binprm *bprm);
extern int __audit_socketcall(int nargs, unsigned long *args);
extern int __audit_sockaddr(int len, void *addr);
extern void __audit_fd_pair(int fd1, int fd2);
extern void __audit_mq_open(int oflag, umode_t mode, struct mq_attr *attr);
extern void __audit_mq_sendrecv(mqd_t mqdes, size_t msg_len, unsigned int msg_prio, const struct timespec *abs_timeout);
extern void __audit_mq_notify(mqd_t mqdes, const struct sigevent *notification);
extern void __audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat);
extern int __audit_log_bprm_fcaps(struct linux_binprm *bprm,
const struct cred *new,
const struct cred *old);
extern void __audit_log_capset(const struct cred *new, const struct cred *old);
extern void __audit_mmap_fd(int fd, int flags);
static inline void audit_ipc_obj(struct kern_ipc_perm *ipcp)
{
if (unlikely(!audit_dummy_context()))
__audit_ipc_obj(ipcp);
}
static inline void audit_fd_pair(int fd1, int fd2)
{
if (unlikely(!audit_dummy_context()))
__audit_fd_pair(fd1, fd2);
}
static inline void audit_ipc_set_perm(unsigned long qbytes, uid_t uid, gid_t gid, umode_t mode)
{
if (unlikely(!audit_dummy_context()))
__audit_ipc_set_perm(qbytes, uid, gid, mode);
}
static inline void audit_bprm(struct linux_binprm *bprm)
{
if (unlikely(!audit_dummy_context()))
__audit_bprm(bprm);
}
static inline int audit_socketcall(int nargs, unsigned long *args)
{
if (unlikely(!audit_dummy_context()))
return __audit_socketcall(nargs, args);
return 0;
}
static inline int audit_sockaddr(int len, void *addr)
{
if (unlikely(!audit_dummy_context()))
return __audit_sockaddr(len, addr);
return 0;
}
static inline void audit_mq_open(int oflag, umode_t mode, struct mq_attr *attr)
{
if (unlikely(!audit_dummy_context()))
__audit_mq_open(oflag, mode, attr);
}
static inline void audit_mq_sendrecv(mqd_t mqdes, size_t msg_len, unsigned int msg_prio, const struct timespec *abs_timeout)
{
if (unlikely(!audit_dummy_context()))
__audit_mq_sendrecv(mqdes, msg_len, msg_prio, abs_timeout);
}
static inline void audit_mq_notify(mqd_t mqdes, const struct sigevent *notification)
{
if (unlikely(!audit_dummy_context()))
__audit_mq_notify(mqdes, notification);
}
static inline void audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat)
{
if (unlikely(!audit_dummy_context()))
__audit_mq_getsetattr(mqdes, mqstat);
}
static inline int audit_log_bprm_fcaps(struct linux_binprm *bprm,
const struct cred *new,
const struct cred *old)
{
if (unlikely(!audit_dummy_context()))
return __audit_log_bprm_fcaps(bprm, new, old);
return 0;
}
static inline void audit_log_capset(const struct cred *new,
const struct cred *old)
{
if (unlikely(!audit_dummy_context()))
__audit_log_capset(new, old);
}
static inline void audit_mmap_fd(int fd, int flags)
{
if (unlikely(!audit_dummy_context()))
__audit_mmap_fd(fd, flags);
}
extern int audit_n_rules;
extern int audit_signals;
#else /* CONFIG_AUDITSYSCALL */
static inline int audit_alloc(struct task_struct *task)
{
return 0;
}
static inline void audit_free(struct task_struct *task)
{ }
static inline void audit_syscall_entry(int major, unsigned long a0,
unsigned long a1, unsigned long a2,
unsigned long a3)
{ }
static inline void audit_syscall_exit(void *pt_regs)
{ }
static inline int audit_dummy_context(void)
{
return 1;
}
static inline struct filename *audit_reusename(const __user char *name)
{
return NULL;
}
static inline void audit_getname(struct filename *name)
{ }
static inline void audit_putname(struct filename *name)
{ }
static inline void __audit_inode(struct filename *name,
const struct dentry *dentry,
unsigned int flags)
{ }
static inline void __audit_inode_child(const struct inode *parent,
const struct dentry *dentry,
const unsigned char type)
{ }
static inline void audit_inode(struct filename *name,
const struct dentry *dentry,
unsigned int parent)
{ }
static inline void audit_inode_parent_hidden(struct filename *name,
const struct dentry *dentry)
{ }
static inline void audit_inode_child(const struct inode *parent,
const struct dentry *dentry,
const unsigned char type)
{ }
static inline void audit_core_dumps(long signr)
{ }
static inline void __audit_seccomp(unsigned long syscall, long signr, int code)
{ }
static inline void audit_seccomp(unsigned long syscall, long signr, int code)
{ }
static inline int auditsc_get_stamp(struct audit_context *ctx,
struct timespec *t, unsigned int *serial)
{
return 0;
}
static inline kuid_t audit_get_loginuid(struct task_struct *tsk)
{
return INVALID_UID;
}
static inline unsigned int audit_get_sessionid(struct task_struct *tsk)
{
return -1;
}
static inline void audit_ipc_obj(struct kern_ipc_perm *ipcp)
{ }
static inline void audit_ipc_set_perm(unsigned long qbytes, uid_t uid,
gid_t gid, umode_t mode)
{ }
static inline void audit_bprm(struct linux_binprm *bprm)
{ }
static inline int audit_socketcall(int nargs, unsigned long *args)
{
return 0;
}
static inline void audit_fd_pair(int fd1, int fd2)
{ }
static inline int audit_sockaddr(int len, void *addr)
{
return 0;
}
static inline void audit_mq_open(int oflag, umode_t mode, struct mq_attr *attr)
{ }
static inline void audit_mq_sendrecv(mqd_t mqdes, size_t msg_len,
unsigned int msg_prio,
const struct timespec *abs_timeout)
{ }
static inline void audit_mq_notify(mqd_t mqdes,
const struct sigevent *notification)
{ }
static inline void audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat)
{ }
static inline int audit_log_bprm_fcaps(struct linux_binprm *bprm,
const struct cred *new,
const struct cred *old)
{
return 0;
}
static inline void audit_log_capset(const struct cred *new,
const struct cred *old)
{ }
static inline void audit_mmap_fd(int fd, int flags)
{ }
static inline void audit_ptrace(struct task_struct *t)
{ }
#define audit_n_rules 0
#define audit_signals 0
#endif /* CONFIG_AUDITSYSCALL */
static inline bool audit_loginuid_set(struct task_struct *tsk)
{
return uid_valid(audit_get_loginuid(tsk));
}
#ifdef CONFIG_AUDIT
/* These are defined in audit.c */
/* Public API */
extern __printf(4, 5)
void audit_log(struct audit_context *ctx, gfp_t gfp_mask, int type,
const char *fmt, ...);
extern struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, int type);
extern __printf(2, 3)
void audit_log_format(struct audit_buffer *ab, const char *fmt, ...);
extern void audit_log_end(struct audit_buffer *ab);
extern int audit_string_contains_control(const char *string,
size_t len);
extern void audit_log_n_hex(struct audit_buffer *ab,
const unsigned char *buf,
size_t len);
extern void audit_log_n_string(struct audit_buffer *ab,
const char *buf,
size_t n);
extern void audit_log_n_untrustedstring(struct audit_buffer *ab,
const char *string,
size_t n);
extern void audit_log_untrustedstring(struct audit_buffer *ab,
const char *string);
extern void audit_log_d_path(struct audit_buffer *ab,
const char *prefix,
const struct path *path);
extern void audit_log_key(struct audit_buffer *ab,
char *key);
extern void audit_log_link_denied(const char *operation,
struct path *link);
extern void audit_log_lost(const char *message);
#ifdef CONFIG_SECURITY
extern void audit_log_secctx(struct audit_buffer *ab, u32 secid);
#else
static inline void audit_log_secctx(struct audit_buffer *ab, u32 secid)
{ }
#endif
extern int audit_log_task_context(struct audit_buffer *ab);
extern void audit_log_task_info(struct audit_buffer *ab,
struct task_struct *tsk);
extern int audit_update_lsm_rules(void);
/* Private API (for audit.c only) */
extern int audit_filter_user(int type);
extern int audit_filter_type(int type);
extern int audit_rule_change(int type, __u32 portid, int seq,
void *data, size_t datasz);
extern int audit_list_rules_send(struct sk_buff *request_skb, int seq);
extern u32 audit_enabled;
#else /* CONFIG_AUDIT */
static inline __printf(4, 5)
void audit_log(struct audit_context *ctx, gfp_t gfp_mask, int type,
const char *fmt, ...)
{ }
static inline struct audit_buffer *audit_log_start(struct audit_context *ctx,
gfp_t gfp_mask, int type)
{
return NULL;
}
static inline __printf(2, 3)
void audit_log_format(struct audit_buffer *ab, const char *fmt, ...)
{ }
static inline void audit_log_end(struct audit_buffer *ab)
{ }
static inline void audit_log_n_hex(struct audit_buffer *ab,
const unsigned char *buf, size_t len)
{ }
static inline void audit_log_n_string(struct audit_buffer *ab,
const char *buf, size_t n)
{ }
static inline void audit_log_n_untrustedstring(struct audit_buffer *ab,
const char *string, size_t n)
{ }
static inline void audit_log_untrustedstring(struct audit_buffer *ab,
const char *string)
{ }
static inline void audit_log_d_path(struct audit_buffer *ab,
const char *prefix,
const struct path *path)
{ }
static inline void audit_log_key(struct audit_buffer *ab, char *key)
{ }
static inline void audit_log_link_denied(const char *string,
const struct path *link)
{ }
static inline void audit_log_secctx(struct audit_buffer *ab, u32 secid)
{ }
static inline int audit_log_task_context(struct audit_buffer *ab)
{
return 0;
}
static inline void audit_log_task_info(struct audit_buffer *ab,
struct task_struct *tsk)
{ }
#define audit_enabled 0
#endif /* CONFIG_AUDIT */
static inline void audit_log_string(struct audit_buffer *ab, const char *buf)
{
audit_log_n_string(ab, buf, strlen(buf));
}
#endif

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/*
* Copyright 2008 Red Hat, Inc. All rights reserved.
* Copyright 2008 Ian Kent <raven@themaw.net>
*
* This file is part of the Linux kernel and is made available under
* the terms of the GNU General Public License, version 2, or at your
* option, any later version, incorporated herein by reference.
*/
#ifndef _LINUX_AUTO_DEV_IOCTL_H
#define _LINUX_AUTO_DEV_IOCTL_H
#include <linux/auto_fs.h>
#ifdef __KERNEL__
#include <linux/string.h>
#else
#include <string.h>
#endif /* __KERNEL__ */
#define AUTOFS_DEVICE_NAME "autofs"
#define AUTOFS_DEV_IOCTL_VERSION_MAJOR 1
#define AUTOFS_DEV_IOCTL_VERSION_MINOR 0
#define AUTOFS_DEVID_LEN 16
#define AUTOFS_DEV_IOCTL_SIZE sizeof(struct autofs_dev_ioctl)
/*
* An ioctl interface for autofs mount point control.
*/
struct args_protover {
__u32 version;
};
struct args_protosubver {
__u32 sub_version;
};
struct args_openmount {
__u32 devid;
};
struct args_ready {
__u32 token;
};
struct args_fail {
__u32 token;
__s32 status;
};
struct args_setpipefd {
__s32 pipefd;
};
struct args_timeout {
__u64 timeout;
};
struct args_requester {
__u32 uid;
__u32 gid;
};
struct args_expire {
__u32 how;
};
struct args_askumount {
__u32 may_umount;
};
struct args_ismountpoint {
union {
struct args_in {
__u32 type;
} in;
struct args_out {
__u32 devid;
__u32 magic;
} out;
};
};
/*
* All the ioctls use this structure.
* When sending a path size must account for the total length
* of the chunk of memory otherwise is is the size of the
* structure.
*/
struct autofs_dev_ioctl {
__u32 ver_major;
__u32 ver_minor;
__u32 size; /* total size of data passed in
* including this struct */
__s32 ioctlfd; /* automount command fd */
/* Command parameters */
union {
struct args_protover protover;
struct args_protosubver protosubver;
struct args_openmount openmount;
struct args_ready ready;
struct args_fail fail;
struct args_setpipefd setpipefd;
struct args_timeout timeout;
struct args_requester requester;
struct args_expire expire;
struct args_askumount askumount;
struct args_ismountpoint ismountpoint;
};
char path[0];
};
static inline void init_autofs_dev_ioctl(struct autofs_dev_ioctl *in)
{
memset(in, 0, sizeof(struct autofs_dev_ioctl));
in->ver_major = AUTOFS_DEV_IOCTL_VERSION_MAJOR;
in->ver_minor = AUTOFS_DEV_IOCTL_VERSION_MINOR;
in->size = sizeof(struct autofs_dev_ioctl);
in->ioctlfd = -1;
return;
}
/*
* If you change this make sure you make the corresponding change
* to autofs-dev-ioctl.c:lookup_ioctl()
*/
enum {
/* Get various version info */
AUTOFS_DEV_IOCTL_VERSION_CMD = 0x71,
AUTOFS_DEV_IOCTL_PROTOVER_CMD,
AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD,
/* Open mount ioctl fd */
AUTOFS_DEV_IOCTL_OPENMOUNT_CMD,
/* Close mount ioctl fd */
AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD,
/* Mount/expire status returns */
AUTOFS_DEV_IOCTL_READY_CMD,
AUTOFS_DEV_IOCTL_FAIL_CMD,
/* Activate/deactivate autofs mount */
AUTOFS_DEV_IOCTL_SETPIPEFD_CMD,
AUTOFS_DEV_IOCTL_CATATONIC_CMD,
/* Expiry timeout */
AUTOFS_DEV_IOCTL_TIMEOUT_CMD,
/* Get mount last requesting uid and gid */
AUTOFS_DEV_IOCTL_REQUESTER_CMD,
/* Check for eligible expire candidates */
AUTOFS_DEV_IOCTL_EXPIRE_CMD,
/* Request busy status */
AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD,
/* Check if path is a mountpoint */
AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD,
};
#define AUTOFS_IOCTL 0x93
#define AUTOFS_DEV_IOCTL_VERSION \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_VERSION_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_PROTOVER \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_PROTOVER_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_PROTOSUBVER \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_OPENMOUNT \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_OPENMOUNT_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_CLOSEMOUNT \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_READY \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_READY_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_FAIL \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_FAIL_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_SETPIPEFD \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_SETPIPEFD_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_CATATONIC \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_CATATONIC_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_TIMEOUT \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_TIMEOUT_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_REQUESTER \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_REQUESTER_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_EXPIRE \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_EXPIRE_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_ASKUMOUNT \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD, struct autofs_dev_ioctl)
#define AUTOFS_DEV_IOCTL_ISMOUNTPOINT \
_IOWR(AUTOFS_IOCTL, \
AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD, struct autofs_dev_ioctl)
#endif /* _LINUX_AUTO_DEV_IOCTL_H */

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/* -*- linux-c -*- ------------------------------------------------------- *
*
* linux/include/linux/auto_fs.h
*
* Copyright 1997 Transmeta Corporation - All Rights Reserved
*
* This file is part of the Linux kernel and is made available under
* the terms of the GNU General Public License, version 2, or at your
* option, any later version, incorporated herein by reference.
*
* ----------------------------------------------------------------------- */
#ifndef _LINUX_AUTO_FS_H
#define _LINUX_AUTO_FS_H
#include <linux/fs.h>
#include <linux/limits.h>
#include <linux/ioctl.h>
#include <uapi/linux/auto_fs.h>
#endif /* _LINUX_AUTO_FS_H */

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#ifndef _LINUX_AUXVEC_H
#define _LINUX_AUXVEC_H
#include <uapi/linux/auxvec.h>
#define AT_VECTOR_SIZE_BASE 20 /* NEW_AUX_ENT entries in auxiliary table */
/* number of "#define AT_.*" above, minus {AT_NULL, AT_IGNORE, AT_NOTELF} */
#endif /* _LINUX_AUXVEC_H */

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#ifndef _LINUX_AVERAGE_H
#define _LINUX_AVERAGE_H
/* Exponentially weighted moving average (EWMA) */
/* For more documentation see lib/average.c */
struct ewma {
unsigned long internal;
unsigned long factor;
unsigned long weight;
};
extern void ewma_init(struct ewma *avg, unsigned long factor,
unsigned long weight);
extern struct ewma *ewma_add(struct ewma *avg, unsigned long val);
/**
* ewma_read() - Get average value
* @avg: Average structure
*
* Returns the average value held in @avg.
*/
static inline unsigned long ewma_read(const struct ewma *avg)
{
return avg->internal >> avg->factor;
}
#endif /* _LINUX_AVERAGE_H */

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/* $Id: b1pcmcia.h,v 1.1.8.2 2001/09/23 22:25:05 kai Exp $
*
* Exported functions of module b1pcmcia to be called by
* avm_cs card services module.
*
* Copyright 1999 by Carsten Paeth (calle@calle.in-berlin.de)
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#ifndef _B1PCMCIA_H_
#define _B1PCMCIA_H_
int b1pcmcia_addcard_b1(unsigned int port, unsigned irq);
int b1pcmcia_addcard_m1(unsigned int port, unsigned irq);
int b1pcmcia_addcard_m2(unsigned int port, unsigned irq);
int b1pcmcia_delcard(unsigned int port, unsigned irq);
#endif /* _B1PCMCIA_H_ */

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/*
* include/linux/backing-dev.h
*
* low-level device information and state which is propagated up through
* to high-level code.
*/
#ifndef _LINUX_BACKING_DEV_H
#define _LINUX_BACKING_DEV_H
#include <linux/percpu_counter.h>
#include <linux/log2.h>
#include <linux/flex_proportions.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/writeback.h>
#include <linux/atomic.h>
#include <linux/sysctl.h>
#include <linux/workqueue.h>
struct page;
struct device;
struct dentry;
/*
* Bits in backing_dev_info.state
*/
enum bdi_state {
BDI_async_congested, /* The async (write) queue is getting full */
BDI_sync_congested, /* The sync queue is getting full */
BDI_registered, /* bdi_register() was done */
BDI_writeback_running, /* Writeback is in progress */
};
typedef int (congested_fn)(void *, int);
enum bdi_stat_item {
BDI_RECLAIMABLE,
BDI_WRITEBACK,
BDI_DIRTIED,
BDI_WRITTEN,
NR_BDI_STAT_ITEMS
};
#define BDI_STAT_BATCH (8*(1+ilog2(nr_cpu_ids)))
struct bdi_writeback {
struct backing_dev_info *bdi; /* our parent bdi */
unsigned long last_old_flush; /* last old data flush */
struct delayed_work dwork; /* work item used for writeback */
struct list_head b_dirty; /* dirty inodes */
struct list_head b_io; /* parked for writeback */
struct list_head b_more_io; /* parked for more writeback */
spinlock_t list_lock; /* protects the b_* lists */
};
struct backing_dev_info {
struct list_head bdi_list;
unsigned long ra_pages; /* max readahead in PAGE_CACHE_SIZE units */
unsigned long state; /* Always use atomic bitops on this */
unsigned int capabilities; /* Device capabilities */
congested_fn *congested_fn; /* Function pointer if device is md/dm */
void *congested_data; /* Pointer to aux data for congested func */
char *name;
struct percpu_counter bdi_stat[NR_BDI_STAT_ITEMS];
unsigned long bw_time_stamp; /* last time write bw is updated */
unsigned long dirtied_stamp;
unsigned long written_stamp; /* pages written at bw_time_stamp */
unsigned long write_bandwidth; /* the estimated write bandwidth */
unsigned long avg_write_bandwidth; /* further smoothed write bw */
/*
* The base dirty throttle rate, re-calculated on every 200ms.
* All the bdi tasks' dirty rate will be curbed under it.
* @dirty_ratelimit tracks the estimated @balanced_dirty_ratelimit
* in small steps and is much more smooth/stable than the latter.
*/
unsigned long dirty_ratelimit;
unsigned long balanced_dirty_ratelimit;
struct fprop_local_percpu completions;
int dirty_exceeded;
unsigned int min_ratio;
unsigned int max_ratio, max_prop_frac;
struct bdi_writeback wb; /* default writeback info for this bdi */
spinlock_t wb_lock; /* protects work_list & wb.dwork scheduling */
struct list_head work_list;
struct device *dev;
struct timer_list laptop_mode_wb_timer;
#ifdef CONFIG_DEBUG_FS
struct dentry *debug_dir;
struct dentry *debug_stats;
#endif
};
int __must_check bdi_init(struct backing_dev_info *bdi);
void bdi_destroy(struct backing_dev_info *bdi);
__printf(3, 4)
int bdi_register(struct backing_dev_info *bdi, struct device *parent,
const char *fmt, ...);
int bdi_register_dev(struct backing_dev_info *bdi, dev_t dev);
void bdi_unregister(struct backing_dev_info *bdi);
int __must_check bdi_setup_and_register(struct backing_dev_info *, char *, unsigned int);
void bdi_start_writeback(struct backing_dev_info *bdi, long nr_pages,
enum wb_reason reason);
void bdi_start_background_writeback(struct backing_dev_info *bdi);
void bdi_writeback_workfn(struct work_struct *work);
int bdi_has_dirty_io(struct backing_dev_info *bdi);
void bdi_wakeup_thread_delayed(struct backing_dev_info *bdi);
extern spinlock_t bdi_lock;
extern struct list_head bdi_list;
extern struct workqueue_struct *bdi_wq;
static inline int wb_has_dirty_io(struct bdi_writeback *wb)
{
return !list_empty(&wb->b_dirty) ||
!list_empty(&wb->b_io) ||
!list_empty(&wb->b_more_io);
}
static inline void __add_bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item, s64 amount)
{
__percpu_counter_add(&bdi->bdi_stat[item], amount, BDI_STAT_BATCH);
}
static inline void __inc_bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
__add_bdi_stat(bdi, item, 1);
}
static inline void inc_bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
unsigned long flags;
local_irq_save(flags);
__inc_bdi_stat(bdi, item);
local_irq_restore(flags);
}
static inline void __dec_bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
__add_bdi_stat(bdi, item, -1);
}
static inline void dec_bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
unsigned long flags;
local_irq_save(flags);
__dec_bdi_stat(bdi, item);
local_irq_restore(flags);
}
static inline s64 bdi_stat(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
return percpu_counter_read_positive(&bdi->bdi_stat[item]);
}
static inline s64 __bdi_stat_sum(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
return percpu_counter_sum_positive(&bdi->bdi_stat[item]);
}
static inline s64 bdi_stat_sum(struct backing_dev_info *bdi,
enum bdi_stat_item item)
{
s64 sum;
unsigned long flags;
local_irq_save(flags);
sum = __bdi_stat_sum(bdi, item);
local_irq_restore(flags);
return sum;
}
extern void bdi_writeout_inc(struct backing_dev_info *bdi);
/*
* maximal error of a stat counter.
*/
static inline unsigned long bdi_stat_error(struct backing_dev_info *bdi)
{
#ifdef CONFIG_SMP
return nr_cpu_ids * BDI_STAT_BATCH;
#else
return 1;
#endif
}
int bdi_set_min_ratio(struct backing_dev_info *bdi, unsigned int min_ratio);
int bdi_set_max_ratio(struct backing_dev_info *bdi, unsigned int max_ratio);
/*
* Flags in backing_dev_info::capability
*
* The first three flags control whether dirty pages will contribute to the
* VM's accounting and whether writepages() should be called for dirty pages
* (something that would not, for example, be appropriate for ramfs)
*
* WARNING: these flags are closely related and should not normally be
* used separately. The BDI_CAP_NO_ACCT_AND_WRITEBACK combines these
* three flags into a single convenience macro.
*
* BDI_CAP_NO_ACCT_DIRTY: Dirty pages shouldn't contribute to accounting
* BDI_CAP_NO_WRITEBACK: Don't write pages back
* BDI_CAP_NO_ACCT_WB: Don't automatically account writeback pages
*
* These flags let !MMU mmap() govern direct device mapping vs immediate
* copying more easily for MAP_PRIVATE, especially for ROM filesystems.
*
* BDI_CAP_MAP_COPY: Copy can be mapped (MAP_PRIVATE)
* BDI_CAP_MAP_DIRECT: Can be mapped directly (MAP_SHARED)
* BDI_CAP_READ_MAP: Can be mapped for reading
* BDI_CAP_WRITE_MAP: Can be mapped for writing
* BDI_CAP_EXEC_MAP: Can be mapped for execution
*
* BDI_CAP_SWAP_BACKED: Count shmem/tmpfs objects as swap-backed.
*
* BDI_CAP_STRICTLIMIT: Keep number of dirty pages below bdi threshold.
*/
#define BDI_CAP_NO_ACCT_DIRTY 0x00000001
#define BDI_CAP_NO_WRITEBACK 0x00000002
#define BDI_CAP_MAP_COPY 0x00000004
#define BDI_CAP_MAP_DIRECT 0x00000008
#define BDI_CAP_READ_MAP 0x00000010
#define BDI_CAP_WRITE_MAP 0x00000020
#define BDI_CAP_EXEC_MAP 0x00000040
#define BDI_CAP_NO_ACCT_WB 0x00000080
#define BDI_CAP_SWAP_BACKED 0x00000100
#define BDI_CAP_STABLE_WRITES 0x00000200
#define BDI_CAP_STRICTLIMIT 0x00000400
#define BDI_CAP_VMFLAGS \
(BDI_CAP_READ_MAP | BDI_CAP_WRITE_MAP | BDI_CAP_EXEC_MAP)
#define BDI_CAP_NO_ACCT_AND_WRITEBACK \
(BDI_CAP_NO_WRITEBACK | BDI_CAP_NO_ACCT_DIRTY | BDI_CAP_NO_ACCT_WB)
#if defined(VM_MAYREAD) && \
(BDI_CAP_READ_MAP != VM_MAYREAD || \
BDI_CAP_WRITE_MAP != VM_MAYWRITE || \
BDI_CAP_EXEC_MAP != VM_MAYEXEC)
#error please change backing_dev_info::capabilities flags
#endif
extern struct backing_dev_info default_backing_dev_info;
extern struct backing_dev_info noop_backing_dev_info;
int writeback_in_progress(struct backing_dev_info *bdi);
static inline int bdi_congested(struct backing_dev_info *bdi, int bdi_bits)
{
if (bdi->congested_fn)
return bdi->congested_fn(bdi->congested_data, bdi_bits);
return (bdi->state & bdi_bits);
}
static inline int bdi_read_congested(struct backing_dev_info *bdi)
{
return bdi_congested(bdi, 1 << BDI_sync_congested);
}
static inline int bdi_write_congested(struct backing_dev_info *bdi)
{
return bdi_congested(bdi, 1 << BDI_async_congested);
}
static inline int bdi_rw_congested(struct backing_dev_info *bdi)
{
return bdi_congested(bdi, (1 << BDI_sync_congested) |
(1 << BDI_async_congested));
}
enum {
BLK_RW_ASYNC = 0,
BLK_RW_SYNC = 1,
};
void clear_bdi_congested(struct backing_dev_info *bdi, int sync);
void set_bdi_congested(struct backing_dev_info *bdi, int sync);
long congestion_wait(int sync, long timeout);
long wait_iff_congested(struct zone *zone, int sync, long timeout);
int pdflush_proc_obsolete(struct ctl_table *table, int write,
void __user *buffer, size_t *lenp, loff_t *ppos);
static inline bool bdi_cap_stable_pages_required(struct backing_dev_info *bdi)
{
return bdi->capabilities & BDI_CAP_STABLE_WRITES;
}
static inline bool bdi_cap_writeback_dirty(struct backing_dev_info *bdi)
{
return !(bdi->capabilities & BDI_CAP_NO_WRITEBACK);
}
static inline bool bdi_cap_account_dirty(struct backing_dev_info *bdi)
{
return !(bdi->capabilities & BDI_CAP_NO_ACCT_DIRTY);
}
static inline bool bdi_cap_account_writeback(struct backing_dev_info *bdi)
{
/* Paranoia: BDI_CAP_NO_WRITEBACK implies BDI_CAP_NO_ACCT_WB */
return !(bdi->capabilities & (BDI_CAP_NO_ACCT_WB |
BDI_CAP_NO_WRITEBACK));
}
static inline bool bdi_cap_swap_backed(struct backing_dev_info *bdi)
{
return bdi->capabilities & BDI_CAP_SWAP_BACKED;
}
static inline bool mapping_cap_writeback_dirty(struct address_space *mapping)
{
return bdi_cap_writeback_dirty(mapping->backing_dev_info);
}
static inline bool mapping_cap_account_dirty(struct address_space *mapping)
{
return bdi_cap_account_dirty(mapping->backing_dev_info);
}
static inline bool mapping_cap_swap_backed(struct address_space *mapping)
{
return bdi_cap_swap_backed(mapping->backing_dev_info);
}
static inline int bdi_sched_wait(void *word)
{
schedule();
return 0;
}
#endif /* _LINUX_BACKING_DEV_H */

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/*
* Backlight Lowlevel Control Abstraction
*
* Copyright (C) 2003,2004 Hewlett-Packard Company
*
*/
#ifndef _LINUX_BACKLIGHT_H
#define _LINUX_BACKLIGHT_H
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
/* Notes on locking:
*
* backlight_device->ops_lock is an internal backlight lock protecting the
* ops pointer and no code outside the core should need to touch it.
*
* Access to update_status() is serialised by the update_lock mutex since
* most drivers seem to need this and historically get it wrong.
*
* Most drivers don't need locking on their get_brightness() method.
* If yours does, you need to implement it in the driver. You can use the
* update_lock mutex if appropriate.
*
* Any other use of the locks below is probably wrong.
*/
enum backlight_update_reason {
BACKLIGHT_UPDATE_HOTKEY,
BACKLIGHT_UPDATE_SYSFS,
};
enum backlight_type {
BACKLIGHT_RAW = 1,
BACKLIGHT_PLATFORM,
BACKLIGHT_FIRMWARE,
BACKLIGHT_TYPE_MAX,
};
enum backlight_notification {
BACKLIGHT_REGISTERED,
BACKLIGHT_UNREGISTERED,
};
struct backlight_device;
struct fb_info;
struct backlight_ops {
unsigned int options;
#define BL_CORE_SUSPENDRESUME (1 << 0)
/* Notify the backlight driver some property has changed */
int (*update_status)(struct backlight_device *);
/* Return the current backlight brightness (accounting for power,
fb_blank etc.) */
int (*get_brightness)(struct backlight_device *);
/* Check if given framebuffer device is the one bound to this backlight;
return 0 if not, !=0 if it is. If NULL, backlight always matches the fb. */
int (*check_fb)(struct backlight_device *, struct fb_info *);
};
/* This structure defines all the properties of a backlight */
struct backlight_properties {
/* Current User requested brightness (0 - max_brightness) */
int brightness;
/* Maximal value for brightness (read-only) */
int max_brightness;
/* Current FB Power mode (0: full on, 1..3: power saving
modes; 4: full off), see FB_BLANK_XXX */
int power;
/* FB Blanking active? (values as for power) */
/* Due to be removed, please use (state & BL_CORE_FBBLANK) */
int fb_blank;
/* Backlight type */
enum backlight_type type;
/* Flags used to signal drivers of state changes */
/* Upper 4 bits are reserved for driver internal use */
unsigned int state;
#define BL_CORE_SUSPENDED (1 << 0) /* backlight is suspended */
#define BL_CORE_FBBLANK (1 << 1) /* backlight is under an fb blank event */
#define BL_CORE_DRIVER4 (1 << 28) /* reserved for driver specific use */
#define BL_CORE_DRIVER3 (1 << 29) /* reserved for driver specific use */
#define BL_CORE_DRIVER2 (1 << 30) /* reserved for driver specific use */
#define BL_CORE_DRIVER1 (1 << 31) /* reserved for driver specific use */
};
struct backlight_device {
/* Backlight properties */
struct backlight_properties props;
/* Serialise access to update_status method */
struct mutex update_lock;
/* This protects the 'ops' field. If 'ops' is NULL, the driver that
registered this device has been unloaded, and if class_get_devdata()
points to something in the body of that driver, it is also invalid. */
struct mutex ops_lock;
const struct backlight_ops *ops;
/* The framebuffer notifier block */
struct notifier_block fb_notif;
/* list entry of all registered backlight devices */
struct list_head entry;
struct device dev;
/* Multiple framebuffers may share one backlight device */
bool fb_bl_on[FB_MAX];
int use_count;
};
static inline void backlight_update_status(struct backlight_device *bd)
{
mutex_lock(&bd->update_lock);
if (bd->ops && bd->ops->update_status)
bd->ops->update_status(bd);
mutex_unlock(&bd->update_lock);
}
extern struct backlight_device *backlight_device_register(const char *name,
struct device *dev, void *devdata, const struct backlight_ops *ops,
const struct backlight_properties *props);
extern struct backlight_device *devm_backlight_device_register(
struct device *dev, const char *name, struct device *parent,
void *devdata, const struct backlight_ops *ops,
const struct backlight_properties *props);
extern void backlight_device_unregister(struct backlight_device *bd);
extern void devm_backlight_device_unregister(struct device *dev,
struct backlight_device *bd);
extern void backlight_force_update(struct backlight_device *bd,
enum backlight_update_reason reason);
extern bool backlight_device_registered(enum backlight_type type);
extern int backlight_register_notifier(struct notifier_block *nb);
extern int backlight_unregister_notifier(struct notifier_block *nb);
#define to_backlight_device(obj) container_of(obj, struct backlight_device, dev)
static inline void * bl_get_data(struct backlight_device *bl_dev)
{
return dev_get_drvdata(&bl_dev->dev);
}
struct generic_bl_info {
const char *name;
int max_intensity;
int default_intensity;
int limit_mask;
void (*set_bl_intensity)(int intensity);
void (*kick_battery)(void);
};
#ifdef CONFIG_OF
struct backlight_device *of_find_backlight_by_node(struct device_node *node);
#else
static inline struct backlight_device *
of_find_backlight_by_node(struct device_node *node)
{
return NULL;
}
#endif
#endif

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/*
* include/linux/balloon_compaction.h
*
* Common interface definitions for making balloon pages movable by compaction.
*
* Despite being perfectly possible to perform ballooned pages migration, they
* make a special corner case to compaction scans because balloon pages are not
* enlisted at any LRU list like the other pages we do compact / migrate.
*
* As the page isolation scanning step a compaction thread does is a lockless
* procedure (from a page standpoint), it might bring some racy situations while
* performing balloon page compaction. In order to sort out these racy scenarios
* and safely perform balloon's page compaction and migration we must, always,
* ensure following these three simple rules:
*
* i. when updating a balloon's page ->mapping element, strictly do it under
* the following lock order, independently of the far superior
* locking scheme (lru_lock, balloon_lock):
* +-page_lock(page);
* +--spin_lock_irq(&b_dev_info->pages_lock);
* ... page->mapping updates here ...
*
* ii. before isolating or dequeueing a balloon page from the balloon device
* pages list, the page reference counter must be raised by one and the
* extra refcount must be dropped when the page is enqueued back into
* the balloon device page list, thus a balloon page keeps its reference
* counter raised only while it is under our special handling;
*
* iii. after the lockless scan step have selected a potential balloon page for
* isolation, re-test the PageBalloon mark and the PagePrivate flag
* under the proper page lock, to ensure isolating a valid balloon page
* (not yet isolated, nor under release procedure)
*
* iv. isolation or dequeueing procedure must clear PagePrivate flag under
* page lock together with removing page from balloon device page list.
*
* The functions provided by this interface are placed to help on coping with
* the aforementioned balloon page corner case, as well as to ensure the simple
* set of exposed rules are satisfied while we are dealing with balloon pages
* compaction / migration.
*
* Copyright (C) 2012, Red Hat, Inc. Rafael Aquini <aquini@redhat.com>
*/
#ifndef _LINUX_BALLOON_COMPACTION_H
#define _LINUX_BALLOON_COMPACTION_H
#include <linux/pagemap.h>
#include <linux/page-flags.h>
#include <linux/migrate.h>
#include <linux/gfp.h>
#include <linux/err.h>
/*
* Balloon device information descriptor.
* This struct is used to allow the common balloon compaction interface
* procedures to find the proper balloon device holding memory pages they'll
* have to cope for page compaction / migration, as well as it serves the
* balloon driver as a page book-keeper for its registered balloon devices.
*/
struct balloon_dev_info {
unsigned long isolated_pages; /* # of isolated pages for migration */
spinlock_t pages_lock; /* Protection to pages list */
struct list_head pages; /* Pages enqueued & handled to Host */
int (*migratepage)(struct balloon_dev_info *, struct page *newpage,
struct page *page, enum migrate_mode mode);
};
extern struct page *balloon_page_enqueue(struct balloon_dev_info *b_dev_info);
extern struct page *balloon_page_dequeue(struct balloon_dev_info *b_dev_info);
static inline void balloon_devinfo_init(struct balloon_dev_info *balloon)
{
balloon->isolated_pages = 0;
spin_lock_init(&balloon->pages_lock);
INIT_LIST_HEAD(&balloon->pages);
balloon->migratepage = NULL;
}
#ifdef CONFIG_BALLOON_COMPACTION
extern bool balloon_page_isolate(struct page *page);
extern void balloon_page_putback(struct page *page);
extern int balloon_page_migrate(struct page *newpage,
struct page *page, enum migrate_mode mode);
/*
* __is_movable_balloon_page - helper to perform @page PageBalloon tests
*/
static inline bool __is_movable_balloon_page(struct page *page)
{
return PageBalloon(page);
}
/*
* balloon_page_movable - test PageBalloon to identify balloon pages
* and PagePrivate to check that the page is not
* isolated and can be moved by compaction/migration.
*
* As we might return false positives in the case of a balloon page being just
* released under us, this need to be re-tested later, under the page lock.
*/
static inline bool balloon_page_movable(struct page *page)
{
return PageBalloon(page) && PagePrivate(page);
}
/*
* isolated_balloon_page - identify an isolated balloon page on private
* compaction/migration page lists.
*/
static inline bool isolated_balloon_page(struct page *page)
{
return PageBalloon(page);
}
/*
* balloon_page_insert - insert a page into the balloon's page list and make
* the page->private assignment accordingly.
* @balloon : pointer to balloon device
* @page : page to be assigned as a 'balloon page'
*
* Caller must ensure the page is locked and the spin_lock protecting balloon
* pages list is held before inserting a page into the balloon device.
*/
static inline void balloon_page_insert(struct balloon_dev_info *balloon,
struct page *page)
{
__SetPageBalloon(page);
SetPagePrivate(page);
set_page_private(page, (unsigned long)balloon);
list_add(&page->lru, &balloon->pages);
}
/*
* balloon_page_delete - delete a page from balloon's page list and clear
* the page->private assignement accordingly.
* @page : page to be released from balloon's page list
*
* Caller must ensure the page is locked and the spin_lock protecting balloon
* pages list is held before deleting a page from the balloon device.
*/
static inline void balloon_page_delete(struct page *page)
{
__ClearPageBalloon(page);
set_page_private(page, 0);
if (PagePrivate(page)) {
ClearPagePrivate(page);
list_del(&page->lru);
}
}
/*
* balloon_page_device - get the b_dev_info descriptor for the balloon device
* that enqueues the given page.
*/
static inline struct balloon_dev_info *balloon_page_device(struct page *page)
{
return (struct balloon_dev_info *)page_private(page);
}
static inline gfp_t balloon_mapping_gfp_mask(void)
{
return GFP_HIGHUSER_MOVABLE;
}
#else /* !CONFIG_BALLOON_COMPACTION */
static inline void balloon_page_insert(struct balloon_dev_info *balloon,
struct page *page)
{
__SetPageBalloon(page);
list_add(&page->lru, &balloon->pages);
}
static inline void balloon_page_delete(struct page *page)
{
__ClearPageBalloon(page);
list_del(&page->lru);
}
static inline bool __is_movable_balloon_page(struct page *page)
{
return false;
}
static inline bool balloon_page_movable(struct page *page)
{
return false;
}
static inline bool isolated_balloon_page(struct page *page)
{
return false;
}
static inline bool balloon_page_isolate(struct page *page)
{
return false;
}
static inline void balloon_page_putback(struct page *page)
{
return;
}
static inline int balloon_page_migrate(struct page *newpage,
struct page *page, enum migrate_mode mode)
{
return 0;
}
static inline gfp_t balloon_mapping_gfp_mask(void)
{
return GFP_HIGHUSER;
}
#endif /* CONFIG_BALLOON_COMPACTION */
#endif /* _LINUX_BALLOON_COMPACTION_H */

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/*
* Basic memory-mapped GPIO controllers.
*
* Copyright 2008 MontaVista Software, Inc.
* Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __BASIC_MMIO_GPIO_H
#define __BASIC_MMIO_GPIO_H
#include <linux/gpio.h>
#include <linux/types.h>
#include <linux/compiler.h>
#include <linux/spinlock_types.h>
struct bgpio_pdata {
const char *label;
int base;
int ngpio;
};
struct device;
struct bgpio_chip {
struct gpio_chip gc;
unsigned long (*read_reg)(void __iomem *reg);
void (*write_reg)(void __iomem *reg, unsigned long data);
void __iomem *reg_dat;
void __iomem *reg_set;
void __iomem *reg_clr;
void __iomem *reg_dir;
/* Number of bits (GPIOs): <register width> * 8. */
int bits;
/*
* Some GPIO controllers work with the big-endian bits notation,
* e.g. in a 8-bits register, GPIO7 is the least significant bit.
*/
unsigned long (*pin2mask)(struct bgpio_chip *bgc, unsigned int pin);
/*
* Used to lock bgpio_chip->data. Also, this is needed to keep
* shadowed and real data registers writes together.
*/
spinlock_t lock;
/* Shadowed data register to clear/set bits safely. */
unsigned long data;
/* Shadowed direction registers to clear/set direction safely. */
unsigned long dir;
};
static inline struct bgpio_chip *to_bgpio_chip(struct gpio_chip *gc)
{
return container_of(gc, struct bgpio_chip, gc);
}
int bgpio_remove(struct bgpio_chip *bgc);
int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
unsigned long sz, void __iomem *dat, void __iomem *set,
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
unsigned long flags);
#define BGPIOF_BIG_ENDIAN BIT(0)
#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
#endif /* __BASIC_MMIO_GPIO_H */

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/*
* bq24260_charger.h
* Samsung BQ24260 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __BQ24260_CHARGER_H
#define __BQ24260_CHARGER_H __FILE__
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define SEC_CHARGER_I2C_SLAVEADDR (0x6B)
/* BQ24260 Registers. */
#define BQ24260_STATUS 0x00
#define BQ24260_CONTROL 0x01
#define BQ24260_VOLTAGE 0x02
#define BQ24260_VENDOR 0x03
#define BQ24260_CURRENT 0x04
#define BQ24260_SPECIAL 0x05
#define BQ24260_SAFETY 0x06
#endif /* __BQ24260_CHARGER_H */

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/*
* p9015_charger.h
* Samsung P9015 Charger Header
*
* Copyright (C) 2014 Samsung Electronics, Inc.
* Yeongmi Ha <yeongmi86.ha@samsung.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __BQ51221_CHARGER_H
#define __BQ51221_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/battery/sec_charging_common.h>
#include <linux/wakelock.h>
/* REGISTER MAPS */
#define BQ51221_REG_CURRENT_REGISTER 0X01
#define BQ51221_REG_CURRENT_REGISTER2 0X02
#define BQ51221_REG_MAILBOX 0XE0
#define BQ51221_REG_POD_RAM 0XE1
#define BQ51221_REG_USER_HEADER 0XE2
#define BQ51221_REG_VRECT_STATUS 0XE3
#define BQ51221_REG_VOUT_STATUS 0XE4
#define BQ51221_REG_PWR_BYTE_STATUS 0XE8
#define BQ51221_REG_INDICATOR 0XEF
#define BQ51221_REG_PROP_PACKET_PAYLOAD 0XF1
/* WPC HEADER */
#define BQ51221_EPT_HEADER_EPT 0x02
#define BQ51221_EPT_HEADER_CS100 0x05
/* END POWER TRANSFER CODES IN WPC */
#define BQ51221_EPT_CODE_UNKOWN 0x00
#define BQ51221_EPT_CODE_CHARGE_COMPLETE 0x01
#define BQ51221_EPT_CODE_INTERNAL_FAULT 0x02
#define BQ51221_EPT_CODE_OVER_TEMPERATURE 0x03
#define BQ51221_EPT_CODE_OVER_VOLTAGE 0x04
#define BQ51221_EPT_CODE_OVER_CURRENT 0x05
#define BQ51221_EPT_CODE_BATTERY_FAILURE 0x06
#define BQ51221_EPT_CODE_RECONFIGURE 0x07
#define BQ51221_EPT_CODE_NO_RESPONSE 0x08
#define BQ51221_POWER_MODE_MASK (0x1 << 0)
#define BQ51221_SEND_USER_PKT_DONE_MASK (0x1 << 7)
#define BQ51221_SEND_USER_PKT_ERR_MASK (0x3 << 5)
#define BQ51221_SEND_ALIGN_MASK (0x1 << 3)
#define BQ51221_SEND_EPT_CC_MASK (0x1 << 0)
#define BQ51221_SEND_EOC_MASK (0x1 << 0)
#define BQ51221_CS100_VALUE 0x64
#define BQ51221_IOREG_100_VALUE 0x07
#define BQ51221_IOREG_90_VALUE 0x06
#define BQ51221_IOREG_60_VALUE 0x05
#define BQ51221_IOREG_50_VALUE 0x04
#define BQ51221_IOREG_40_VALUE 0x03
#define BQ51221_IOREG_30_VALUE 0x02
#define BQ51221_IOREG_20_VALUE 0x01
#define BQ51221_IOREG_10_VALUE 0x00
#define BQ51221_PTK_ERR_NO_ERR 0x00
#define BQ51221_PTK_ERR_ERR 0x01
#define BQ51221_PTK_ERR_ILLEGAL_HD 0x02
#define BQ51221_PTK_ERR_NO_DEF 0x03
enum {
END_POWER_TRANSFER_CODE_UNKOWN = 0,
END_POWER_TRANSFER_CODE_CHARGECOMPLETE,
END_POWER_TRANSFER_CODE_INTERNAL_FAULT,
END_POWER_TRANSFER_CODE_OVER_TEMPERATURE,
END_POWER_TRANSFER_CODE_OVER_VOLTAGE,
END_POWER_TRANSFER_CODE_OVER_CURRENT,
END_POWER_TRANSFER_CODE_BATTERY_FAILURE,
END_POWER_TRANSFER_CODE_RECONFIGURE,
END_POWER_TRANSFER_CODE_NO_RESPONSE,
};
struct bq51221_charger_platform_data {
int irq_gpio;
int irq_base;
int tsb_gpio;
int cs100_status;
int pad_mode;
int wireless_cc_cv;
int siop_level;
bool default_voreg;
char *wireless_charger_name;
};
#define bq51221_charger_platform_data_t \
struct bq51221_charger_platform_data
struct bq51221_charger_data {
struct i2c_client *client;
struct device *dev;
bq51221_charger_platform_data_t *pdata;
struct mutex io_lock;
struct power_supply psy_chg;
struct wake_lock wpc_wake_lock;
struct workqueue_struct *wqueue;
struct work_struct chgin_work;
struct delayed_work wpc_work;
struct delayed_work isr_work;
int chg_irq;
int irq_base;
int irq_gpio;
int wpc_state;
};
enum {
BQ51221_EVENT_IRQ = 0,
BQ51221_IRQS_NR,
};
enum {
BQ51221_PAD_MODE_NONE = 0,
BQ51221_PAD_MODE_WPC,
BQ51221_PAD_MODE_PMA,
};
#endif /* __BQ51221_CHARGER_H */

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/*
* MAX77693_charger.h
* Samsung MAX77693 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77693_CHARGER_H
#define __MAX77693_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/mfd/max77693.h>
#include <linux/mfd/max77693-private.h>
#include <linux/regulator/machine.h>
#define ENABLE 1
#define DISABLE 0
/* macro */
#define MAX(x, y) ((x) > (y) ? (x) : (y))
#define MIN(x, y) ((x) < (y) ? (x) : (y))
#define ABS(x) ((x) < 0 ? (-1 * (x)) : (x))
/*
* Use for battery
*/
#define OFF_CURR 0 /* charger off current */
#define KEEP_CURR -1 /* keep previous current */
/* MAX77693_CHG_REG_CHG_INT */
#define MAX77693_BYP_I (1 << 0)
#define MAX77693_BATP_I (1 << 2)
#define MAX77693_BAT_I (1 << 3)
#define MAX77693_CHG_I (1 << 4)
#define MAX77693_WCIN_I (1 << 5)
#define MAX77693_CHGIN_I (1 << 6)
/* MAX77693_CHG_REG_CHG_INT_MASK */
#define MAX77693_BYP_IM (1 << 0)
#define MAX77693_THM_IM (1 << 2)
#define MAX77693_BAT_IM (1 << 3)
#define MAX77693_CHG_IM (1 << 4)
#define MAX77693_WCIN_IM (1 << 5)
#define MAX77693_CHGIN_IM (1 << 6)
/* MAX77693_CHG_REG_CHG_INT_OK */
#define MAX77693_BYP_OK 0x01
#define MAX77693_BYP_OK_SHIFT 0
#define MAX77693_BATP_OK 0x04
#define MAX77693_BATP_OK_SHIFT 2
#define MAX77693_BAT_OK 0x08
#define MAX77693_BAT_OK_SHIFT 3
#define MAX77693_CHG_OK 0x10
#define MAX77693_CHG_OK_SHIFT 4
#define MAX77693_WCIN_OK 0x20
#define MAX77693_WCIN_OK_SHIFT 5
#define MAX77693_CHGIN_OK 0x40
#define MAX77693_CHGIN_OK_SHIFT 6
#define MAX77693_DETBAT 0x04
#define MAX77693_DETBAT_SHIFT 2
/* MAX77693_CHG_REG_CHG_DTLS_00 */
#define MAX77693_BATP_DTLS 0x01
#define MAX77693_BATP_DTLS_SHIFT 0
#define MAX77693_WCIN_DTLS 0x18
#define MAX77693_WCIN_DTLS_SHIFT 3
#define MAX77693_CHGIN_DTLS 0x60
#define MAX77693_CHGIN_DTLS_SHIFT 5
/* MAX77693_CHG_REG_CHG_DTLS_01 */
#define MAX77693_CHG_DTLS 0x0F
#define MAX77693_CHG_DTLS_SHIFT 0
#define MAX77693_BAT_DTLS 0x70
#define MAX77693_BAT_DTLS_SHIFT 4
/* MAX77693_CHG_REG_CHG_DTLS_02 */
#define MAX77693_BYP_DTLS 0x0F
#define MAX77693_BYP_DTLS_SHIFT 0
#define MAX77693_BYP_DTLS0 0x1
#define MAX77693_BYP_DTLS1 0x2
#define MAX77693_BYP_DTLS2 0x4
#define MAX77693_BYP_DTLS3 0x8
/* MAX77693_CHG_REG_CHG_CNFG_00 */
#define MAX77693_MODE_DEFAULT 0x04
#define MAX77693_MODE_CHGR 0x01
#define MAX77693_MODE_OTG 0x02
#define MAX77693_MODE_BUCK 0x04
/* MAX77693_CHG_REG_CHG_CNFG_02 */
#define MAX77693_CHG_CC 0x3F
/* MAX77693_CHG_REG_CHG_CNFG_03 */
#define MAX77693_CHG_TO_ITH 0x07
/* MAX77693_CHG_REG_CHG_CNFG_04 */
#define MAX77693_CHG_MINVSYS_MASK 0xE0
#define MAX77693_CHG_MINVSYS_SHIFT 5
#define MAX77693_CHG_PRM_MASK 0x1F
#define MAX77693_CHG_PRM_SHIFT 0
/* MAX77693_CHG_REG_CHG_CNFG_09 */
#define MAX77693_CHG_CHGIN_LIM 0x7F
/* MAX77693_CHG_REG_CHG_CNFG_12 */
#define MAX77693_CHG_WCINSEL 0x40
/* MAX77693_MUIC_REG_CDETCTRL1 */
#define MAX77693_CHGTYPMAN 0x02
#define MAX77693_CHGTYPMAN_SHIFT 1
/* MAX77693_MUIC_REG_STATUS2 */
#define MAX77693_VBVOLT 0x40
#define MAX77693_VBVOLT_SHIFT 6
#define MAX77693_CHGDETRUN 0x08
#define MAX77693_CHGDETRUN_SHIFT 3
#define MAX77693_CHGTYPE 0x07
#define MAX77693_CHGTYPE_SHIFT 0
/* irq */
#define IRQ_DEBOUNCE_TIME 20 /* msec */
/* charger type detection */
#define DET_ERR_RETRY 5
#define DET_ERR_DELAY 200
/* soft charging */
#define SOFT_CHG_START_CURR 100 /* mA */
#define SOFT_CHG_START_DUR 100 /* ms */
#define SOFT_CHG_CURR_STEP 100 /* mA */
#define SOFT_CHG_STEP_DUR 20 /* ms */
#define DEFAULT_AC_CURRENT 1600 /* mA */
#define DEFAULT_USB_CURRENT 500 /* mA */
enum {
POWER_SUPPLY_VBUS_UNKNOWN = 0,
POWER_SUPPLY_VBUS_UVLO,
POWER_SUPPLY_VBUS_WEAK,
POWER_SUPPLY_VBUS_OVLO,
POWER_SUPPLY_VBUS_GOOD,
};
extern sec_battery_platform_data_t sec_battery_pdata;
#endif

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/*
* max77804_charger.h
* Samsung max77804 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77804_CHARGER_H
#define __MAX77804_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/mfd/max77804.h>
#include <linux/mfd/max77804-private.h>
#include <linux/regulator/machine.h>
#if defined(CONFIG_V1A) || defined(CONFIG_N1A)
#define max77888_charger
#else
#undef max77888_charger
#endif
#define ENABLE 1
#define DISABLE 0
/* macro */
#define MAX(x, y) ((x) > (y) ? (x) : (y))
#define MIN(x, y) ((x) < (y) ? (x) : (y))
#define ABS(x) ((x) < 0 ? (-1 * (x)) : (x))
/*
* Use for battery
*/
#define OFF_CURR 0 /* charger off current */
#define KEEP_CURR -1 /* keep previous current */
/* MAX77803 CHG_CNFG_04 register */
#define CHG_CNFG_04_CHG_CV_PRM_SHIFT 0
#define CHG_CNFG_04_CHG_CV_PRM_MASK (0x1f << CHG_CNFG_04_CHG_CV_PRM_SHIFT)
/* MAX77803 CHG_CNFG_12 register */
#define CHG_CNFG_12_CHGINSEL_SHIFT 5
#define CHG_CNFG_12_CHGINSEL_MASK (0x1 << CHG_CNFG_12_CHGINSEL_SHIFT)
/* MAX77804_CHG_REG_CHG_INT */
#define MAX77804_BYP_I (1 << 0)
#define MAX77804_BATP_I (1 << 2)
#define MAX77804_BAT_I (1 << 3)
#define MAX77804_CHG_I (1 << 4)
#define MAX77804_WCIN_I (1 << 5)
#define MAX77804_CHGIN_I (1 << 6)
/* MAX77804_CHG_REG_CHG_INT_MASK */
#define MAX77804_BYP_IM (1 << 0)
#define MAX77804_THM_IM (1 << 2)
#define MAX77804_BAT_IM (1 << 3)
#define MAX77804_CHG_IM (1 << 4)
#define MAX77804_WCIN_IM (1 << 5)
#define MAX77804_CHGIN_IM (1 << 6)
/* MAX77804_CHG_REG_CHG_INT_OK */
#define MAX77804_BYP_OK 0x01
#define MAX77804_BYP_OK_SHIFT 0
#define MAX77804_BATP_OK 0x04
#define MAX77804_BATP_OK_SHIFT 2
#define MAX77804_BAT_OK 0x08
#define MAX77804_BAT_OK_SHIFT 3
#define MAX77804_CHG_OK 0x10
#define MAX77804_CHG_OK_SHIFT 4
#define MAX77804_WCIN_OK 0x20
#define MAX77804_WCIN_OK_SHIFT 5
#define MAX77804_CHGIN_OK 0x40
#define MAX77804_CHGIN_OK_SHIFT 6
#define MAX77804_DETBAT 0x04
#define MAX77804_DETBAT_SHIFT 2
/* MAX77804_CHG_REG_CHG_DTLS_00 */
#define MAX77804_BATP_DTLS 0x01
#define MAX77804_BATP_DTLS_SHIFT 0
#define MAX77804_WCIN_DTLS 0x18
#define MAX77804_WCIN_DTLS_SHIFT 3
#define MAX77804_CHGIN_DTLS 0x60
#define MAX77804_CHGIN_DTLS_SHIFT 5
/* MAX77804_CHG_REG_CHG_DTLS_01 */
#define MAX77804_CHG_DTLS 0x0F
#define MAX77804_CHG_DTLS_SHIFT 0
#define MAX77804_BAT_DTLS 0x70
#define MAX77804_BAT_DTLS_SHIFT 4
/* MAX77804_CHG_REG_CHG_DTLS_02 */
#define MAX77804_BYP_DTLS 0x0F
#define MAX77804_BYP_DTLS_SHIFT 0
#define MAX77804_BYP_DTLS0 0x1
#define MAX77804_BYP_DTLS1 0x2
#define MAX77804_BYP_DTLS2 0x4
#define MAX77804_BYP_DTLS3 0x8
/* MAX77804_CHG_REG_CHG_CNFG_00 */
#define MAX77804_MODE_DEFAULT 0x04
#define MAX77804_MODE_CHGR 0x01
#define MAX77804_MODE_OTG 0x02
#define MAX77804_MODE_BUCK 0x04
#define MAX77804_MODE_BOOST 0x08
/* MAX77804_CHG_REG_CHG_CNFG_02 */
#define MAX77804_CHG_CC 0x3F
/* MAX77804_CHG_REG_CHG_CNFG_03 */
#define MAX77804_CHG_TO_ITH 0x07
/* MAX77804_CHG_REG_CHG_CNFG_04 */
#define MAX77804_CHG_MINVSYS_MASK 0xE0
#define MAX77804_CHG_MINVSYS_SHIFT 5
#define MAX77804_CHG_PRM_MASK 0x1F
#define MAX77804_CHG_PRM_SHIFT 0
/* MAX77804_CHG_REG_CHG_CNFG_09 */
#define MAX77804_CHG_CHGIN_LIM 0x7F
/* MAX77804_CHG_REG_CHG_CNFG_12 */
#define MAX77804_CHG_WCINSEL 0x40
/* MAX77804_MUIC_REG_CDETCTRL1 */
#define MAX77804_CHGTYPMAN 0x02
#define MAX77804_CHGTYPMAN_SHIFT 1
/* MAX77804_MUIC_REG_STATUS2 */
#define MAX77804_VBVOLT 0x40
#define MAX77804_VBVOLT_SHIFT 6
#define MAX77804_CHGDETRUN 0x08
#define MAX77804_CHGDETRUN_SHIFT 3
#define MAX77804_CHGTYPE 0x07
#define MAX77804_CHGTYPE_SHIFT 0
/* irq */
#define IRQ_DEBOUNCE_TIME 20 /* msec */
/* charger type detection */
#define DET_ERR_RETRY 5
#define DET_ERR_DELAY 200
/* soft charging */
#define SOFT_CHG_START_CURR 100 /* mA */
#define SOFT_CHG_START_DUR 100 /* ms */
#define SOFT_CHG_CURR_STEP 100 /* mA */
#define SOFT_CHG_STEP_DUR 20 /* ms */
#define DEFAULT_AC_CURRENT 1600 /* mA */
#define DEFAULT_USB_CURRENT 500 /* mA */
enum {
POWER_SUPPLY_VBUS_UNKNOWN = 0,
POWER_SUPPLY_VBUS_UVLO,
POWER_SUPPLY_VBUS_WEAK,
POWER_SUPPLY_VBUS_OVLO,
POWER_SUPPLY_VBUS_GOOD,
};
extern sec_battery_platform_data_t sec_battery_pdata;
#if defined(CONFIG_TARGET_LOCALE_KOR)
#define SEC_CHG_ATTR(_name) \
{ \
.attr = {.name = #_name, .mode = 0664}, \
.show = sec_chg_show_attrs, \
.store = sec_chg_store_attrs, \
}
enum {
CHG_SIOP_INPUT_LIMIT = 0,
};
#endif
#endif

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/*
* max77823_charger.h
* Samsung MAX77823 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77823_CHARGER_H
#define __MAX77823_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/mfd/max77823.h>
#include <linux/mfd/max77823-private.h>
#include <linux/regulator/machine.h>
#define MAX77823_SAFEOUT2 0x80
/* MAX77823_CHG_REG_CHG_INT */
#define MAX77823_BYP_I (1 << 0)
#define MAX77823_BATP_I (1 << 2)
#define MAX77823_BAT_I (1 << 3)
#define MAX77823_CHG_I (1 << 4)
#define MAX77823_WCIN_I (1 << 5)
#define MAX77823_CHGIN_I (1 << 6)
/* MAX77823_CHG_REG_CHG_INT_MASK */
#define MAX77823_BYP_IM (1 << 0)
#define MAX77823_THM_IM (1 << 2)
#define MAX77823_BAT_IM (1 << 3)
#define MAX77823_CHG_IM (1 << 4)
#define MAX77823_WCIN_IM (1 << 5)
#define MAX77823_CHGIN_IM (1 << 6)
/* MAX77823_CHG_REG_CHG_INT_OK */
#define MAX77823_BYP_OK 0x01
#define MAX77823_BYP_OK_SHIFT 0
#define MAX77823_BATP_OK 0x04
#define MAX77823_BATP_OK_SHIFT 2
#define MAX77823_BAT_OK 0x08
#define MAX77823_BAT_OK_SHIFT 3
#define MAX77823_CHG_OK 0x10
#define MAX77823_CHG_OK_SHIFT 4
#define MAX77823_WCIN_OK 0x20
#define MAX77823_WCIN_OK_SHIFT 5
#define MAX77823_CHGIN_OK 0x40
#define MAX77823_CHGIN_OK_SHIFT 6
#define MAX77823_DETBAT 0x04
#define MAX77823_DETBAT_SHIFT 2
/* MAX77823_CHG_REG_CHG_DTLS_00 */
#define MAX77823_BATP_DTLS 0x01
#define MAX77823_BATP_DTLS_SHIFT 0
#define MAX77823_WCIN_DTLS 0x18
#define MAX77823_WCIN_DTLS_SHIFT 3
#define MAX77823_CHGIN_DTLS 0x60
#define MAX77823_CHGIN_DTLS_SHIFT 5
/* MAX77823_CHG_REG_CHG_DTLS_01 */
#define MAX77823_CHG_DTLS 0x0F
#define MAX77823_CHG_DTLS_SHIFT 0
#define MAX77823_BAT_DTLS 0x70
#define MAX77823_BAT_DTLS_SHIFT 4
/* MAX77823_CHG_REG_CHG_DTLS_02 */
#define MAX77823_BYP_DTLS 0x0F
#define MAX77823_BYP_DTLS_SHIFT 0
#define MAX77823_BYP_DTLS0 0x1
#define MAX77823_BYP_DTLS1 0x2
#define MAX77823_BYP_DTLS2 0x4
#define MAX77823_BYP_DTLS3 0x8
/* MAX77823_CHG_REG_CHG_CNFG_00 */
#define CHG_CNFG_00_MODE_SHIFT 0
#define CHG_CNFG_00_CHG_SHIFT 0
#define CHG_CNFG_00_OTG_SHIFT 1
#define CHG_CNFG_00_BUCK_SHIFT 2
#define CHG_CNFG_00_BOOST_SHIFT 3
#define CHG_CNFG_00_DIS_MUIC_CTRL_SHIFT 5
#define CHG_CNFG_00_MODE_MASK (0xf << CHG_CNFG_00_MODE_SHIFT)
#define CHG_CNFG_00_CHG_MASK (1 << CHG_CNFG_00_CHG_SHIFT)
#define CHG_CNFG_00_OTG_MASK (1 << CHG_CNFG_00_OTG_SHIFT)
#define CHG_CNFG_00_BUCK_MASK (1 << CHG_CNFG_00_BUCK_SHIFT)
#define CHG_CNFG_00_BOOST_MASK (1 << CHG_CNFG_00_BOOST_SHIFT)
#define CHG_CNFG_00_DIS_MUIC_CTRL_MASK (1 << CHG_CNFG_00_DIS_MUIC_CTRL_SHIFT)
#define MAX77823_MODE_DEFAULT 0x04
#define MAX77823_MODE_CHGR 0x01
#define MAX77823_MODE_OTG 0x02
#define MAX77823_MODE_BUCK 0x04
#define MAX77823_MODE_BOOST 0x08
/* MAX77823_CHG_REG_CHG_CNFG_02 */
#define MAX77823_CHG_CC 0x3F
/* MAX77823_CHG_REG_CHG_CNFG_03 */
#define MAX77823_CHG_TO_ITH 0x07
/* MAX77823_CHG_REG_CHG_CNFG_04 */
#define MAX77823_CHG_MINVSYS_MASK 0xE0
#define MAX77823_CHG_MINVSYS_SHIFT 5
#define MAX77823_CHG_PRM_MASK 0x1F
#define MAX77823_CHG_PRM_SHIFT 0
#define CHG_CNFG_04_CHG_CV_PRM_SHIFT 0
#define CHG_CNFG_04_CHG_CV_PRM_MASK (0x3F << CHG_CNFG_04_CHG_CV_PRM_SHIFT)
/* MAX77823_CHG_REG_CHG_CNFG_09 */
#define MAX77823_CHG_CHGIN_LIM 0x7F
/* MAX77823_CHG_REG_CHG_CNFG_12 */
#define MAX77823_CHG_WCINSEL 0x40
/* MAX77823_CHG_REG_CHG_DTLS_00 */
#define MAX77823_BATP_DTLS 0x01
#define MAX77823_BATP_DTLS_SHIFT 0
#define MAX77823_WCIN_DTLS 0x18
#define MAX77823_WCIN_DTLS_SHIFT 3
#define MAX77823_CHGIN_DTLS 0x60
#define MAX77823_CHGIN_DTLS_SHIFT 5
/* MAX77823_CHG_DETAILS_01 */
#define MAX77823_CHG_DTLS 0x0F
#define MAX77823_CHG_DTLS_SHIFT 0
#define MAX77823_BAT_DTLS 0x70
#define MAX77823_BAT_DTLS_SHIFT 4
#define SIOP_INPUT_LIMIT_CURRENT 1200
#define SIOP_CHARGING_LIMIT_CURRENT 1000
#define SLOW_CHARGING_CURRENT_STANDARD 400
struct max77823_charger_data {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *pmic_i2c;
struct mutex charger_mutex;
struct max77823_platform_data *max77823_pdata;
struct power_supply psy_chg;
struct workqueue_struct *wqueue;
struct work_struct chgin_work;
struct delayed_work isr_work;
struct delayed_work recovery_work; /* softreg recovery work */
struct delayed_work wpc_work; /* wpc detect work */
struct delayed_work chgin_init_work; /* chgin init work */
/* mutex */
struct mutex irq_lock;
struct mutex ops_lock;
/* wakelock */
struct wake_lock recovery_wake_lock;
struct wake_lock wpc_wake_lock;
struct wake_lock chgin_wake_lock;
unsigned int is_charging;
unsigned int charging_type;
unsigned int battery_state;
unsigned int battery_present;
unsigned int cable_type;
unsigned int charging_current_max;
unsigned int charging_current;
unsigned int input_current_limit;
unsigned int vbus_state;
int aicl_on;
int status;
int siop_level;
int uvlo_attach_flag;
int uvlo_attach_cable_type;
int irq_bypass;
int irq_batp;
int irq_battery;
int irq_chg;
int irq_wcin;
int irq_chgin;
/* software regulation */
bool soft_reg_state;
int soft_reg_current;
/* unsufficient power */
bool reg_loop_deted;
/* wireless charge, w(wpc), v(vbus) */
int wc_w_gpio;
int wc_w_irq;
int wc_w_state;
int wc_v_gpio;
int wc_v_irq;
int wc_v_state;
bool wc_pwr_det;
int soft_reg_recovery_cnt;
int pmic_ver;
int input_curr_limit_step;
int wpc_input_curr_limit_step;
int charging_curr_step;
sec_battery_platform_data_t *pdata;
};
extern void cp_usb_power_control(int enable);
#endif /* __MAX77823_CHARGER_H */

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/*
* max77833_charger.h
* Samsung MAX77833 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77833_CHARGER_H
#define __MAX77833_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/mfd/max77833.h>
#include <linux/mfd/max77833-private.h>
#include <linux/regulator/machine.h>
#include <linux/wakelock.h>
enum {
CHIP_ID = 0,
};
ssize_t max77833_chg_show_attrs(struct device *dev,
struct device_attribute *attr, char *buf);
ssize_t max77833_chg_store_attrs(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#define MAX77833_CHARGER_ATTR(_name) \
{ \
.attr = {.name = #_name, .mode = 0664}, \
.show = max77833_chg_show_attrs, \
.store = max77833_chg_store_attrs, \
}
extern sec_battery_platform_data_t sec_battery_pdata;
#define MAX77833_CHG_SAFEOUT2 0x80
/* MAX77833_CHG_REG_CHG_INT */
#define MAX77833_BYP_I (1 << 0)
#define MAX77833_BATP_I (1 << 2)
#define MAX77833_BAT_I (1 << 3)
#define MAX77833_CHG_I (1 << 4)
#define MAX77833_WCIN_I (1 << 5)
#define MAX77833_CHGIN_I (1 << 6)
#define MAX77833_AICL_I (1 << 7)
/* MAX77833_CHG_REG_CHG_INT_MASK */
#define MAX77833_BYP_IM (1 << 0)
#define MAX77833_BATP_IM (1 << 2)
#define MAX77833_BAT_IM (1 << 3)
#define MAX77833_CHG_IM (1 << 4)
#define MAX77833_WCIN_IM (1 << 5)
#define MAX77833_CHGIN_IM (1 << 6)
#define MAX77833_AICL_IM (1 << 7)
/* MAX77833_CHG_REG_CHG_INT_OK */
#define MAX77833_BYP_OK 0x01
#define MAX77833_BYP_OK_SHIFT 0
#define MAX77833_BATP_OK 0x04
#define MAX77833_BATP_OK_SHIFT 2
#define MAX77833_BAT_OK 0x08
#define MAX77833_BAT_OK_SHIFT 3
#define MAX77833_CHG_OK 0x10
#define MAX77833_CHG_OK_SHIFT 4
#define MAX77833_WCIN_OK 0x20
#define MAX77833_WCIN_OK_SHIFT 5
#define MAX77833_CHGIN_OK 0x40
#define MAX77833_CHGIN_OK_SHIFT 6
#define MAX77833_AICL_OK 0x04
#define MAX77833_AICL_OK_SHIFT 7
/* MAX77833_CHG_REG_CHG_DTLS_00 */
#define MAX77833_BATP_DTLS 0x01
#define MAX77833_BATP_DTLS_SHIFT 0
#define MAX77833_WCIN_DTLS 0x30
#define MAX77833_WCIN_DTLS_SHIFT 4
#define MAX77833_CHGIN_DTLS 0xC0
#define MAX77833_CHGIN_DTLS_SHIFT 6
/* MAX77833_CHG_REG_CHG_DTLS_01 */
#define MAX77833_CHG_DTLS 0x0F
#define MAX77833_CHG_DTLS_SHIFT 0
#define MAX77833_BAT_DTLS 0x70
#define MAX77833_BAT_DTLS_SHIFT 4
/* MAX77833_CHG_REG_CHG_DTLS_02 */
#define MAX77833_BYP_DTLS 0x0F
#define MAX77833_BYP_DTLS_SHIFT 0
#define MAX77833_BYP_DTLS0 0x1
#define MAX77833_BYP_DTLS1 0x2
#define MAX77833_BYP_DTLS2 0x4
#define MAX77833_BYP_DTLS3 0x8
/* MAX77833_CHG_REG_CHG_CNFG_00 */
#define CHG_CNFG_00_MODE_SHIFT 0
#define CHG_CNFG_00_CHG_SHIFT 0
#define CHG_CNFG_00_OTG_SHIFT 1
#define CHG_CNFG_00_BUCK_SHIFT 2
#define CHG_CNFG_00_BOOST_SHIFT 3
#define CHG_CNFG_00_MODE_MASK (0xf << CHG_CNFG_00_MODE_SHIFT)
#define CHG_CNFG_00_CHG_MASK (1 << CHG_CNFG_00_CHG_SHIFT)
#define CHG_CNFG_00_OTG_MASK (1 << CHG_CNFG_00_OTG_SHIFT)
#define CHG_CNFG_00_BUCK_MASK (1 << CHG_CNFG_00_BUCK_SHIFT)
#define CHG_CNFG_00_BOOST_MASK (1 << CHG_CNFG_00_BOOST_SHIFT)
#define CHG_CNFG_00_OTG_CTRL (CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK)
#define MAX77833_MODE_DEFAULT 0x04
#define MAX77833_MODE_CHGR 0x01
#define MAX77833_MODE_OTG 0x02
#define MAX77833_MODE_BUCK 0x04
#define MAX77833_MODE_BOOST 0x08
/* MAX77833_CHG_REG_CHG_CNFG_02 */
#define MAX77833_CHG_TO_ITH 0x07
#define MAX77833_CHG_TO_TIME 0x38
#define MAX77833_CHG_OTG_ILIM 0xC0
/* MAX77833_CHG_REG_CHG_CNFG_04 */
#define MAX77833_CHG_MINVSYS_MASK 0xE0
#define MAX77833_CHG_MINVSYS_SHIFT 5
#define MAX77833_CHG_PRM_MASK 0x1F
#define MAX77833_CHG_PRM_SHIFT 0
/* MAX77833_CHG_REG_CHG_CNFG_17 */
#define MAX77833_CHG_WCIN_LIM 0x7F
#define REDUCE_CURRENT_STEP 100
#define MINIMUM_INPUT_CURRENT 300
#define SIOP_INPUT_LIMIT_CURRENT 1200
#define SIOP_CHARGING_LIMIT_CURRENT 1000
#define SIOP_WIRELESS_INPUT_LIMIT_CURRENT 530
#define SIOP_WIRELESS_CHARGING_LIMIT_CURRENT 780
#define SIOP_HV_INPUT_LIMIT_CURRENT 700
#define SIOP_HV_CHARGING_LIMIT_CURRENT 1000
#define SLOW_CHARGING_CURRENT_STANDARD 400
#define INPUT_CURRENT_TA 1000
struct max77833_charger_data {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *pmic_i2c;
struct mutex charger_mutex;
struct max77833_platform_data *max77833_pdata;
struct power_supply psy_chg;
struct workqueue_struct *wqueue;
struct work_struct chgin_work;
struct delayed_work isr_work;
struct delayed_work recovery_work; /* softreg recovery work */
struct delayed_work wpc_work; /* wpc detect work */
struct delayed_work chgin_init_work; /* chgin init work */
struct delayed_work afc_work;
struct delayed_work aicl_work;
/* mutex */
struct mutex irq_lock;
struct mutex ops_lock;
/* wakelock */
struct wake_lock recovery_wake_lock;
struct wake_lock wpc_wake_lock;
struct wake_lock afc_wake_lock;
struct wake_lock chgin_wake_lock;
struct wake_lock aicl_wake_lock;
unsigned int is_charging;
unsigned int charging_type;
unsigned int battery_state;
unsigned int battery_present;
unsigned int cable_type;
unsigned int charging_current_max;
unsigned int charging_current;
unsigned int input_current_limit;
unsigned int vbus_state;
int aicl_on;
int status;
int siop_level;
int uvlo_attach_flag;
int uvlo_attach_cable_type;
int irq_bypass;
int irq_batp;
int irq_aicl;
int irq_battery;
int irq_chg;
int irq_wcin;
int irq_chgin;
/* software regulation */
bool soft_reg_state;
int soft_reg_current;
/* unsufficient power */
bool reg_loop_deted;
/* wireless charge, w(wpc), v(vbus) */
int wc_w_gpio;
int wc_w_irq;
int wc_w_state;
int wc_v_gpio;
int wc_v_irq;
int wc_v_state;
bool wc_pwr_det;
int soft_reg_recovery_cnt;
bool afc_detect;
bool is_mdock;
int pmic_ver;
int input_curr_limit_step;
int wpc_input_curr_limit_step;
int charging_curr_step;
sec_charger_platform_data_t *pdata;
};
#endif /* __MAX77833_CHARGER_H */

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/*
* max77843_charger.h
* Samsung MAX77843 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77843_CHARGER_H
#define __MAX77843_CHARGER_H __FILE__
#include <linux/mfd/core.h>
#include <linux/mfd/max77843.h>
#include <linux/mfd/max77843-private.h>
#include <linux/regulator/machine.h>
#define MAX77843_CHG_SAFEOUT2 0x80
/* MAX77843_CHG_REG_CHG_INT */
#define MAX77843_BYP_I (1 << 0)
#define MAX77843_BATP_I (1 << 2)
#define MAX77843_BAT_I (1 << 3)
#define MAX77843_CHG_I (1 << 4)
#define MAX77843_WCIN_I (1 << 5)
#define MAX77843_CHGIN_I (1 << 6)
/* MAX77843_CHG_REG_CHG_INT_MASK */
#define MAX77843_BYP_IM (1 << 0)
#define MAX77843_THM_IM (1 << 2)
#define MAX77843_BAT_IM (1 << 3)
#define MAX77843_CHG_IM (1 << 4)
#define MAX77843_WCIN_IM (1 << 5)
#define MAX77843_CHGIN_IM (1 << 6)
/* MAX77843_CHG_REG_CHG_INT_OK */
#define MAX77843_BYP_OK 0x01
#define MAX77843_BYP_OK_SHIFT 0
#define MAX77843_BATP_OK 0x04
#define MAX77843_BATP_OK_SHIFT 2
#define MAX77843_BAT_OK 0x08
#define MAX77843_BAT_OK_SHIFT 3
#define MAX77843_CHG_OK 0x10
#define MAX77843_CHG_OK_SHIFT 4
#define MAX77843_WCIN_OK 0x20
#define MAX77843_WCIN_OK_SHIFT 5
#define MAX77843_CHGIN_OK 0x40
#define MAX77843_CHGIN_OK_SHIFT 6
#define MAX77843_DETBAT 0x04
#define MAX77843_DETBAT_SHIFT 2
/* MAX77843_CHG_REG_CHG_DTLS_00 */
#define MAX77843_BATP_DTLS 0x01
#define MAX77843_BATP_DTLS_SHIFT 0
#define MAX77843_WCIN_DTLS 0x18
#define MAX77843_WCIN_DTLS_SHIFT 3
#define MAX77843_CHGIN_DTLS 0x60
#define MAX77843_CHGIN_DTLS_SHIFT 5
/* MAX77843_CHG_REG_CHG_DTLS_01 */
#define MAX77843_CHG_DTLS 0x0F
#define MAX77843_CHG_DTLS_SHIFT 0
#define MAX77843_BAT_DTLS 0x70
#define MAX77843_BAT_DTLS_SHIFT 4
/* MAX77843_CHG_REG_CHG_DTLS_02 */
#define MAX77843_BYP_DTLS 0x0F
#define MAX77843_BYP_DTLS_SHIFT 0
#define MAX77843_BYP_DTLS0 0x1
#define MAX77843_BYP_DTLS1 0x2
#define MAX77843_BYP_DTLS2 0x4
#define MAX77843_BYP_DTLS3 0x8
/* MAX77843_CHG_REG_CHG_CNFG_00 */
#define CHG_CNFG_00_MODE_SHIFT 0
#define CHG_CNFG_00_CHG_SHIFT 0
#define CHG_CNFG_00_OTG_SHIFT 1
#define CHG_CNFG_00_BUCK_SHIFT 2
#define CHG_CNFG_00_BOOST_SHIFT 3
#define CHG_CNFG_00_MODE_MASK (0xf << CHG_CNFG_00_MODE_SHIFT)
#define CHG_CNFG_00_CHG_MASK (1 << CHG_CNFG_00_CHG_SHIFT)
#define CHG_CNFG_00_OTG_MASK (1 << CHG_CNFG_00_OTG_SHIFT)
#define CHG_CNFG_00_BUCK_MASK (1 << CHG_CNFG_00_BUCK_SHIFT)
#define CHG_CNFG_00_BOOST_MASK (1 << CHG_CNFG_00_BOOST_SHIFT)
#define CHG_CNFG_00_OTG_CTRL (CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK)
#define MAX77843_MODE_DEFAULT 0x04
#define MAX77843_MODE_CHGR 0x01
#define MAX77843_MODE_OTG 0x02
#define MAX77843_MODE_BUCK 0x04
#define MAX77843_MODE_BOOST 0x08
/* MAX&7843_CHG_REG_CHG_CNFG_01 */
#define MAX77843_CHG_FQ_2MHz (1 << 3)
/* MAX77843_CHG_REG_CHG_CNFG_02 */
#define MAX77843_CHG_CC 0x3F
/* MAX77843_CHG_REG_CHG_CNFG_03 */
#define MAX77843_CHG_TO_ITH 0x07
/* MAX77843_CHG_REG_CHG_CNFG_04 */
#define MAX77843_CHG_MINVSYS_MASK 0xE0
#define MAX77843_CHG_MINVSYS_SHIFT 5
#define MAX77843_CHG_PRM_MASK 0x1F
#define MAX77843_CHG_PRM_SHIFT 0
#define CHG_CNFG_04_CHG_CV_PRM_SHIFT 0
#define CHG_CNFG_04_CHG_CV_PRM_MASK (0x3F << CHG_CNFG_04_CHG_CV_PRM_SHIFT)
/* MAX77843_CHG_REG_CHG_CNFG_09 */
#define MAX77843_CHG_CHGIN_LIM 0x7F
/* MAX77843_CHG_REG_CHG_CNFG_10 */
#define MAX77843_CHG_WCIN_LIM 0x3F
/* MAX77843_CHG_REG_CHG_CNFG_12 */
#define MAX77843_CHG_WCINSEL 0x40
/* MAX77843_CHG_REG_CHG_DTLS_00 */
#define MAX77843_BATP_DTLS 0x01
#define MAX77843_BATP_DTLS_SHIFT 0
#define MAX77843_WCIN_DTLS 0x18
#define MAX77843_WCIN_DTLS_SHIFT 3
#define MAX77843_CHGIN_DTLS 0x60
#define MAX77843_CHGIN_DTLS_SHIFT 5
/* MAX77843_CHG_DETAILS_01 */
#define MAX77843_CHG_DTLS 0x0F
#define MAX77843_CHG_DTLS_SHIFT 0
#define MAX77843_BAT_DTLS 0x70
#define MAX77843_BAT_DTLS_SHIFT 4
#define SIOP_INPUT_LIMIT_CURRENT 1200
#define SIOP_CHARGING_LIMIT_CURRENT 1000
#define SIOP_WIRELESS_INPUT_LIMIT_CURRENT 660
#define SIOP_WIRELESS_CHARGING_LIMIT_CURRENT 780
#define SLOW_CHARGING_CURRENT_STANDARD 400
struct max77843_charger_data {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *pmic_i2c;
struct mutex charger_mutex;
struct max77843_platform_data *max77843_pdata;
struct power_supply psy_chg;
struct workqueue_struct *wqueue;
struct work_struct chgin_work;
struct delayed_work isr_work;
struct delayed_work recovery_work; /* softreg recovery work */
struct delayed_work wpc_work; /* wpc detect work */
struct delayed_work chgin_init_work; /* chgin init work */
struct delayed_work afc_work;
/* mutex */
struct mutex irq_lock;
struct mutex ops_lock;
/* wakelock */
struct wake_lock recovery_wake_lock;
struct wake_lock wpc_wake_lock;
struct wake_lock chgin_wake_lock;
unsigned int is_charging;
unsigned int charging_type;
unsigned int battery_state;
unsigned int battery_present;
unsigned int cable_type;
unsigned int charging_current_max;
unsigned int charging_current;
unsigned int input_current_limit;
unsigned int vbus_state;
int aicl_on;
int status;
int siop_level;
int uvlo_attach_flag;
int uvlo_attach_cable_type;
int irq_bypass;
int irq_batp;
int irq_battery;
int irq_chg;
int irq_wcin;
int irq_chgin;
/* software regulation */
bool soft_reg_state;
int soft_reg_current;
/* unsufficient power */
bool reg_loop_deted;
/* wireless charge, w(wpc), v(vbus) */
int wc_w_gpio;
int wc_w_irq;
int wc_w_state;
int wc_v_gpio;
int wc_v_irq;
int wc_v_state;
bool wc_pwr_det;
int soft_reg_recovery_cnt;
bool afc_detect;
bool is_mdock;
int pmic_ver;
int input_curr_limit_step;
int wpc_input_curr_limit_step;
int charging_curr_step;
sec_battery_platform_data_t *pdata;
};
#endif /* __MAX77843_CHARGER_H */

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/*
* drivers/battery/s2mu003_charger.h
*
* Header of Richtek S2MU003 Fuelgauge Driver
*
* Copyright (C) 2013 Richtek Technology Corp.
* Patrick Chang <patrick_chang@richtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef S2MU003_CHARGER_H
#define S2MU003_CHARGER_H
#include <linux/mfd/samsung/s2mu003.h>
#include <linux/mfd/samsung/s2mu003_irq.h>
#define S2MU003_CHG_STATUS1 0x00
#define S2MU003_CHG_CTRL1 0x01
#define S2MU003_CHG_CTRL2 0x02
#define S2MU003_CHG_CTRL3 0x04
#define S2MU003_CHG_CTRL4 0x05
#define S2MU003_CHG_CTRL5 0x06
#define S2MU003_SOFTRESET 0x07
#define S2MU003_CHG_CTRL6 0x08
#define S2MU003_CHG_CTRL7 0x09
#define S2MU003_CHG_CTRL8 0x0A
#define S2MU003_CHG_STATUS2 0x0B
#define S2MU003_CHG_STATUS3 0x0C
#define S2MU003_CHG_STATUS4 0x0D
#define S2MU003_CHG_CTRL9 0x0E
#define S2MU003_OTG_SS_ENB_MASK (1 << 0)
#define S2MU003_OPAMODE_MASK (1 << 0)
#define S2MU003_CHG_EN_MASK (1 << 6)
#define S2MU003_TIMEREN_MASK (1 << 0)
#define S2MU003_SEL_SWFREQ_MASK (1 << 2)
#define S2MU003_TEEN_MASK (1 << 3)
#define S2MU003_AICR_LIMIT_MASK (0x7 << 5)
#define S2MU003_AICR_LIMIT_SHIFT 5
#define S2MU003_MIVR_MASK (0x7 << 5)
#define S2MU003_MIVR_SHIFT 5
#define S2MU003_VOREG_MASK (0x3f << 2)
#define S2MU003_VOREG_SHIFT 2
#define S2MU003_IEOC_MASK 0x07
#define S2MU003_IEOC_SHIFT 0
#define S2MU003_ICHRG_MASK 0xf0
#define S2MU003_ICHRG_SHIFT 4
#define S2MU003_CHG_IRQ1 0x60
#define S2MU003_CHG_IRQ2 0x61
#define S2MU003_CHG_IRQ3 0x62
#define S2MU003_CHG_IRQ_CTRL1 0x63
#define S2MU003_CHG_IRQ_CTRL2 0x64
#define S2MU003_CHG_IRQ_CTRL3 0x65
/* S2MU003_CHG_STAT */
#define S2MU003_EXT_PMOS_CTRL 0x1
#define S2MU003_EXT_PMOS_CTRL_SHIFT 7
#define S2MU003SW_HW_CTRL 0x1
#define S2MU003SW_HW_CTRL_SHIFT 2
#define S2MU003_OTG_SS_DISABLE 0x1
#define S2MU003_OTG_SS_DISABLE_SHIFT 1
/* S2MU003_CHR_CTRL1 */
#define S2MU003_IAICR 0x101
#define S2MU003_IAICR_SHIFT 5
#define S2MU003_HIGHER_OCP 0x1
#define S2MU003_HIGHER_OCP_SHIFT 4
#define S2MU003_TERMINATION_EN 0x0
#define S2MU003_TERMINATION_EN_SHIFT 3
#define S2MU003_SEL_SWFREQ 0x1
#define S2MU003_SEL_SWFREQ_SHIFT 2
#define S2MU003_HIGH_IMPEDANCE 0
#define S2MU003_HIGH_IMPEDANCE_SHIFT 1
#define S2MU003_OPA_MODE 2
#define S2MU003_OPA_MODE_SHIFT 0
/* S2MU003_CHG_CTRL2 */
#define S2MU003_REG_VOLTAGE 0x011100
#define S2MU003_REG_VOLTAGE_SHIFT 2
#define S2MU003_TDEG_EOC 0x0
#define S2MU003_TDEG_EOC_SHIFT 0
/* S2MU003_CHG_CTRL3 */
#define S2MU003_PPC_TE 0x0
#define S2MU003_PPC_TE_SHIFT 7
#define S2MU003_CHG_EN 0x1
#define S2MU003_CHG_EN_SHIFT 6
enum {
CHG_REG = 0,
CHG_DATA,
CHG_REGS,
};
struct charger_info {
int dummy;
};
#endif /*S2MU003_CHARGER_H*/

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/*
* smb347_charger.h
* Samsung SMB347 Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SMB347_CHARGER_H
#define __SMB347_CHARGER_H __FILE__
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define SEC_CHARGER_I2C_SLAVEADDR (0x0C >> 1)
/* Register define */
#define SMB347_CHARGE_CURRENT 0x00
#define SMB347_INPUT_CURRENTLIMIT 0x01
#define SMB347_VARIOUS_FUNCTIONS 0x02
#define SMB347_FLOAT_VOLTAGE 0x03
#define SMB347_CHARGE_CONTROL 0x04
#define SMB347_STAT_TIMERS_CONTROL 0x05
#define SMB347_PIN_ENABLE_CONTROL 0x06
#define SMB347_THERM_CONTROL_A 0x07
#define SMB347_SYSOK_USB30_SELECTION 0x08
#define SMB347_OTHER_CONTROL_A 0x09
#define SMB347_OTG_TLIM_THERM_CONTROL 0x0A
#define SMB347_LIMIT_CELL_TEMPERATURE_MONITOR 0x0B
#define SMB347_FAULT_INTERRUPT 0x0C
#define SMB347_STATUS_INTERRUPT 0x0D
#define SMB347_I2C_BUS_SLAVE_ADDR 0x0E
#define SMB347_COMMAND_A 0x30
#define SMB347_COMMAND_B 0x31
#define SMB347_COMMAND_C 0x33
#define SMB347_INTERRUPT_STATUS_A 0x35
#define SMB347_INTERRUPT_STATUS_B 0x36
#define SMB347_INTERRUPT_STATUS_C 0x37
#define SMB347_INTERRUPT_STATUS_D 0x38
#define SMB347_INTERRUPT_STATUS_E 0x39
#define SMB347_INTERRUPT_STATUS_F 0x3A
#define SMB347_STATUS_A 0x3B
#define SMB347_STATUS_B 0x3C
#define SMB347_STATUS_C 0x3D
#define SMB347_STATUS_D 0x3E
#define SMB347_STATUS_E 0x3F
#endif /* __SMB347_CHARGER_H */

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include/linux/battery/fuelgauge/max17048_fuelgauge.h Normal file
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/*
* max17048_fuelgauge.h
* Samsung MAX17048 Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX17048_FUELGAUGE_H
#define __MAX17048_FUELGAUGE_H __FILE__
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define SEC_FUELGAUGE_I2C_SLAVEADDR (0x6D >> 1)
#define MAX17048_VCELL_MSB 0x02
#define MAX17048_VCELL_LSB 0x03
#define MAX17048_SOC_MSB 0x04
#define MAX17048_SOC_LSB 0x05
#define MAX17048_MODE_MSB 0x06
#define MAX17048_MODE_LSB 0x07
#define MAX17048_VER_MSB 0x08
#define MAX17048_VER_LSB 0x09
#define MAX17048_RCOMP_MSB 0x0C
#define MAX17048_RCOMP_LSB 0x0D
#define MAX17048_OCV_MSB 0x0E
#define MAX17048_OCV_LSB 0x0F
#define MAX17048_CMD_MSB 0xFE
#define MAX17048_CMD_LSB 0xFF
#define RCOMP0_TEMP 20
#define AVER_SAMPLE_CNT 5
struct battery_data_t {
u8 RCOMP0;
u8 RCOMP_charging;
int temp_cohot;
int temp_cocold;
bool is_using_model_data;
u8 *type_str;
};
struct sec_fg_info {
bool dummy;
};
#endif /* __MAX17048_FUELGAUGE_H */

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include/linux/battery/fuelgauge/max17050_fuelgauge.h Normal file
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/*
* max17050_fuelgauge.h
* Samsung MAX17050 Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX17050_FUELGAUGE_H
#define __MAX17050_FUELGAUGE_H __FILE__
#if defined(ANDROID_ALARM_ACTIVATED)
#include <linux/android_alarm.h>
#endif
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define SEC_FUELGAUGE_I2C_SLAVEADDR 0x36
#if defined(CONFIG_FUELGAUGE_MAX17050_VOLTAGE_TRACKING)
#define MAX17050_REG_STATUS 0x00
#define MAX17050_REG_VALRT_TH 0x01
#define MAX17050_REG_TALRT_TH 0x02
#define MAX17050_REG_SALRT_TH 0x03
#define MAX17050_REG_VCELL 0x09
#define MAX17050_REG_TEMPERATURE 0x08
#define MAX17050_REG_AVGVCELL 0x19
#define MAX17050_REG_CONFIG 0x1D
#define MAX17050_REG_VERSION 0x21
#define MAX17050_REG_LEARNCFG 0x28
#define MAX17050_REG_FILTERCFG 0x29
#define MAX17050_REG_MISCCFG 0x2B
#define MAX17050_REG_CGAIN 0x2E
#define MAX17050_REG_RCOMP 0x38
#define MAX17050_REG_VFOCV 0xFB
#define MAX17050_REG_SOC_VF 0xFF
struct battery_data_t {
u8 *type_str;
};
struct sec_fg_info {
bool dummy;
};
#endif
#if defined(CONFIG_FUELGAUGE_MAX17050_COULOMB_COUNTING)
#define PRINT_COUNT 10
/* Register address */
#define STATUS_REG 0x00
#define VALRT_THRESHOLD_REG 0x01
#define TALRT_THRESHOLD_REG 0x02
#define SALRT_THRESHOLD_REG 0x03
#define REMCAP_REP_REG 0x05
#define SOCREP_REG 0x06
#define TEMPERATURE_REG 0x08
#define VCELL_REG 0x09
#define CURRENT_REG 0x0A
#define AVG_CURRENT_REG 0x0B
#define SOCMIX_REG 0x0D
#define SOCAV_REG 0x0E
#define REMCAP_MIX_REG 0x0F
#define FULLCAP_REG 0x10
#define RFAST_REG 0x15
#define AVR_TEMPERATURE_REG 0x16
#define CYCLES_REG 0x17
#define DESIGNCAP_REG 0x18
#define AVR_VCELL_REG 0x19
#define CONFIG_REG 0x1D
#define REMCAP_AV_REG 0x1F
#define FULLCAP_NOM_REG 0x23
#define MISCCFG_REG 0x2B
#define RCOMP_REG 0x38
#define FSTAT_REG 0x3D
#define DQACC_REG 0x45
#define DPACC_REG 0x46
#define OCV_REG 0xEE
#define VFOCV_REG 0xFB
#define VFSOC_REG 0xFF
#define LOW_BATT_COMP_RANGE_NUM 5
#define LOW_BATT_COMP_LEVEL_NUM 2
#define MAX_LOW_BATT_CHECK_CNT 10
enum {
FG_LEVEL = 0,
FG_TEMPERATURE,
FG_VOLTAGE,
FG_CURRENT,
FG_CURRENT_AVG,
FG_CHECK_STATUS,
FG_RAW_SOC,
FG_VF_SOC,
FG_AV_SOC,
FG_FULLCAP,
FG_MIXCAP,
FG_AVCAP,
FG_REPCAP,
};
enum {
POSITIVE = 0,
NEGATIVE,
};
enum {
RANGE = 0,
SLOPE,
OFFSET,
TABLE_MAX
};
#define CURRENT_RANGE_MAX_NUM 5
#define TEMP_RANGE_MAX_NUM 3
struct battery_data_t {
u16 Capacity;
u16 low_battery_comp_voltage;
s32 low_battery_table[CURRENT_RANGE_MAX_NUM][TABLE_MAX];
s32 temp_adjust_table[TEMP_RANGE_MAX_NUM][TABLE_MAX];
u8 *type_str;
};
struct sec_fg_info {
/* test print count */
int pr_cnt;
/* full charge comp */
struct delayed_work full_comp_work;
u32 previous_fullcap;
u32 previous_vffullcap;
/* low battery comp */
int low_batt_comp_cnt[LOW_BATT_COMP_RANGE_NUM][LOW_BATT_COMP_LEVEL_NUM];
int low_batt_comp_flag;
/* low battery boot */
int low_batt_boot_flag;
bool is_low_batt_alarm;
/* battery info */
u32 soc;
/* miscellaneous */
unsigned long fullcap_check_interval;
int full_check_flag;
bool is_first_check;
};
/* FullCap learning setting */
#define VFFULLCAP_CHECK_INTERVAL 300 /* sec */
/* soc should be 0.1% unit */
#define VFSOC_FOR_FULLCAP_LEARNING 950
#define LOW_CURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_CURRENT_FOR_FULLCAP_LEARNING 120
#define LOW_AVGCURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_AVGCURRENT_FOR_FULLCAP_LEARNING 100
/* power off margin */
/* soc should be 0.1% unit */
#define POWER_OFF_SOC_HIGH_MARGIN 20
#define POWER_OFF_VOLTAGE_HIGH_MARGIN 3500
#define POWER_OFF_VOLTAGE_LOW_MARGIN 3400
/* FG recovery handler */
/* soc should be 0.1% unit */
#define STABLE_LOW_BATTERY_DIFF 30
#define STABLE_LOW_BATTERY_DIFF_LOWBATT 10
#define LOW_BATTERY_SOC_REDUCE_UNIT 10
#endif
#endif /* __MAX17050_FUELGAUGE_H */

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include/linux/battery/fuelgauge/max77823_fuelgauge.h Normal file
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/*
* max77823_fuelgauge.h
* Samsung MAX77823 Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX17050_FUELGAUGE_H
#define __MAX17050_FUELGAUGE_H __FILE__
#if defined(ANDROID_ALARM_ACTIVATED)
#include <linux/android_alarm.h>
#endif
#include <linux/mfd/core.h>
#include <linux/mfd/max77823.h>
#include <linux/mfd/max77823-private.h>
#include <linux/regulator/machine.h>
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#if defined(CONFIG_FUELGAUGE_MAX77823_VOLTAGE_TRACKING)
#define MAX77823_REG_STATUS 0x00
#define MAX77823_REG_VALRT_TH 0x01
#define MAX77823_REG_TALRT_TH 0x02
#define MAX77823_REG_SALRT_TH 0x03
#define MAX77823_REG_VCELL 0x09
#define MAX77823_REG_TEMPERATURE 0x08
#define MAX77823_REG_AVGVCELL 0x19
#define MAX77823_REG_CONFIG 0x1D
#define MAX77823_REG_VERSION 0x21
#define MAX77823_REG_LEARNCFG 0x28
#define MAX77823_REG_FILTERCFG 0x29
#define MAX77823_REG_MISCCFG 0x2B
#define MAX77823_REG_CGAIN 0x2E
#define MAX77823_REG_RCOMP 0x38
#define MAX77823_REG_VFOCV 0xFB
#define MAX77823_REG_SOC_VF 0xFF
struct battery_data_t {
u8 *type_str;
};
struct sec_fg_info {
bool dummy;
};
#endif
#if defined(CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING)
#define PRINT_COUNT 10
#define LOW_BATT_COMP_RANGE_NUM 5
#define LOW_BATT_COMP_LEVEL_NUM 2
#define MAX_LOW_BATT_CHECK_CNT 10
enum {
FG_LEVEL = 0,
FG_TEMPERATURE,
FG_VOLTAGE,
FG_CURRENT,
FG_CURRENT_AVG,
FG_CHECK_STATUS,
FG_RAW_SOC,
FG_VF_SOC,
FG_AV_SOC,
FG_FULLCAP,
FG_MIXCAP,
FG_AVCAP,
FG_REPCAP,
};
enum {
POSITIVE = 0,
NEGATIVE,
};
enum {
RANGE = 0,
SLOPE,
OFFSET,
TABLE_MAX
};
#define CURRENT_RANGE_MAX_NUM 5
struct battery_data_t {
u32 Capacity;
u32 low_battery_comp_voltage;
s32 low_battery_table[CURRENT_RANGE_MAX_NUM][TABLE_MAX];
u8 *type_str;
};
struct sec_fg_info {
/* test print count */
int pr_cnt;
/* full charge comp */
struct delayed_work full_comp_work;
u32 previous_fullcap;
u32 previous_vffullcap;
/* low battery comp */
int low_batt_comp_cnt[LOW_BATT_COMP_RANGE_NUM][LOW_BATT_COMP_LEVEL_NUM];
int low_batt_comp_flag;
/* low battery boot */
int low_batt_boot_flag;
bool is_low_batt_alarm;
/* battery info */
u32 soc;
/* miscellaneous */
unsigned long fullcap_check_interval;
int full_check_flag;
bool is_first_check;
};
/* FullCap learning setting */
#define VFFULLCAP_CHECK_INTERVAL 300 /* sec */
/* soc should be 0.1% unit */
#define VFSOC_FOR_FULLCAP_LEARNING 950
#define LOW_CURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_CURRENT_FOR_FULLCAP_LEARNING 120
#define LOW_AVGCURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_AVGCURRENT_FOR_FULLCAP_LEARNING 100
/* power off margin */
/* soc should be 0.1% unit */
#define POWER_OFF_SOC_HIGH_MARGIN 20
#define POWER_OFF_VOLTAGE_HIGH_MARGIN 3500
#define POWER_OFF_VOLTAGE_LOW_MARGIN 3400
/* FG recovery handler */
/* soc should be 0.1% unit */
#define STABLE_LOW_BATTERY_DIFF 30
#define STABLE_LOW_BATTERY_DIFF_LOWBATT 10
#define LOW_BATTERY_SOC_REDUCE_UNIT 10
#endif
struct max77823_fuelgauge_data {
struct device *dev;
struct i2c_client *i2c;
struct mutex fuelgauge_mutex;
struct max77823_platform_data *max77823_pdata;
sec_battery_platform_data_t *pdata;
struct power_supply psy_fg;
struct delayed_work isr_work;
int cable_type;
bool is_charging;
/* HW-dedicated fuel guage info structure
* used in individual fuel gauge file only
* (ex. dummy_fuelgauge.c)
*/
struct sec_fg_info info;
struct battery_data_t *battery_data;
bool is_fuel_alerted;
struct wake_lock fuel_alert_wake_lock;
unsigned int capacity_old; /* only for atomic calculation */
unsigned int capacity_max; /* only for dynamic calculation */
bool initial_update_of_soc;
struct mutex fg_lock;
/* register programming */
int reg_addr;
u8 reg_data[2];
int fg_irq;
};
#endif /* __MAX77823_FUELGAUGE_H */

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/*
* max77833_fuelgauge.h
* Samsung MAX77833 Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
* This software is 77833 under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX77833_FUELGAUGE_H
#define __MAX77833_FUELGAUGE_H __FILE__
#if defined(ANDROID_ALARM_ACTIVATED)
#include <linux/android_alarm.h>
#endif
#include <linux/battery/sec_charging_common.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77833.h>
#include <linux/mfd/max77833-private.h>
#include <linux/regulator/machine.h>
#include <linux/wakelock.h>
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define PRINT_COUNT 10
#define LOW_BATT_COMP_RANGE_NUM 5
#define LOW_BATT_COMP_LEVEL_NUM 2
#define MAX_LOW_BATT_CHECK_CNT 10
#define ALERT_EN 0x04
struct sec_fuelgauge_reg_data {
u8 reg_addr;
u8 reg_data1;
u8 reg_data2;
};
struct max77833_fg_info {
/* test print count */
int pr_cnt;
/* full charge comp */
struct delayed_work full_comp_work;
u32 previous_fullcap;
u32 previous_vffullcap;
/* low battery comp */
int low_batt_comp_cnt[LOW_BATT_COMP_RANGE_NUM][LOW_BATT_COMP_LEVEL_NUM];
int low_batt_comp_flag;
/* low battery boot */
int low_batt_boot_flag;
bool is_low_batt_alarm;
/* battery info */
u32 soc;
/* miscellaneous */
unsigned long fullcap_check_interval;
int full_check_flag;
bool is_first_check;
};
enum {
MAX77833_FG_LEVEL = 0,
MAX77833_FG_TEMPERATURE,
MAX77833_FG_VOLTAGE,
MAX77833_FG_CURRENT,
MAX77833_FG_CURRENT_AVG,
MAX77833_FG_CHECK_STATUS,
MAX77833_FG_RAW_SOC,
MAX77833_FG_VF_SOC,
MAX77833_FG_AV_SOC,
MAX77833_FG_FULLCAP,
MAX77833_FG_FULLCAPNOM,
MAX77833_FG_FULLCAPREP,
MAX77833_FG_MIXCAP,
MAX77833_FG_AVCAP,
MAX77833_FG_REPCAP,
MAX77833_FG_CYCLE,
};
enum {
MAX77833_POSITIVE = 0,
MAX77833_NEGATIVE,
};
enum {
MAX77833_RANGE = 0,
MAX77833_SLOPE,
MAX77833_OFFSET,
MAX77833_TABLE_MAX
};
#define CURRENT_RANGE_MAX_NUM 5
struct battery_data_t {
u32 QResidual20;
u32 QResidual30;
u32 Capacity;
u32 low_battery_comp_voltage;
s32 low_battery_table[CURRENT_RANGE_MAX_NUM][MAX77833_TABLE_MAX];
u8 *type_str;
u32 ichgterm;
u32 misccfg;
u32 fullsocthr;
u32 ichgterm_2nd;
u32 misccfg_2nd;
u32 fullsocthr_2nd;
};
/* FullCap learning setting */
#define VFFULLCAP_CHECK_INTERVAL 300 /* sec */
/* soc should be 0.1% unit */
#define VFSOC_FOR_FULLCAP_LEARNING 950
#define LOW_CURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_CURRENT_FOR_FULLCAP_LEARNING 120
#define LOW_AVGCURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_AVGCURRENT_FOR_FULLCAP_LEARNING 100
/* power off margin */
/* soc should be 0.1% unit */
#define POWER_OFF_SOC_HIGH_MARGIN 20
#define POWER_OFF_VOLTAGE_HIGH_MARGIN 3500
#define POWER_OFF_VOLTAGE_LOW_MARGIN 3400
/* FG recovery handler */
/* soc should be 0.1% unit */
#define STABLE_LOW_BATTERY_DIFF 30
#define STABLE_LOW_BATTERY_DIFF_LOWBATT 10
#define LOW_BATTERY_SOC_REDUCE_UNIT 10
struct cv_slope{
int fg_current;
int soc;
int time;
};
struct max77833_fuelgauge_data {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *pmic;
struct mutex fuelgauge_mutex;
struct max77833_platform_data *max77833_pdata;
sec_fuelgauge_platform_data_t *pdata;
struct power_supply psy_fg;
struct delayed_work isr_work;
int cable_type;
bool is_charging;
/* HW-dedicated fuel guage info structure
* used in individual fuel gauge file only
* (ex. dummy_fuelgauge.c)
*/
struct max77833_fg_info info;
struct battery_data_t *battery_data;
bool is_fuel_alerted;
struct wake_lock fuel_alert_wake_lock;
unsigned int capacity_old; /* only for atomic calculation */
unsigned int capacity_max; /* only for dynamic calculation */
unsigned int standard_capacity;
bool initial_update_of_soc;
struct mutex fg_lock;
/* register programming */
int reg_addr;
u8 reg_data[2];
unsigned int pre_soc;
int fg_irq;
int raw_capacity;
int current_now;
int current_avg;
struct cv_slope *cv_data;
int cv_data_lenth;
};
#endif /* __MAX77833_FUELGAUGE_H */

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/*
* max77843_fuelgauge.h
* Samsung MAX77843 Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
* This software is 77843 under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MAX17050_FUELGAUGE_H
#define __MAX17050_FUELGAUGE_H __FILE__
#if defined(ANDROID_ALARM_ACTIVATED)
#include <linux/android_alarm.h>
#endif
#include <linux/mfd/core.h>
#include <linux/mfd/max77843.h>
#include <linux/mfd/max77843-private.h>
#include <linux/regulator/machine.h>
/* Slave address should be shifted to the right 1bit.
* R/W bit should NOT be included.
*/
#define PRINT_COUNT 10
#define LOW_BATT_COMP_RANGE_NUM 5
#define LOW_BATT_COMP_LEVEL_NUM 2
#define MAX_LOW_BATT_CHECK_CNT 10
#define ALERT_EN 0x04
enum {
FG_LEVEL = 0,
FG_TEMPERATURE,
FG_VOLTAGE,
FG_CURRENT,
FG_CURRENT_AVG,
FG_CHECK_STATUS,
FG_RAW_SOC,
FG_VF_SOC,
FG_AV_SOC,
FG_FULLCAP,
FG_MIXCAP,
FG_AVCAP,
FG_REPCAP,
};
enum {
POSITIVE = 0,
NEGATIVE,
};
enum {
RANGE = 0,
SLOPE,
OFFSET,
TABLE_MAX
};
#define CURRENT_RANGE_MAX_NUM 5
struct battery_data_t {
u32 QResidual20;
u32 QResidual30;
u32 Capacity;
u32 low_battery_comp_voltage;
s32 low_battery_table[CURRENT_RANGE_MAX_NUM][TABLE_MAX];
u8 *type_str;
u32 ichgterm;
u32 misccfg;
u32 fullsocthr;
u32 ichgterm_2nd;
u32 misccfg_2nd;
u32 fullsocthr_2nd;
};
struct sec_fg_info {
/* test print count */
int pr_cnt;
/* full charge comp */
struct delayed_work full_comp_work;
u32 previous_fullcap;
u32 previous_vffullcap;
/* low battery comp */
int low_batt_comp_cnt[LOW_BATT_COMP_RANGE_NUM][LOW_BATT_COMP_LEVEL_NUM];
int low_batt_comp_flag;
/* low battery boot */
int low_batt_boot_flag;
bool is_low_batt_alarm;
/* battery info */
u32 soc;
/* miscellaneous */
unsigned long fullcap_check_interval;
int full_check_flag;
bool is_first_check;
};
/* FullCap learning setting */
#define VFFULLCAP_CHECK_INTERVAL 300 /* sec */
/* soc should be 0.1% unit */
#define VFSOC_FOR_FULLCAP_LEARNING 950
#define LOW_CURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_CURRENT_FOR_FULLCAP_LEARNING 120
#define LOW_AVGCURRENT_FOR_FULLCAP_LEARNING 20
#define HIGH_AVGCURRENT_FOR_FULLCAP_LEARNING 100
/* power off margin */
/* soc should be 0.1% unit */
#define POWER_OFF_SOC_HIGH_MARGIN 20
#define POWER_OFF_VOLTAGE_HIGH_MARGIN 3500
#define POWER_OFF_VOLTAGE_LOW_MARGIN 3400
/* FG recovery handler */
/* soc should be 0.1% unit */
#define STABLE_LOW_BATTERY_DIFF 30
#define STABLE_LOW_BATTERY_DIFF_LOWBATT 10
#define LOW_BATTERY_SOC_REDUCE_UNIT 10
struct max77843_fuelgauge_data {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *pmic;
struct mutex fuelgauge_mutex;
struct max77843_platform_data *max77843_pdata;
sec_battery_platform_data_t *pdata;
struct power_supply psy_fg;
struct delayed_work isr_work;
int cable_type;
bool is_charging;
/* HW-dedicated fuel guage info structure
* used in individual fuel gauge file only
* (ex. dummy_fuelgauge.c)
*/
struct sec_fg_info info;
struct battery_data_t *battery_data;
bool is_fuel_alerted;
struct wake_lock fuel_alert_wake_lock;
unsigned int capacity_old; /* only for atomic calculation */
unsigned int capacity_max; /* only for dynamic calculation */
unsigned int standard_capacity;
bool initial_update_of_soc;
struct mutex fg_lock;
/* register programming */
int reg_addr;
u8 reg_data[2];
unsigned int pre_soc;
int fg_irq;
};
#endif /* __MAX77843_FUELGAUGE_H */

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/*
* sec_adc.h
* Samsung Mobile Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SEC_ADC_H
#define __SEC_ADC_H __FILE__
#include <linux/iio/consumer.h>
#include <linux/battery/sec_battery.h>
#include <linux/battery/sec_charging_common.h>
#define VENDOR_UNKNOWN 0
#define VENDOR_LSI 1
#define VENDOR_QCOM 2
#endif /* __SEC_ADC_H */

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/*
* sec_battery.h
* Samsung Mobile Battery Header
*
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SEC_BATTERY_H
#define __SEC_BATTERY_H __FILE__
#include <linux/battery/sec_charging_common.h>
#include <linux/of_gpio.h>
#include <linux/alarmtimer.h>
#include <linux/wakelock.h>
#include <linux/workqueue.h>
#include <linux/proc_fs.h>
#include <linux/jiffies.h>
#if defined(CONFIG_MUIC_NOTIFIER)
#include <linux/muic/muic.h>
#include <linux/muic/muic_notifier.h>
#endif /* CONFIG_MUIC_NOTIFIER */
#if defined(CONFIG_VBUS_NOTIFIER)
#include <linux/vbus_notifier.h>
#endif
#include <linux/sec_batt.h>
#define SEC_BAT_CURRENT_EVENT_NONE 0x0000
#define SEC_BAT_CURRENT_EVENT_AFC 0x0001
#define SEC_BAT_CURRENT_EVENT_LOW_TEMP_SWELLING 0x0010
#define SEC_BAT_CURRENT_EVENT_HIGH_TEMP_SWELLING 0x0020
#define SIOP_EVENT_NONE 0x0000
#define SIOP_EVENT_WPC_CALL 0x0001
#if defined(CONFIG_CHARGING_VZWCONCEPT)
#define STORE_MODE_CHARGING_MAX 35
#define STORE_MODE_CHARGING_MIN 30
#else
#define STORE_MODE_CHARGING_MAX 70
#define STORE_MODE_CHARGING_MIN 60
#endif
#define ADC_CH_COUNT 10
#define ADC_SAMPLE_COUNT 10
#define DEFAULT_HEALTH_CHECK_COUNT 5
#define TEMP_HIGHLIMIT_DEFAULT 2000
#define SIOP_INPUT_LIMIT_CURRENT 1200
#define SIOP_CHARGING_LIMIT_CURRENT 1000
#define SIOP_WIRELESS_INPUT_LIMIT_CURRENT 530
#define SIOP_WIRELESS_CHARGING_LIMIT_CURRENT 780
#define SIOP_HV_WIRELESS_INPUT_LIMIT_CURRENT 700
#define SIOP_HV_WIRELESS_CHARGING_LIMIT_CURRENT 600
#define SIOP_HV_INPUT_LIMIT_CURRENT 1200
#define SIOP_HV_CHARGING_LIMIT_CURRENT 1000
#define BATT_MISC_EVENT_UNDEFINED_RANGE_TYPE 0x00000001
#if defined(CONFIG_BATTERY_SWELLING)
enum swelling_mode_state {
SWELLING_MODE_NONE = 0,
SWELLING_MODE_CHARGING,
SWELLING_MODE_FULL,
SWELLING_MODE_ADDITIONAL,
};
#endif
struct adc_sample_info {
unsigned int cnt;
int total_adc;
int average_adc;
int adc_arr[ADC_SAMPLE_COUNT];
int index;
};
struct sec_battery_info {
struct device *dev;
sec_battery_platform_data_t *pdata;
/* power supply used in Android */
struct power_supply psy_bat;
struct power_supply psy_usb;
struct power_supply psy_ac;
struct power_supply psy_wireless;
struct power_supply psy_ps;
unsigned int irq;
struct notifier_block batt_nb;
#if defined(CONFIG_VBUS_NOTIFIER)
struct notifier_block vbus_nb;
#endif
int status;
int health;
bool present;
int voltage_now; /* cell voltage (mV) */
int voltage_avg; /* average voltage (mV) */
int voltage_ocv; /* open circuit voltage (mV) */
int current_now; /* current (mA) */
int inbat_adc; /* inbat adc */
int current_avg; /* average current (mA) */
int current_max; /* input current limit (mA) */
int current_adc;
unsigned int capacity; /* SOC (%) */
struct mutex adclock;
struct adc_sample_info adc_sample[ADC_CH_COUNT];
/* keep awake until monitor is done */
struct wake_lock monitor_wake_lock;
struct workqueue_struct *monitor_wqueue;
struct delayed_work monitor_work;
#ifdef CONFIG_SAMSUNG_BATTERY_FACTORY
struct wake_lock lpm_wake_lock;
#endif
unsigned int polling_count;
unsigned int polling_time;
bool polling_in_sleep;
bool polling_short;
struct delayed_work polling_work;
struct alarm polling_alarm;
ktime_t last_poll_time;
/* battery check */
unsigned int check_count;
/* ADC check */
unsigned int check_adc_count;
unsigned int check_adc_value;
/* health change check */
bool health_change;
/* ovp-uvlo health check */
int health_check_count;
/* time check */
unsigned long charging_start_time;
unsigned long charging_passed_time;
unsigned long charging_next_time;
unsigned long charging_fullcharged_time;
unsigned long wc_heating_start_time;
unsigned long wc_heating_passed_time;
unsigned int wc_heat_limit;
/* chg temperature check */
bool chg_limit;
/* wpc temperature and pad status check */
bool pad_limit;
/* temperature check */
int temperature; /* battery temperature */
int temper_amb; /* target temperature */
int chg_temp; /* charger temperature */
int pre_chg_temp;
int wpc_temp;
int slave_chg_temp;
int pre_slave_chg_temp;
int temp_adc;
int temp_ambient_adc;
int chg_temp_adc;
int wpc_temp_adc;
int slave_chg_temp_adc;
int temp_highlimit_threshold;
int temp_highlimit_recovery;
int temp_high_threshold;
int temp_high_recovery;
int temp_low_threshold;
int temp_low_recovery;
unsigned int temp_highlimit_cnt;
unsigned int temp_high_cnt;
unsigned int temp_low_cnt;
unsigned int temp_recover_cnt;
/* charging */
unsigned int charging_mode;
bool is_recharging;
int wdt_kick_disable;
bool is_jig_on;
int cable_type;
int muic_cable_type;
#if defined(CONFIG_VBUS_NOTIFIER)
int muic_vbus_status;
#endif
int extended_cable_type;
struct wake_lock cable_wake_lock;
struct delayed_work cable_work;
struct wake_lock vbus_wake_lock;
struct delayed_work siop_work;
struct wake_lock siop_wake_lock;
struct wake_lock afc_wake_lock;
struct delayed_work afc_work;
struct delayed_work wc_afc_work;
#if defined(CONFIG_WIRELESS_FIRMWARE_UPDATE)
struct delayed_work update_work;
struct delayed_work fw_init_work;
#endif
struct delayed_work siop_event_work;
struct wake_lock siop_event_wake_lock;
struct delayed_work siop_level_work;
struct wake_lock siop_level_wake_lock;
struct delayed_work wc_headroom_work;
struct wake_lock wc_headroom_wake_lock;
#if defined(CONFIG_UPDATE_BATTERY_DATA)
struct delayed_work batt_data_work;
struct wake_lock batt_data_wake_lock;
char *data_path;
#endif
unsigned int full_check_cnt;
unsigned int recharge_check_cnt;
struct mutex iolock;
int wired_input_current;
int wireless_input_current;
int charging_current;
int topoff_current;
unsigned int current_event;
/* wireless charging enable*/
int wc_enable;
int wc_status;
bool wc_cv_mode;
bool wc_pack_max_curr;
int wire_status;
/* wearable charging */
int ps_status;
int ps_enable;
/* test mode */
int test_mode;
bool factory_mode;
bool store_mode;
bool ignore_store_mode;
bool slate_mode;
/* MTBF test for CMCC */
bool is_hc_usb;
bool ignore_siop;
int r_siop_level;
int siop_level;
int siop_event;
int siop_prev_event;
int stability_test;
int eng_not_full_status;
bool skip_chg_temp_check;
bool skip_wpc_temp_check;
bool wpc_temp_mode;
#if defined(CONFIG_BATTERY_SWELLING_SELF_DISCHARGING)
bool factory_self_discharging_mode_on;
bool force_discharging;
bool self_discharging;
bool discharging_ntc;
int discharging_ntc_adc;
int self_discharging_adc;
#endif
#if defined(CONFIG_SW_SELF_DISCHARGING)
bool sw_self_discharging;
struct wake_lock self_discharging_wake_lock;
#endif
bool charging_block;
#if defined(CONFIG_BATTERY_SWELLING)
unsigned int swelling_mode;
int swelling_full_check_cnt;
#endif
#if defined(CONFIG_AFC_CHARGER_MODE)
char *hv_chg_name;
#endif
#if defined(CONFIG_CALC_TIME_TO_FULL)
int timetofull;
bool complete_timetofull;
struct delayed_work timetofull_work;
#endif
#if defined(CONFIG_BATTERY_AGE_FORECAST)
int batt_cycle;
#endif
#if defined(CONFIG_STEP_CHARGING)
int step_charging_status;
int step_charging_step;
#endif
int battery_type;
struct mutex misclock;
unsigned int misc_event;
unsigned int prev_misc_event;
struct delayed_work misc_event_work;
struct wake_lock misc_event_wake_lock;
};
ssize_t sec_bat_show_attrs(struct device *dev,
struct device_attribute *attr, char *buf);
ssize_t sec_bat_store_attrs(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#define SEC_BATTERY_ATTR(_name) \
{ \
.attr = {.name = #_name, .mode = 0664}, \
.show = sec_bat_show_attrs, \
.store = sec_bat_store_attrs, \
}
/* event check */
#define EVENT_NONE (0)
#define EVENT_2G_CALL (0x1 << 0)
#define EVENT_3G_CALL (0x1 << 1)
#define EVENT_MUSIC (0x1 << 2)
#define EVENT_VIDEO (0x1 << 3)
#define EVENT_BROWSER (0x1 << 4)
#define EVENT_HOTSPOT (0x1 << 5)
#define EVENT_CAMERA (0x1 << 6)
#define EVENT_CAMCORDER (0x1 << 7)
#define EVENT_DATA_CALL (0x1 << 8)
#define EVENT_WIFI (0x1 << 9)
#define EVENT_WIBRO (0x1 << 10)
#define EVENT_LTE (0x1 << 11)
#define EVENT_LCD (0x1 << 12)
#define EVENT_GPS (0x1 << 13)
enum {
BATT_RESET_SOC = 0,
BATT_READ_RAW_SOC,
BATT_READ_ADJ_SOC,
BATT_TYPE,
BATT_VFOCV,
BATT_VOL_ADC,
BATT_VOL_ADC_CAL,
BATT_VOL_AVER,
BATT_VOL_ADC_AVER,
BATT_CURRENT_UA_NOW,
BATT_CURRENT_UA_AVG,
BATT_TEMP,
BATT_TEMP_ADC,
BATT_TEMP_AVER,
BATT_TEMP_ADC_AVER,
BATT_CHG_TEMP,
BATT_CHG_TEMP_ADC,
BATT_SLAVE_CHG_TEMP,
BATT_SLAVE_CHG_TEMP_ADC,
BATT_VF_ADC,
BATT_SLATE_MODE,
BATT_LP_CHARGING,
SIOP_ACTIVATED,
SIOP_LEVEL,
SIOP_EVENT,
BATT_CHARGING_SOURCE,
FG_REG_DUMP,
FG_RESET_CAP,
FG_CAPACITY,
FG_ASOC,
AUTH,
CHG_CURRENT_ADC,
WC_ADC,
WC_STATUS,
WC_ENABLE,
WC_CONTROL,
HV_CHARGER_STATUS,
HV_WC_CHARGER_STATUS,
HV_CHARGER_SET,
FACTORY_MODE,
STORE_MODE,
UPDATE,
TEST_MODE,
BATT_EVENT_CALL,
BATT_EVENT_2G_CALL,
BATT_EVENT_TALK_GSM,
BATT_EVENT_3G_CALL,
BATT_EVENT_TALK_WCDMA,
BATT_EVENT_MUSIC,
BATT_EVENT_VIDEO,
BATT_EVENT_BROWSER,
BATT_EVENT_HOTSPOT,
BATT_EVENT_CAMERA,
BATT_EVENT_CAMCORDER,
BATT_EVENT_DATA_CALL,
BATT_EVENT_WIFI,
BATT_EVENT_WIBRO,
BATT_EVENT_LTE,
BATT_EVENT_LCD,
BATT_EVENT_GPS,
BATT_EVENT,
BATT_TEMP_TABLE,
BATT_HIGH_CURRENT_USB,
#if defined(CONFIG_SAMSUNG_BATTERY_ENG_TEST)
BATT_TEST_CHARGE_CURRENT,
#endif
BATT_STABILITY_TEST,
BATT_CAPACITY_MAX,
BATT_INBAT_VOLTAGE,
#if defined(CONFIG_BATTERY_SWELLING_SELF_DISCHARGING)
BATT_DISCHARGING_CHECK,
BATT_DISCHARGING_CHECK_ADC,
BATT_DISCHARGING_NTC,
BATT_DISCHARGING_NTC_ADC,
BATT_SELF_DISCHARGING_CONTROL,
#endif
#if defined(CONFIG_SW_SELF_DISCHARGING)
BATT_SW_SELF_DISCHARGING,
#endif
BATT_INBAT_WIRELESS_CS100,
HMT_TA_CONNECTED,
HMT_TA_CHARGE,
#if defined(CONFIG_BATTERY_SMART)
FG_FIRMWARE,
#endif
#if defined(CONFIG_BATTERY_AGE_FORECAST)
FG_CYCLE,
FG_FULLCAPNOM,
BATTERY_CYCLE,
#endif
FG_FULL_VOLTAGE,
BATT_WPC_TEMP,
BATT_WPC_TEMP_ADC,
#if defined(CONFIG_WIRELESS_FIRMWARE_UPDATE)
BATT_WIRELESS_FIRMWARE_UPDATE,
BATT_WIRELESS_OTP_FIRMWARE_RESULT,
BATT_WIRELESS_IC_GRADE,
BATT_WIRELESS_FIRMWARE_VER_BIN,
BATT_WIRELESS_FIRMWARE_VER,
BATT_WIRELESS_TX_FIRMWARE_RESULT,
BATT_WIRELESS_TX_FIRMWARE_VER,
BATT_TX_STATUS,
#endif
BATT_WIRELESS_VOUT,
BATT_WIRELESS_VRCT,
BATT_HV_WIRELESS_STATUS,
BATT_HV_WIRELESS_PAD_CTRL,
BATT_TUNE_FLOAT_VOLTAGE,
BATT_TUNE_INPUT_CHARGE_CURRENT,
BATT_TUNE_FAST_CHARGE_CURRENT,
BATT_TUNE_UI_TERM_CURRENT_1ST,
BATT_TUNE_UI_TERM_CURRENT_2ND,
BATT_TUNE_TEMP_HIGH_NORMAL,
BATT_TUNE_TEMP_HIGH_REC_NORMAL,
BATT_TUNE_TEMP_LOW_NORMAL,
BATT_TUNE_TEMP_LOW_REC_NORMAL,
BATT_TUNE_CHG_TEMP_HIGH,
BATT_TUNE_CHG_TEMP_REC,
BATT_TUNE_CHG_LIMMIT_CURRENT,
BATT_TUNE_COIL_TEMP_HIGH,
BATT_TUNE_COIL_TEMP_REC,
BATT_TUNE_COIL_LIMMIT_CURRENT,
#if defined(CONFIG_UPDATE_BATTERY_DATA)
BATT_UPDATE_DATA,
#endif
BATT_MISC_EVENT,
FACTORY_MODE_RELIEVE,
FACTORY_MODE_BYPASS,
BATT_WDT_CONTROL,
};
#ifdef CONFIG_OF
extern int adc_read(struct sec_battery_info *battery, int channel);
extern void adc_init(struct platform_device *pdev, struct sec_battery_info *battery);
extern void adc_exit(struct sec_battery_info *battery);
#endif
#if defined(CONFIG_STEP_CHARGING)
extern void sec_bat_reset_step_charging(struct sec_battery_info *battery);
extern void sec_step_charging_init(struct sec_battery_info *battery, struct device *dev);
extern bool sec_bat_check_step_charging(struct sec_battery_info *battery);
#endif
#if defined(CONFIG_UPDATE_BATTERY_DATA)
extern int sec_battery_update_data(const char* file_path);
#endif
#endif /* __SEC_BATTERY_H */

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/*
* sec_charger.h
* Samsung Mobile Charger Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SEC_CHARGER_H
#define __SEC_CHARGER_H __FILE__
#include <linux/battery/sec_charging_common.h>
#if defined(CONFIG_CHARGER_DUMMY) || \
defined(CONFIG_CHARGER_PM8917)
#include <linux/battery/charger/dummy_charger.h>
#elif defined(CONFIG_CHARGER_MAX8903)
#include <linux/battery/charger/max8903_charger.h>
#elif defined(CONFIG_CHARGER_SMB328)
#include <linux/battery/charger/smb328_charger.h>
#elif defined(CONFIG_CHARGER_SMB347)
#include <linux/battery/charger/smb347_charger.h>
#elif defined(CONFIG_CHARGER_SMB358)
#include <linux/battery/charger/smb358_charger.h>
#elif defined(CONFIG_CHARGER_BQ24157)
#include <linux/battery/charger/bq24157_charger.h>
#elif defined(CONFIG_CHARGER_BQ24190) || \
defined(CONFIG_CHARGER_BQ24191)
#include <linux/battery/charger/bq24190_charger.h>
#elif defined(CONFIG_CHARGER_BQ24260)
#include <linux/battery/charger/bq24260_charger.h>
#elif defined(CONFIG_CHARGER_MAX77803)
#include <linux/battery/charger/max77803_charger.h>
#elif defined(CONFIG_CHARGER_MAX77804)
#include <linux/battery/charger/max77804_charger.h>
#elif defined(CONFIG_CHARGER_MAX77823)
#include <linux/battery/charger/max77823_charger.h>
#elif defined(CONFIG_CHARGER_MAX77833)
#include <linux/battery/charger/max77833_charger.h>
#elif defined(CONFIG_CHARGER_MAX77843)
#include <linux/battery/charger/max77843_charger.h>
#elif defined(CONFIG_CHARGER_MAX77888)
#include <linux/battery/charger/max77888_charger.h>
#elif defined(CONFIG_CHARGER_MAX77693)
#include <linux/battery/charger/max77693_charger.h>
#elif defined(CONFIG_CHARGER_NCP1851)
#include <linux/battery/charger/ncp1851_charger.h>
#endif
enum {
CHIP_ID = 0,
};
struct sec_charger_info {
struct i2c_client *client;
sec_battery_platform_data_t *pdata;
struct power_supply psy_chg;
struct delayed_work isr_work;
int cable_type;
int status;
bool is_charging;
/* charging current : + charging, - OTG */
int charging_current;
unsigned charging_current_max;
/* register programming */
int reg_addr;
int reg_data;
int irq_base;
};
bool sec_hal_chg_init(struct i2c_client *);
bool sec_hal_chg_suspend(struct i2c_client *);
bool sec_hal_chg_shutdown(struct i2c_client *);
bool sec_hal_chg_resume(struct i2c_client *);
bool sec_hal_chg_get_property(struct i2c_client *,
enum power_supply_property,
union power_supply_propval *);
bool sec_hal_chg_set_property(struct i2c_client *,
enum power_supply_property,
const union power_supply_propval *);
ssize_t sec_hal_chg_show_attrs(struct device *dev,
const ptrdiff_t offset, char *buf);
ssize_t sec_hal_chg_store_attrs(struct device *dev,
const ptrdiff_t offset,
const char *buf, size_t count);
ssize_t sec_chg_show_attrs(struct device *dev,
struct device_attribute *attr, char *buf);
ssize_t sec_chg_store_attrs(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#define SEC_CHARGER_ATTR(_name) \
{ \
.attr = {.name = #_name, .mode = 0664}, \
.show = sec_chg_show_attrs, \
.store = sec_chg_store_attrs, \
}
enum {
CHG_REG = 0,
CHG_DATA,
CHG_REGS,
};
extern sec_battery_platform_data_t sec_battery_pdata;
#endif /* __SEC_CHARGER_H */

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/*
* sec_charging_common.h
* Samsung Mobile Charging Common Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SEC_CHARGING_COMMON_H
#define __SEC_CHARGING_COMMON_H __FILE__
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/power_supply.h>
#include <linux/slab.h>
#include <linux/device.h>
/* definitions */
#define SEC_SIZEOF_POWER_SUPPLY_TYPE POWER_SUPPLY_TYPE_MAX
enum sec_battery_voltage_mode {
/* average voltage */
SEC_BATTERY_VOLTAGE_AVERAGE = 0,
/* open circuit voltage */
SEC_BATTERY_VOLTAGE_OCV,
};
enum sec_battery_current_mode {
/* uA */
SEC_BATTERY_CURRENT_UA = 0,
/* mA */
SEC_BATTERY_CURRENT_MA,
};
enum sec_battery_capacity_mode {
/* designed capacity */
SEC_BATTERY_CAPACITY_DESIGNED = 0,
/* absolute capacity by fuel gauge */
SEC_BATTERY_CAPACITY_ABSOLUTE,
/* temperary capacity in the time */
SEC_BATTERY_CAPACITY_TEMPERARY,
/* current capacity now */
SEC_BATTERY_CAPACITY_CURRENT,
/* cell aging information */
SEC_BATTERY_CAPACITY_AGEDCELL,
/* charge count */
SEC_BATTERY_CAPACITY_CYCLE,
};
enum sec_wireless_info_mode {
SEC_WIRELESS_OTP_FIRM_RESULT = 0,
SEC_WIRELESS_IC_GRADE,
SEC_WIRELESS_IC_REVISION,
SEC_WIRELESS_OTP_FIRM_VER_BIN,
SEC_WIRELESS_OTP_FIRM_VER,
SEC_WIRELESS_TX_FIRM_RESULT,
SEC_WIRELESS_TX_FIRM_VER,
SEC_TX_FIRMWARE,
SEC_WIRELESS_OTP_FIRM_VERIFY,
};
enum sec_wireless_firm_update_mode {
SEC_WIRELESS_RX_SDCARD_MODE = 0,
SEC_WIRELESS_RX_BUILT_IN_MODE,
SEC_WIRELESS_TX_ON_MODE,
SEC_WIRELESS_TX_OFF_MODE,
SEC_WIRELESS_RX_INIT,
};
enum sec_tx_firmware_mode {
SEC_TX_OFF = 0,
SEC_TX_STANDBY,
SEC_TX_POWER_TRANSFER,
SEC_TX_ERROR,
};
enum sec_wireless_control_mode {
WIRELESS_VOUT_OFF = 0,
WIRELESS_VOUT_NORMAL_VOLTAGE, /* 5V , reserved by factory */
WIRELESS_VOUT_RESERVED, /* 6V */
WIRELESS_VOUT_HIGH_VOLTAGE, /* 9V , reserved by factory */
WIRELESS_VOUT_CC_CV_VOUT,
WIRELESS_VOUT_CV_CALL,
WIRELESS_VOUT_CC_CALL,
WIRELESS_VOUT_5V,
WIRELESS_VOUT_9V,
WIRELESS_VOUT_9V_OTG,
WIRELESS_PAD_FAN_OFF,
WIRELESS_PAD_FAN_ON,
WIRELESS_PAD_LED_OFF,
WIRELESS_PAD_LED_ON,
WIRELESS_VRECT_ADJ_ON,
WIRELESS_VRECT_ADJ_OFF,
WIRELESS_VRECT_ADJ_ROOM_0,
WIRELESS_VRECT_ADJ_ROOM_1,
WIRELESS_VRECT_ADJ_ROOM_2,
WIRELESS_VRECT_ADJ_ROOM_3,
WIRELESS_VRECT_ADJ_ROOM_4,
WIRELESS_VRECT_ADJ_ROOM_5,
WIRELESS_CLAMP_ENABLE,
};
enum sec_siop_event_mode {
SIOP_EVENT_IDLE = 0,
SIOP_EVENT_WPC_CALL_START, /* 5V wireless charging + Call */
SIOP_EVENT_WPC_CALL_END, /* 5V wireless charging + Call */
SIOP_EVENT_MAX, /* end */
};
enum sec_wireless_pad_mode {
SEC_WIRELESS_PAD_NONE = 0,
SEC_WIRELESS_PAD_WPC,
SEC_WIRELESS_PAD_WPC_PACK,
SEC_WIRELESS_PAD_WPC_PACK_TA,
SEC_WIRELESS_PAD_WPC_HV,
SEC_WIRELESS_PAD_PMA,
};
/* ADC type */
enum sec_battery_adc_type {
/* NOT using this ADC channel */
SEC_BATTERY_ADC_TYPE_NONE = 0,
/* ADC in AP */
SEC_BATTERY_ADC_TYPE_AP,
/* ADC by additional IC */
SEC_BATTERY_ADC_TYPE_IC,
SEC_BATTERY_ADC_TYPE_NUM
};
enum sec_battery_adc_channel {
SEC_BAT_ADC_CHANNEL_CABLE_CHECK = 0,
SEC_BAT_ADC_CHANNEL_BAT_CHECK,
SEC_BAT_ADC_CHANNEL_TEMP,
SEC_BAT_ADC_CHANNEL_TEMP_AMBIENT,
SEC_BAT_ADC_CHANNEL_FULL_CHECK,
SEC_BAT_ADC_CHANNEL_VOLTAGE_NOW,
SEC_BAT_ADC_CHANNEL_CHG_TEMP,
SEC_BAT_ADC_CHANNEL_INBAT_VOLTAGE,
SEC_BAT_ADC_CHANNEL_DISCHARGING_CHECK,
SEC_BAT_ADC_CHANNEL_DISCHARGING_NTC,
SEC_BAT_ADC_CHANNEL_WPC_TEMP,
SEC_BAT_ADC_CHANNEL_SLAVE_CHG_TEMP,
SEC_BAT_ADC_CHANNEL_NUM,
};
enum sec_battery_charge_mode {
SEC_BAT_CHG_MODE_CHARGING = 0,
SEC_BAT_CHG_MODE_CHARGING_OFF,
SEC_BAT_CHG_MODE_BUCK_OFF,
};
/* charging mode */
enum sec_battery_charging_mode {
/* no charging */
SEC_BATTERY_CHARGING_NONE = 0,
/* 1st charging */
SEC_BATTERY_CHARGING_1ST,
/* 2nd charging */
SEC_BATTERY_CHARGING_2ND,
/* recharging */
SEC_BATTERY_CHARGING_RECHARGING,
};
/* chg_temp state */
enum sec_battery_chg_temp_state {
SEC_BATTERY_CHG_TEMP_NONE = 0,
SEC_BATTERY_CHG_TEMP_HIGH_1ST,
SEC_BATTERY_CHG_TEMP_HIGH_2ND,
};
/* pad_limit state */
enum sec_battery_wpc_pad_state {
SEC_BATTERY_WPC_TEMP_NONE = 0,
SEC_BATTERY_WPC_TEMP_HIGH,
};
/* heat_limit state */
enum sec_battery_wc_heat_state {
SEC_BATTERY_WC_HEAT_NONE = 0, /* (9V, 1A), (9V, 600mA) */
SEC_BATTERY_WC_HEAT_HIGH, /* (5V, 400mA) */
};
struct sec_bat_adc_api {
bool (*init)(struct platform_device *);
bool (*exit)(void);
int (*read)(unsigned int);
};
#define sec_bat_adc_api_t struct sec_bat_adc_api
/* monitor activation */
enum sec_battery_polling_time_type {
/* same order with power supply status */
SEC_BATTERY_POLLING_TIME_BASIC = 0,
SEC_BATTERY_POLLING_TIME_CHARGING,
SEC_BATTERY_POLLING_TIME_DISCHARGING,
SEC_BATTERY_POLLING_TIME_NOT_CHARGING,
SEC_BATTERY_POLLING_TIME_SLEEP,
};
enum sec_battery_monitor_polling {
/* polling work queue */
SEC_BATTERY_MONITOR_WORKQUEUE,
/* alarm polling */
SEC_BATTERY_MONITOR_ALARM,
/* timer polling (NOT USE) */
SEC_BATTERY_MONITOR_TIMER,
};
#define sec_battery_monitor_polling_t \
enum sec_battery_monitor_polling
/* full charged check : POWER_SUPPLY_PROP_STATUS */
enum sec_battery_full_charged {
SEC_BATTERY_FULLCHARGED_NONE = 0,
/* current check by ADC */
SEC_BATTERY_FULLCHARGED_ADC,
/* fuel gauge current check */
SEC_BATTERY_FULLCHARGED_FG_CURRENT,
/* time check */
SEC_BATTERY_FULLCHARGED_TIME,
/* SOC check */
SEC_BATTERY_FULLCHARGED_SOC,
/* charger GPIO, NO additional full condition */
SEC_BATTERY_FULLCHARGED_CHGGPIO,
/* charger interrupt, NO additional full condition */
SEC_BATTERY_FULLCHARGED_CHGINT,
/* charger power supply property, NO additional full condition */
SEC_BATTERY_FULLCHARGED_CHGPSY,
SEC_BATTERY_FULLCHARGED_SMART_FG,
};
/* Self discharger type */
enum sec_battery_discharger_type {
/* type ADC */
SEC_BAT_SELF_DISCHARGING_BY_ADC = 0,
/* type Fuel Gauge */
SEC_BAT_SELF_DISCHARGING_BY_FG,
/* type Charger */
SEC_BAT_SELF_DISCHARGING_BY_CHG,
};
#define sec_battery_full_charged_t \
enum sec_battery_full_charged
/* full check condition type (can be used overlapped) */
#define sec_battery_full_condition_t unsigned int
/* SEC_BATTERY_FULL_CONDITION_NOTIMEFULL
* full-charged by absolute-timer only in high voltage
*/
#define SEC_BATTERY_FULL_CONDITION_NOTIMEFULL 1
/* SEC_BATTERY_FULL_CONDITION_NOSLEEPINFULL
* do not set polling time as sleep polling time in full-charged
*/
#define SEC_BATTERY_FULL_CONDITION_NOSLEEPINFULL 2
/* SEC_BATTERY_FULL_CONDITION_SOC
* use capacity for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_SOC 4
/* SEC_BATTERY_FULL_CONDITION_VCELL
* use VCELL for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_VCELL 8
/* SEC_BATTERY_FULL_CONDITION_AVGVCELL
* use average VCELL for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_AVGVCELL 16
/* SEC_BATTERY_FULL_CONDITION_OCV
* use OCV for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_OCV 32
/* recharge check condition type (can be used overlapped) */
#define sec_battery_recharge_condition_t unsigned int
/* SEC_BATTERY_RECHARGE_CONDITION_SOC
* use capacity for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_SOC 1
/* SEC_BATTERY_RECHARGE_CONDITION_AVGVCELL
* use average VCELL for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_AVGVCELL 2
/* SEC_BATTERY_RECHARGE_CONDITION_VCELL
* use VCELL for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_VCELL 4
/* battery check : POWER_SUPPLY_PROP_PRESENT */
enum sec_battery_check {
/* No Check for internal battery */
SEC_BATTERY_CHECK_NONE,
/* by ADC */
SEC_BATTERY_CHECK_ADC,
/* by callback function (battery certification by 1 wired)*/
SEC_BATTERY_CHECK_CALLBACK,
/* by PMIC */
SEC_BATTERY_CHECK_PMIC,
/* by fuel gauge */
SEC_BATTERY_CHECK_FUELGAUGE,
/* by charger */
SEC_BATTERY_CHECK_CHARGER,
/* by interrupt (use check_battery_callback() to check battery) */
SEC_BATTERY_CHECK_INT,
};
#define sec_battery_check_t \
enum sec_battery_check
/* OVP, UVLO check : POWER_SUPPLY_PROP_HEALTH */
enum sec_battery_ovp_uvlo {
/* by callback function */
SEC_BATTERY_OVP_UVLO_CALLBACK,
/* by PMIC polling */
SEC_BATTERY_OVP_UVLO_PMICPOLLING,
/* by PMIC interrupt */
SEC_BATTERY_OVP_UVLO_PMICINT,
/* by charger polling */
SEC_BATTERY_OVP_UVLO_CHGPOLLING,
/* by charger interrupt */
SEC_BATTERY_OVP_UVLO_CHGINT,
};
#define sec_battery_ovp_uvlo_t \
enum sec_battery_ovp_uvlo
/* thermal source */
enum sec_battery_thermal_source {
/* by fuel gauge */
SEC_BATTERY_THERMAL_SOURCE_FG,
/* by external source */
SEC_BATTERY_THERMAL_SOURCE_CALLBACK,
/* by ADC */
SEC_BATTERY_THERMAL_SOURCE_ADC,
};
#define sec_battery_thermal_source_t \
enum sec_battery_thermal_source
/* temperature check type */
enum sec_battery_temp_check {
SEC_BATTERY_TEMP_CHECK_NONE = 0, /* no temperature check */
SEC_BATTERY_TEMP_CHECK_ADC, /* by ADC value */
SEC_BATTERY_TEMP_CHECK_TEMP, /* by temperature */
};
#define sec_battery_temp_check_t \
enum sec_battery_temp_check
/* cable check (can be used overlapped) */
#define sec_battery_cable_check_t unsigned int
/* SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE
* for USB cable in tablet model,
* status is stuck into discharging,
* but internal charging logic is working
*/
#define SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE 1
/* SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE
* for incompatible charger
* (Not compliant to USB specification,
* cable type is POWER_SUPPLY_TYPE_UNKNOWN),
* do NOT charge and show message to user
* (only for VZW)
*/
#define SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE 2
/* SEC_BATTERY_CABLE_CHECK_PSY
* check cable by power supply set_property
*/
#define SEC_BATTERY_CABLE_CHECK_PSY 4
/* SEC_BATTERY_CABLE_CHECK_INT
* check cable by interrupt
*/
#define SEC_BATTERY_CABLE_CHECK_INT 8
/* SEC_BATTERY_CABLE_CHECK_CHGINT
* check cable by charger interrupt
*/
#define SEC_BATTERY_CABLE_CHECK_CHGINT 16
/* SEC_BATTERY_CABLE_CHECK_POLLING
* check cable by GPIO polling
*/
#define SEC_BATTERY_CABLE_CHECK_POLLING 32
/* check cable source (can be used overlapped) */
#define sec_battery_cable_source_t unsigned int
/* SEC_BATTERY_CABLE_SOURCE_EXTERNAL
* already given by external argument
*/
#define SEC_BATTERY_CABLE_SOURCE_EXTERNAL 1
/* SEC_BATTERY_CABLE_SOURCE_CALLBACK
* by callback (MUIC, USB switch)
*/
#define SEC_BATTERY_CABLE_SOURCE_CALLBACK 2
/* SEC_BATTERY_CABLE_SOURCE_ADC
* by ADC
*/
#define SEC_BATTERY_CABLE_SOURCE_ADC 4
/* capacity calculation type (can be used overlapped) */
#define sec_fuelgauge_capacity_type_t int
/* SEC_FUELGAUGE_CAPACITY_TYPE_RESET
* use capacity information to reset fuel gauge
* (only for driver algorithm, can NOT be set by user)
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_RESET (-1)
/* SEC_FUELGAUGE_CAPACITY_TYPE_RAW
* use capacity information from fuel gauge directly
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_RAW 1
/* SEC_FUELGAUGE_CAPACITY_TYPE_SCALE
* rescale capacity by scaling, need min and max value for scaling
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_SCALE 2
/* SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE
* change only maximum capacity dynamically
* to keep time for every SOC unit
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE 4
/* SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC
* change capacity value by only -1 or +1
* no sudden change of capacity
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC 8
/* SEC_FUELGAUGE_CAPACITY_TYPE_SKIP_ABNORMAL
* skip current capacity value
* if it is abnormal value
*/
#define SEC_FUELGAUGE_CAPACITY_TYPE_SKIP_ABNORMAL 16
/* charger function settings (can be used overlapped) */
#define sec_charger_functions_t unsigned int
/* SEC_CHARGER_NO_GRADUAL_CHARGING_CURRENT
* disable gradual charging current setting
* SUMMIT:AICL, MAXIM:regulation loop
*/
#define SEC_CHARGER_NO_GRADUAL_CHARGING_CURRENT 1
/* SEC_CHARGER_MINIMUM_SIOP_CHARGING_CURRENT
* charging current should be over than USB charging current
*/
#define SEC_CHARGER_MINIMUM_SIOP_CHARGING_CURRENT 2
/**
* struct sec_bat_adc_table_data - adc to temperature table for sec battery
* driver
* @adc: adc value
* @temperature: temperature(C) * 10
*/
struct sec_bat_adc_table_data {
int adc;
int data;
};
#define sec_bat_adc_table_data_t \
struct sec_bat_adc_table_data
struct sec_bat_adc_region {
int min;
int max;
};
#define sec_bat_adc_region_t \
struct sec_bat_adc_region
struct sec_charging_current {
#ifdef CONFIG_OF
unsigned int input_current_limit;
unsigned int fast_charging_current;
unsigned int full_check_current_1st;
unsigned int full_check_current_2nd;
#else
int input_current_limit;
int fast_charging_current;
int full_check_current_1st;
int full_check_current_2nd;
#endif
};
#define sec_charging_current_t \
struct sec_charging_current
#if defined(CONFIG_BATTERY_AGE_FORECAST)
struct sec_age_data {
unsigned int cycle;
unsigned int float_voltage;
unsigned int recharge_condition_vcell;
unsigned int full_condition_vcell;
unsigned int full_condition_soc;
};
#define sec_age_data_t \
struct sec_age_data
#endif
struct sec_battery_platform_data {
/* NO NEED TO BE CHANGED */
/* callback functions */
void (*initial_check)(void);
void (*monitor_additional_check)(void);
bool (*bat_gpio_init)(void);
bool (*fg_gpio_init)(void);
bool (*chg_gpio_init)(void);
bool (*is_lpm)(void);
bool (*check_jig_status) (void);
bool (*is_interrupt_cable_check_possible)(int);
int (*check_cable_callback)(void);
int (*get_cable_from_extended_cable_type)(int);
bool (*cable_switch_check)(void);
bool (*cable_switch_normal)(void);
bool (*check_cable_result_callback)(int);
bool (*check_battery_callback)(void);
bool (*check_battery_result_callback)(void);
int (*ovp_uvlo_callback)(void);
bool (*ovp_uvlo_result_callback)(int);
bool (*fuelalert_process)(bool);
bool (*get_temperature_callback)(
enum power_supply_property,
union power_supply_propval*);
/* ADC API for each ADC type */
sec_bat_adc_api_t adc_api[SEC_BATTERY_ADC_TYPE_NUM];
/* ADC region by power supply type
* ADC region should be exclusive
*/
sec_bat_adc_region_t *cable_adc_value;
/* charging current for type (0: not use) */
sec_charging_current_t *charging_current;
#ifdef CONFIG_OF
unsigned int *polling_time;
char *chip_vendor;
unsigned int temp_adc_type;
#else
int *polling_time;
#endif
/* NO NEED TO BE CHANGED */
unsigned int pre_afc_input_current;
unsigned int pre_wc_afc_input_current;
unsigned int store_mode_afc_input_current;
unsigned int store_mode_hv_wireless_input_current;
char *pmic_name;
/* battery */
char *vendor;
int technology;
int battery_type;
void *battery_data;
int bat_gpio_ta_nconnected;
/* 1 : active high, 0 : active low */
int bat_polarity_ta_nconnected;
int bat_irq;
int bat_irq_gpio;
unsigned int bat_irq_attr;
int jig_irq;
unsigned long jig_irq_attr;
sec_battery_cable_check_t cable_check_type;
sec_battery_cable_source_t cable_source_type;
bool use_LED; /* use charging LED */
/* flag for skipping the swelling mode */
bool swelling_mode_skip_in_high_temp;
/* sustaining event after deactivated (second) */
unsigned int event_waiting_time;
/* battery swelling */
int swelling_high_temp_block;
int swelling_high_temp_recov;
int swelling_low_temp_block;
int swelling_low_temp_recov;
int swelling_low_temp_additional;
unsigned int swelling_low_temp_current;
unsigned int swelling_low_temp_topoff;
unsigned int swelling_high_temp_current;
unsigned int swelling_low_temp_additional_current;
unsigned int swelling_high_temp_topoff;
unsigned int swelling_normal_float_voltage;
unsigned int swelling_drop_float_voltage;
unsigned int swelling_high_rechg_voltage;
unsigned int swelling_low_rechg_voltage;
#if defined(CONFIG_CALC_TIME_TO_FULL)
unsigned int ttf_hv_charge_current;
unsigned int ttf_hv_wireless_charge_current;
#endif
#if defined(CONFIG_STEP_CHARGING)
/* step charging */
unsigned int *step_charging_condition;
unsigned int *step_charging_current;
#endif
/* self discharging */
bool self_discharging_en;
unsigned int discharging_adc_max;
unsigned int discharging_adc_min;
unsigned int self_discharging_voltage_limit;
unsigned int discharging_ntc_limit;
int force_discharging_limit;
int force_discharging_recov;
int factory_discharging;
unsigned int self_discharging_type;
#if defined(CONFIG_SW_SELF_DISCHARGING)
/* sw self discharging */
int self_discharging_temp_block;
int self_discharging_volt_block;
int self_discharging_temp_recov;
int self_discharging_temp_pollingtime;
#endif
/* Monitor setting */
sec_battery_monitor_polling_t polling_type;
/* for initial check */
unsigned int monitor_initial_count;
/* Battery check */
sec_battery_check_t battery_check_type;
/* how many times do we need to check battery */
unsigned int check_count;
/* ADC */
/* battery check ADC maximum value */
unsigned int check_adc_max;
/* battery check ADC minimum value */
unsigned int check_adc_min;
/* OVP/UVLO check */
sec_battery_ovp_uvlo_t ovp_uvlo_check_type;
sec_battery_thermal_source_t thermal_source;
/*
* inbat_adc_table
* in-battery voltage check for table models:
* To read real battery voltage with Jig cable attached,
* dedicated hw pin & conversion table of adc-voltage are required
*/
#ifdef CONFIG_OF
sec_bat_adc_table_data_t *temp_adc_table;
sec_bat_adc_table_data_t *temp_amb_adc_table;
sec_bat_adc_table_data_t *chg_temp_adc_table;
sec_bat_adc_table_data_t *wpc_temp_adc_table;
sec_bat_adc_table_data_t *slave_chg_temp_adc_table;
sec_bat_adc_table_data_t *inbat_adc_table;
#else
const sec_bat_adc_table_data_t *temp_adc_table;
const sec_bat_adc_table_data_t *temp_amb_adc_table;
#endif
unsigned int temp_adc_table_size;
unsigned int temp_amb_adc_table_size;
unsigned int chg_temp_adc_table_size;
unsigned int wpc_temp_adc_table_size;
unsigned int slave_chg_temp_adc_table_size;
unsigned int inbat_adc_table_size;
sec_battery_temp_check_t temp_check_type;
unsigned int temp_check_count;
unsigned int chg_temp_check; /* Control the charging current depending on the chg_thm */
unsigned int chg_thermal_source; /* To confirm the charger temperature */
unsigned int wpc_temp_check;
unsigned int wpc_thermal_source; /* To confirm the wpc temperature */
unsigned int slave_chg_temp_check;
unsigned int slave_thermal_source; /* To confirm the slave charger temperature */
unsigned int inbat_voltage;
/*
* limit can be ADC value or Temperature
* depending on temp_check_type
* temperature should be temp x 10 (0.1 degree)
*/
int temp_highlimit_threshold_normal;
int temp_highlimit_recovery_normal;
int temp_high_threshold_normal;
int temp_high_recovery_normal;
int temp_low_threshold_normal;
int temp_low_recovery_normal;
int temp_highlimit_threshold_lpm;
int temp_highlimit_recovery_lpm;
int temp_high_threshold_lpm;
int temp_high_recovery_lpm;
int temp_low_threshold_lpm;
int temp_low_recovery_lpm;
int chg_high_temp_1st;
int chg_high_temp_2nd;
int chg_high_temp_recovery;
unsigned int chg_charging_limit_current;
unsigned int chg_charging_limit_current_2nd;
unsigned int chg_skip_check_time;
unsigned int chg_skip_check_capacity;
int wpc_high_temp;
int wpc_high_temp_recovery;
int wpc_heat_temp_recovery;
int wpc_lcd_on_high_temp;
int wpc_lcd_on_high_temp_rec;
unsigned int wpc_hv_lcd_on_input_limit_current;
unsigned int wpc_charging_limit_current;
unsigned int sleep_mode_limit_current;
unsigned int wc_full_input_limit_current;
unsigned int wc_heating_input_limit_current;
unsigned int wc_heating_time;
unsigned int wc_cv_current;
unsigned int wpc_skip_check_time;
unsigned int wpc_skip_check_capacity;
/* If these is NOT full check type or NONE full check type,
* it is skipped
*/
/* 1st full check */
sec_battery_full_charged_t full_check_type;
/* 2nd full check */
sec_battery_full_charged_t full_check_type_2nd;
unsigned int full_check_count;
int chg_gpio_full_check;
/* 1 : active high, 0 : active low */
int chg_polarity_full_check;
sec_battery_full_condition_t full_condition_type;
unsigned int full_condition_soc;
unsigned int full_condition_vcell;
unsigned int full_condition_avgvcell;
unsigned int full_condition_ocv;
unsigned int recharge_check_count;
sec_battery_recharge_condition_t recharge_condition_type;
unsigned int recharge_condition_soc;
unsigned int recharge_condition_avgvcell;
unsigned int recharge_condition_vcell;
/* for absolute timer (second) */
unsigned long charging_total_time;
/* for recharging timer (second) */
unsigned long recharging_total_time;
/* reset charging for abnormal malfunction (0: not use) */
unsigned long charging_reset_time;
/* fuel gauge */
char *fuelgauge_name;
int fg_irq;
unsigned long fg_irq_attr;
/* fuel alert SOC (-1: not use) */
int fuel_alert_soc;
/* fuel alert can be repeated */
bool repeated_fuelalert;
sec_fuelgauge_capacity_type_t capacity_calculation_type;
/* soc should be soc x 10 (0.1% degree)
* only for scaling
*/
int capacity_max;
int capacity_max_hv;
int capacity_max_margin;
int capacity_min;
/* charger */
char *charger_name;
char *fgsrc_switch_name;
bool support_fgsrc_change;
/* wireless charger */
char *wireless_charger_name;
int wireless_cc_cv;
int wpc_det;
int wpc_en;
int chg_gpio_en;
/* 1 : active high, 0 : active low */
int chg_polarity_en;
int chg_gpio_curr_adj;
/* 1 : active high, 0 : active low */
int chg_polarity_curr_adj;
int chg_gpio_status;
/* 1 : active high, 0 : active low */
int chg_polarity_status;
int chg_irq;
unsigned long chg_irq_attr;
/* float voltage (mV) */
#ifdef CONFIG_OF
unsigned int chg_float_voltage;
#else
int chg_float_voltage;
#endif
#if defined(CONFIG_BATTERY_AGE_FORECAST)
int num_age_step;
int age_step;
int age_data_length;
sec_age_data_t* age_data;
#endif
unsigned int siop_event_check_type;
unsigned int siop_call_cc_current;
unsigned int siop_call_cv_current;
int siop_input_limit_current;
int siop_charging_limit_current;
int siop_hv_input_limit_current;
int siop_hv_charging_limit_current;
int siop_wireless_input_limit_current;
int siop_wireless_charging_limit_current;
int siop_hv_wireless_input_limit_current;
int siop_hv_wireless_charging_limit_current;
sec_charger_functions_t chg_functions_setting;
bool fake_capacity;
bool always_enable;
bool chg_eoc_dualpath;
/* ADC setting */
unsigned int adc_check_count;
/* ADC type for each channel */
unsigned int adc_type[];
};
struct sec_charger_platform_data {
bool (*chg_gpio_init)(void);
/* charging current for type (0: not use) */
sec_charging_current_t *charging_current;
/* wirelss charger */
char *wireless_charger_name;
int wireless_cc_cv;
int vbus_ctrl_gpio;
int chg_gpio_en;
/* 1 : active high, 0 : active low */
int chg_polarity_en;
/* float voltage (mV) */
int chg_float_voltage;
int irq_gpio;
int chg_irq;
unsigned long chg_irq_attr;
bool support_slow_charging;
/* otg_en setting */
int otg_en;
/* OVP/UVLO check */
sec_battery_ovp_uvlo_t ovp_uvlo_check_type;
/* 1st full check */
sec_battery_full_charged_t full_check_type;
/* 2nd full check */
sec_battery_full_charged_t full_check_type_2nd;
sec_charger_functions_t chg_functions_setting;
};
struct sec_fuelgauge_platform_data {
bool (*fg_gpio_init)(void);
bool (*check_jig_status)(void);
int (*check_cable_callback)(void);
bool (*fuelalert_process)(bool);
/* charging current for type (0: not use) */
sec_charging_current_t *charging_current;
int jig_irq;
int jig_gpio;
unsigned long jig_irq_attr;
sec_battery_thermal_source_t thermal_source;
int fg_irq;
unsigned long fg_irq_attr;
/* fuel alert SOC (-1: not use) */
int fuel_alert_soc;
int fuel_alert_vol;
/* fuel alert can be repeated */
bool repeated_fuelalert;
sec_fuelgauge_capacity_type_t capacity_calculation_type;
/* soc should be soc x 10 (0.1% degree)
* only for scaling
*/
int capacity_max;
int capacity_max_hv;
int capacity_max_margin;
int capacity_min;
int rcomp0;
int rcomp_charging;
#if defined(CONFIG_BATTERY_AGE_FORECAST)
unsigned int full_condition_soc;
#endif
};
#define sec_battery_platform_data_t \
struct sec_battery_platform_data
#define sec_charger_platform_data_t \
struct sec_charger_platform_data
#define sec_fuelgauge_platform_data_t \
struct sec_fuelgauge_platform_data
static inline struct power_supply *get_power_supply_by_name(char *name)
{
if (!name)
return (struct power_supply *)NULL;
else
return power_supply_get_by_name(name);
}
#define psy_do_property(name, function, property, value) \
{ \
struct power_supply *psy; \
int ret; \
psy = get_power_supply_by_name((name)); \
if (!psy) { \
pr_err("%s: Fail to "#function" psy (%s)\n", \
__func__, (name)); \
value.intval = 0; \
} else { \
if (psy->function##_property != NULL) { \
ret = psy->function##_property(psy, (property), &(value)); \
if (ret < 0) { \
pr_err("%s: Fail to %s "#function" (%d=>%d)\n", \
__func__, name, (property), ret); \
value.intval = 0; \
} \
} \
} \
}
#ifndef CONFIG_OF
#define adc_init(pdev, pdata, channel) \
(((pdata)->adc_api)[((((pdata)->adc_type[(channel)]) < \
SEC_BATTERY_ADC_TYPE_NUM) ? ((pdata)->adc_type[(channel)]) : \
SEC_BATTERY_ADC_TYPE_NONE)].init((pdev)))
#define adc_exit(pdata, channel) \
(((pdata)->adc_api)[((pdata)->adc_type[(channel)])].exit())
#define adc_read(pdata, channel) \
(((pdata)->adc_api)[((pdata)->adc_type[(channel)])].read((channel)))
#endif
#define get_battery_data(driver) \
(((struct battery_data_t *)(driver)->pdata->battery_data) \
[(driver)->pdata->battery_type])
#endif /* __SEC_CHARGING_COMMON_H */

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/*
* sec_fuelgauge.h
* Samsung Mobile Fuel Gauge Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SEC_FUELGAUGE_H
#define __SEC_FUELGAUGE_H __FILE__
#include <linux/battery/sec_charging_common.h>
#if defined(CONFIG_FUELGAUGE_DUMMY)
#include <linux/battery/fuelgauge/dummy_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX17042)
#include <linux/battery/fuelgauge/max17042_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX17048)
#include <linux/battery/fuelgauge/max17048_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX77823)
#include <linux/battery/fuelgauge/max77823_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX77833)
#include <linux/battery/fuelgauge/max77833_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX77843)
#include <linux/battery/fuelgauge/max77843_fuelgauge.h>
#elif defined(CONFIG_FUELGAUGE_MAX17050)
#include <linux/battery/fuelgauge/max17050_fuelgauge.h>
#endif
struct sec_fuelgauge_reg_data {
u8 reg_addr;
u8 reg_data1;
u8 reg_data2;
};
struct sec_fuelgauge_info {
struct i2c_client *client;
sec_battery_platform_data_t *pdata;
struct power_supply psy_fg;
struct delayed_work isr_work;
int cable_type;
bool is_charging;
/* HW-dedicated fuel guage info structure
* used in individual fuel gauge file only
* (ex. dummy_fuelgauge.c)
*/
struct sec_fg_info info;
bool is_fuel_alerted;
struct wake_lock fuel_alert_wake_lock;
unsigned int capacity_old; /* only for atomic calculation */
unsigned int capacity_max; /* only for dynamic calculation */
bool initial_update_of_soc;
struct mutex fg_lock;
/* register programming */
int reg_addr;
u8 reg_data[2];
int fg_irq;
};
bool sec_hal_fg_init(struct i2c_client *);
bool sec_hal_fg_suspend(struct i2c_client *);
bool sec_hal_fg_resume(struct i2c_client *);
bool sec_hal_fg_fuelalert_init(struct i2c_client *, int);
bool sec_hal_fg_is_fuelalerted(struct i2c_client *);
bool sec_hal_fg_fuelalert_process(void *, bool);
bool sec_hal_fg_full_charged(struct i2c_client *);
bool sec_hal_fg_reset(struct i2c_client *);
bool sec_hal_fg_get_property(struct i2c_client *,
enum power_supply_property,
union power_supply_propval *);
bool sec_hal_fg_set_property(struct i2c_client *,
enum power_supply_property,
const union power_supply_propval *);
ssize_t sec_hal_fg_show_attrs(struct device *dev,
const ptrdiff_t offset, char *buf);
ssize_t sec_hal_fg_store_attrs(struct device *dev,
const ptrdiff_t offset,
const char *buf, size_t count);
ssize_t sec_fg_show_attrs(struct device *dev,
struct device_attribute *attr, char *buf);
ssize_t sec_fg_store_attrs(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#define SEC_FG_ATTR(_name) \
{ \
.attr = {.name = #_name, .mode = 0664}, \
.show = sec_fg_show_attrs, \
.store = sec_fg_store_attrs, \
}
enum {
FG_REG = 0,
FG_DATA,
FG_REGS,
};
#endif /* __SEC_FUELGAUGE_H */

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#ifndef _BCD_H
#define _BCD_H
#include <linux/compiler.h>
#define bcd2bin(x) \
(__builtin_constant_p((u8 )(x)) ? \
const_bcd2bin(x) : \
_bcd2bin(x))
#define bin2bcd(x) \
(__builtin_constant_p((u8 )(x)) ? \
const_bin2bcd(x) : \
_bin2bcd(x))
#define const_bcd2bin(x) (((x) & 0x0f) + ((x) >> 4) * 10)
#define const_bin2bcd(x) ((((x) / 10) << 4) + (x) % 10)
unsigned _bcd2bin(unsigned char val) __attribute_const__;
unsigned char _bin2bcd(unsigned val) __attribute_const__;
#endif /* _BCD_H */

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/*
* Generic binary BCH encoding/decoding library
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 51
* Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Copyright © 2011 Parrot S.A.
*
* Author: Ivan Djelic <ivan.djelic@parrot.com>
*
* Description:
*
* This library provides runtime configurable encoding/decoding of binary
* Bose-Chaudhuri-Hocquenghem (BCH) codes.
*/
#ifndef _BCH_H
#define _BCH_H
#include <linux/types.h>
/**
* struct bch_control - BCH control structure
* @m: Galois field order
* @n: maximum codeword size in bits (= 2^m-1)
* @t: error correction capability in bits
* @ecc_bits: ecc exact size in bits, i.e. generator polynomial degree (<=m*t)
* @ecc_bytes: ecc max size (m*t bits) in bytes
* @a_pow_tab: Galois field GF(2^m) exponentiation lookup table
* @a_log_tab: Galois field GF(2^m) log lookup table
* @mod8_tab: remainder generator polynomial lookup tables
* @ecc_buf: ecc parity words buffer
* @ecc_buf2: ecc parity words buffer
* @xi_tab: GF(2^m) base for solving degree 2 polynomial roots
* @syn: syndrome buffer
* @cache: log-based polynomial representation buffer
* @elp: error locator polynomial
* @poly_2t: temporary polynomials of degree 2t
*/
struct bch_control {
unsigned int m;
unsigned int n;
unsigned int t;
unsigned int ecc_bits;
unsigned int ecc_bytes;
/* private: */
uint16_t *a_pow_tab;
uint16_t *a_log_tab;
uint32_t *mod8_tab;
uint32_t *ecc_buf;
uint32_t *ecc_buf2;
unsigned int *xi_tab;
unsigned int *syn;
int *cache;
struct gf_poly *elp;
struct gf_poly *poly_2t[4];
};
struct bch_control *init_bch(int m, int t, unsigned int prim_poly);
void free_bch(struct bch_control *bch);
void encode_bch(struct bch_control *bch, const uint8_t *data,
unsigned int len, uint8_t *ecc);
int decode_bch(struct bch_control *bch, const uint8_t *data, unsigned int len,
const uint8_t *recv_ecc, const uint8_t *calc_ecc,
const unsigned int *syn, unsigned int *errloc);
#endif /* _BCH_H */

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#ifndef LINUX_BCM47XX_WDT_H_
#define LINUX_BCM47XX_WDT_H_
#include <linux/notifier.h>
#include <linux/timer.h>
#include <linux/types.h>
#include <linux/watchdog.h>
struct bcm47xx_wdt {
u32 (*timer_set)(struct bcm47xx_wdt *, u32);
u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
u32 max_timer_ms;
void *driver_data;
struct watchdog_device wdd;
struct notifier_block notifier;
struct timer_list soft_timer;
atomic_t soft_ticks;
};
static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
{
return wdt->driver_data;
}
#endif /* LINUX_BCM47XX_WDT_H_ */

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#ifndef LINUX_BCMA_H_
#define LINUX_BCMA_H_
#include <linux/pci.h>
#include <linux/mod_devicetable.h>
#include <linux/bcma/bcma_driver_chipcommon.h>
#include <linux/bcma/bcma_driver_pci.h>
#include <linux/bcma/bcma_driver_pcie2.h>
#include <linux/bcma/bcma_driver_mips.h>
#include <linux/bcma/bcma_driver_gmac_cmn.h>
#include <linux/ssb/ssb.h> /* SPROM sharing */
#include <linux/bcma/bcma_regs.h>
struct bcma_device;
struct bcma_bus;
enum bcma_hosttype {
BCMA_HOSTTYPE_PCI,
BCMA_HOSTTYPE_SDIO,
BCMA_HOSTTYPE_SOC,
};
struct bcma_chipinfo {
u16 id;
u8 rev;
u8 pkg;
};
struct bcma_boardinfo {
u16 vendor;
u16 type;
};
enum bcma_clkmode {
BCMA_CLKMODE_FAST,
BCMA_CLKMODE_DYNAMIC,
};
struct bcma_host_ops {
u8 (*read8)(struct bcma_device *core, u16 offset);
u16 (*read16)(struct bcma_device *core, u16 offset);
u32 (*read32)(struct bcma_device *core, u16 offset);
void (*write8)(struct bcma_device *core, u16 offset, u8 value);
void (*write16)(struct bcma_device *core, u16 offset, u16 value);
void (*write32)(struct bcma_device *core, u16 offset, u32 value);
#ifdef CONFIG_BCMA_BLOCKIO
void (*block_read)(struct bcma_device *core, void *buffer,
size_t count, u16 offset, u8 reg_width);
void (*block_write)(struct bcma_device *core, const void *buffer,
size_t count, u16 offset, u8 reg_width);
#endif
/* Agent ops */
u32 (*aread32)(struct bcma_device *core, u16 offset);
void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
};
/* Core manufacturers */
#define BCMA_MANUF_ARM 0x43B
#define BCMA_MANUF_MIPS 0x4A7
#define BCMA_MANUF_BCM 0x4BF
/* Core class values. */
#define BCMA_CL_SIM 0x0
#define BCMA_CL_EROM 0x1
#define BCMA_CL_CORESIGHT 0x9
#define BCMA_CL_VERIF 0xB
#define BCMA_CL_OPTIMO 0xD
#define BCMA_CL_GEN 0xE
#define BCMA_CL_PRIMECELL 0xF
/* Core-ID values. */
#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
#define BCMA_CORE_4706_CHIPCOMMON 0x500
#define BCMA_CORE_NS_PCIEG2 0x501
#define BCMA_CORE_NS_DMA 0x502
#define BCMA_CORE_NS_SDIO3 0x503
#define BCMA_CORE_NS_USB20 0x504
#define BCMA_CORE_NS_USB30 0x505
#define BCMA_CORE_NS_A9JTAG 0x506
#define BCMA_CORE_NS_DDR23 0x507
#define BCMA_CORE_NS_ROM 0x508
#define BCMA_CORE_NS_NAND 0x509
#define BCMA_CORE_NS_QSPI 0x50A
#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
#define BCMA_CORE_4706_SOC_RAM 0x50E
#define BCMA_CORE_ARMCA9 0x510
#define BCMA_CORE_4706_MAC_GBIT 0x52D
#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
#define BCMA_CORE_ALTA 0x534 /* I2S core */
#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
#define BCMA_CORE_DDR23_PHY 0x5DD
#define BCMA_CORE_INVALID 0x700
#define BCMA_CORE_CHIPCOMMON 0x800
#define BCMA_CORE_ILINE20 0x801
#define BCMA_CORE_SRAM 0x802
#define BCMA_CORE_SDRAM 0x803
#define BCMA_CORE_PCI 0x804
#define BCMA_CORE_MIPS 0x805
#define BCMA_CORE_ETHERNET 0x806
#define BCMA_CORE_V90 0x807
#define BCMA_CORE_USB11_HOSTDEV 0x808
#define BCMA_CORE_ADSL 0x809
#define BCMA_CORE_ILINE100 0x80A
#define BCMA_CORE_IPSEC 0x80B
#define BCMA_CORE_UTOPIA 0x80C
#define BCMA_CORE_PCMCIA 0x80D
#define BCMA_CORE_INTERNAL_MEM 0x80E
#define BCMA_CORE_MEMC_SDRAM 0x80F
#define BCMA_CORE_OFDM 0x810
#define BCMA_CORE_EXTIF 0x811
#define BCMA_CORE_80211 0x812
#define BCMA_CORE_PHY_A 0x813
#define BCMA_CORE_PHY_B 0x814
#define BCMA_CORE_PHY_G 0x815
#define BCMA_CORE_MIPS_3302 0x816
#define BCMA_CORE_USB11_HOST 0x817
#define BCMA_CORE_USB11_DEV 0x818
#define BCMA_CORE_USB20_HOST 0x819
#define BCMA_CORE_USB20_DEV 0x81A
#define BCMA_CORE_SDIO_HOST 0x81B
#define BCMA_CORE_ROBOSWITCH 0x81C
#define BCMA_CORE_PARA_ATA 0x81D
#define BCMA_CORE_SATA_XORDMA 0x81E
#define BCMA_CORE_ETHERNET_GBIT 0x81F
#define BCMA_CORE_PCIE 0x820
#define BCMA_CORE_PHY_N 0x821
#define BCMA_CORE_SRAM_CTL 0x822
#define BCMA_CORE_MINI_MACPHY 0x823
#define BCMA_CORE_ARM_1176 0x824
#define BCMA_CORE_ARM_7TDMI 0x825
#define BCMA_CORE_PHY_LP 0x826
#define BCMA_CORE_PMU 0x827
#define BCMA_CORE_PHY_SSN 0x828
#define BCMA_CORE_SDIO_DEV 0x829
#define BCMA_CORE_ARM_CM3 0x82A
#define BCMA_CORE_PHY_HT 0x82B
#define BCMA_CORE_MIPS_74K 0x82C
#define BCMA_CORE_MAC_GBIT 0x82D
#define BCMA_CORE_DDR12_MEM_CTL 0x82E
#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
#define BCMA_CORE_SHARED_COMMON 0x831
#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
#define BCMA_CORE_SPI_HOST 0x833
#define BCMA_CORE_I2S 0x834
#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
#define BCMA_CORE_PHY_AC 0x83B
#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
#define BCMA_CORE_USB30_DEV 0x83D
#define BCMA_CORE_ARM_CR4 0x83E
#define BCMA_CORE_DEFAULT 0xFFF
#define BCMA_MAX_NR_CORES 16
/* Chip IDs of PCIe devices */
#define BCMA_CHIP_ID_BCM4313 0x4313
#define BCMA_CHIP_ID_BCM43142 43142
#define BCMA_CHIP_ID_BCM43131 43131
#define BCMA_CHIP_ID_BCM43217 43217
#define BCMA_CHIP_ID_BCM43222 43222
#define BCMA_CHIP_ID_BCM43224 43224
#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
#define BCMA_CHIP_ID_BCM43225 43225
#define BCMA_CHIP_ID_BCM43227 43227
#define BCMA_CHIP_ID_BCM43228 43228
#define BCMA_CHIP_ID_BCM43421 43421
#define BCMA_CHIP_ID_BCM43428 43428
#define BCMA_CHIP_ID_BCM43431 43431
#define BCMA_CHIP_ID_BCM43460 43460
#define BCMA_CHIP_ID_BCM4331 0x4331
#define BCMA_CHIP_ID_BCM6362 0x6362
#define BCMA_CHIP_ID_BCM4360 0x4360
#define BCMA_CHIP_ID_BCM4352 0x4352
/* Chip IDs of SoCs */
#define BCMA_CHIP_ID_BCM4706 0x5300
#define BCMA_PKG_ID_BCM4706L 1
#define BCMA_CHIP_ID_BCM4716 0x4716
#define BCMA_PKG_ID_BCM4716 8
#define BCMA_PKG_ID_BCM4717 9
#define BCMA_PKG_ID_BCM4718 10
#define BCMA_CHIP_ID_BCM47162 47162
#define BCMA_CHIP_ID_BCM4748 0x4748
#define BCMA_CHIP_ID_BCM4749 0x4749
#define BCMA_CHIP_ID_BCM5356 0x5356
#define BCMA_CHIP_ID_BCM5357 0x5357
#define BCMA_PKG_ID_BCM5358 9
#define BCMA_PKG_ID_BCM47186 10
#define BCMA_PKG_ID_BCM5357 11
#define BCMA_CHIP_ID_BCM53572 53572
#define BCMA_PKG_ID_BCM47188 9
#define BCMA_CHIP_ID_BCM4707 53010
#define BCMA_PKG_ID_BCM4707 1
#define BCMA_PKG_ID_BCM4708 2
#define BCMA_PKG_ID_BCM4709 0
#define BCMA_CHIP_ID_BCM53018 53018
/* Board types (on PCI usually equals to the subsystem dev id) */
/* BCM4313 */
#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
/* BCM4716 */
#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
/* BCM43224 */
#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
/* BCM43228 */
#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
/* BCM4331 */
#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
/* BCM53572 */
#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
/* BCM43142 */
#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
struct bcma_device {
struct bcma_bus *bus;
struct bcma_device_id id;
struct device dev;
struct device *dma_dev;
unsigned int irq;
bool dev_registered;
u8 core_index;
u8 core_unit;
u32 addr;
u32 addr_s[8];
u32 wrap;
void __iomem *io_addr;
void __iomem *io_wrap;
void *drvdata;
struct list_head list;
};
static inline void *bcma_get_drvdata(struct bcma_device *core)
{
return core->drvdata;
}
static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
{
core->drvdata = drvdata;
}
struct bcma_driver {
const char *name;
const struct bcma_device_id *id_table;
int (*probe)(struct bcma_device *dev);
void (*remove)(struct bcma_device *dev);
int (*suspend)(struct bcma_device *dev);
int (*resume)(struct bcma_device *dev);
void (*shutdown)(struct bcma_device *dev);
struct device_driver drv;
};
extern
int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
#define bcma_driver_register(drv) \
__bcma_driver_register(drv, THIS_MODULE)
extern void bcma_driver_unregister(struct bcma_driver *drv);
/* Set a fallback SPROM.
* See kdoc at the function definition for complete documentation. */
extern int bcma_arch_register_fallback_sprom(
int (*sprom_callback)(struct bcma_bus *bus,
struct ssb_sprom *out));
struct bcma_bus {
/* The MMIO area. */
void __iomem *mmio;
const struct bcma_host_ops *ops;
enum bcma_hosttype hosttype;
union {
/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
struct pci_dev *host_pci;
/* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
struct sdio_func *host_sdio;
/* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
struct platform_device *host_pdev;
};
struct bcma_chipinfo chipinfo;
struct bcma_boardinfo boardinfo;
struct bcma_device *mapped_core;
struct list_head cores;
u8 nr_cores;
u8 num;
struct bcma_drv_cc drv_cc;
struct bcma_drv_cc_b drv_cc_b;
struct bcma_drv_pci drv_pci[2];
struct bcma_drv_pcie2 drv_pcie2;
struct bcma_drv_mips drv_mips;
struct bcma_drv_gmac_cmn drv_gmac_cmn;
/* We decided to share SPROM struct with SSB as long as we do not need
* any hacks for BCMA. This simplifies drivers code. */
struct ssb_sprom sprom;
};
static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
{
return core->bus->ops->read8(core, offset);
}
static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
{
return core->bus->ops->read16(core, offset);
}
static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
{
return core->bus->ops->read32(core, offset);
}
static inline
void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
{
core->bus->ops->write8(core, offset, value);
}
static inline
void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
{
core->bus->ops->write16(core, offset, value);
}
static inline
void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
{
core->bus->ops->write32(core, offset, value);
}
#ifdef CONFIG_BCMA_BLOCKIO
static inline void bcma_block_read(struct bcma_device *core, void *buffer,
size_t count, u16 offset, u8 reg_width)
{
core->bus->ops->block_read(core, buffer, count, offset, reg_width);
}
static inline void bcma_block_write(struct bcma_device *core,
const void *buffer, size_t count,
u16 offset, u8 reg_width)
{
core->bus->ops->block_write(core, buffer, count, offset, reg_width);
}
#endif
static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
{
return core->bus->ops->aread32(core, offset);
}
static inline
void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
{
core->bus->ops->awrite32(core, offset, value);
}
static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
{
bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
}
static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
{
bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
}
static inline void bcma_maskset32(struct bcma_device *cc,
u16 offset, u32 mask, u32 set)
{
bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
}
static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
{
bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
}
static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
{
bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
}
static inline void bcma_maskset16(struct bcma_device *cc,
u16 offset, u16 mask, u16 set)
{
bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
}
extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
u8 unit);
static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
u16 coreid)
{
return bcma_find_core_unit(bus, coreid, 0);
}
extern bool bcma_core_is_enabled(struct bcma_device *core);
extern void bcma_core_disable(struct bcma_device *core, u32 flags);
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
extern void bcma_core_set_clockmode(struct bcma_device *core,
enum bcma_clkmode clkmode);
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
bool on);
extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
#define BCMA_DMA_TRANSLATION_NONE 0x00000000
#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
#define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
extern u32 bcma_core_dma_translation(struct bcma_device *core);
#endif /* LINUX_BCMA_H_ */

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#ifndef LINUX_BCMA_DRIVER_CC_H_
#define LINUX_BCMA_DRIVER_CC_H_
#include <linux/platform_device.h>
#include <linux/gpio.h>
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
#define BCMA_CC_ID_ID 0x0000FFFF
#define BCMA_CC_ID_ID_SHIFT 0
#define BCMA_CC_ID_REV 0x000F0000
#define BCMA_CC_ID_REV_SHIFT 16
#define BCMA_CC_ID_PKG 0x00F00000
#define BCMA_CC_ID_PKG_SHIFT 20
#define BCMA_CC_ID_NRCORES 0x0F000000
#define BCMA_CC_ID_NRCORES_SHIFT 24
#define BCMA_CC_ID_TYPE 0xF0000000
#define BCMA_CC_ID_TYPE_SHIFT 28
#define BCMA_CC_CAP 0x0004 /* Capabilities */
#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
#define BCMA_PLLTYPE_NONE 0x00000000
#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
#define BCMA_CC_CAP_OTPS_SHIFT 19
#define BCMA_CC_CAP_OTPS_BASE 5
#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
#define BCMA_CC_CORECTL 0x0008
#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
#define BCMA_CC_BIST 0x000C
#define BCMA_CC_OTPS 0x0010 /* OTP status */
#define BCMA_CC_OTPS_PROGFAIL 0x80000000
#define BCMA_CC_OTPS_PROTECT 0x00000007
#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
#define BCMA_CC_OTPC 0x0014 /* OTP control */
#define BCMA_CC_OTPC_RECWAIT 0xFF000000
#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
#define BCMA_CC_OTPC_PRW_SHIFT 8
#define BCMA_CC_OTPC_MAXFAIL 0x00000038
#define BCMA_CC_OTPC_VSEL 0x00000006
#define BCMA_CC_OTPC_SELVL 0x00000001
#define BCMA_CC_OTPP 0x0018 /* OTP prog */
#define BCMA_CC_OTPP_COL 0x000000FF
#define BCMA_CC_OTPP_ROW 0x0000FF00
#define BCMA_CC_OTPP_ROW_SHIFT 8
#define BCMA_CC_OTPP_READERR 0x10000000
#define BCMA_CC_OTPP_VALUE 0x20000000
#define BCMA_CC_OTPP_READ 0x40000000
#define BCMA_CC_OTPP_START 0x80000000
#define BCMA_CC_OTPP_BUSY 0x80000000
#define BCMA_CC_OTPL 0x001C /* OTP layout */
#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
#define BCMA_CC_IRQSTAT 0x0020
#define BCMA_CC_IRQMASK 0x0024
#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
#define BCMA_CC_JCMD_PAUSE 0x40000000
#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
#define BCMA_CC_JCMD0_ACC_DR 0x00001000
#define BCMA_CC_JCMD0_ACC_IR 0x00002000
#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
#define BCMA_CC_JCMD_ACC_DR 0x00010000
#define BCMA_CC_JCMD_ACC_IR 0x00020000
#define BCMA_CC_JCMD_ACC_RESET 0x00030000
#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
#define BCMA_CC_JCMD_ACC_PDR 0x00050000
#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
#define BCMA_CC_JCMD_IRW_SHIFT 8
#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
#define BCMA_CC_FLASHCTL 0x0040
/* Start/busy bit in flashcontrol */
#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
#define BCMA_CC_FLASHCTL_ACTION 0x00000700
#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
#define BCMA_CC_FLASHCTL_START 0x80000000
#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
/* Flashcontrol action + opcodes for ST flashes */
#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
/* Flashcontrol action + opcodes for Atmel flashes */
#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
#define BCMA_CC_FLASHADDR 0x0044
#define BCMA_CC_FLASHDATA 0x0048
/* Status register bits for ST flashes */
#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
/* Status register bits for Atmel flashes */
#define BCMA_CC_FLASHDATA_AT_READY 0x80
#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
#define BCMA_CC_BCAST_ADDR 0x0050
#define BCMA_CC_BCAST_DATA 0x0054
#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
#define BCMA_CC_GPIOIN 0x0060
#define BCMA_CC_GPIOOUT 0x0064
#define BCMA_CC_GPIOOUTEN 0x0068
#define BCMA_CC_GPIOCTL 0x006C
#define BCMA_CC_GPIOPOL 0x0070
#define BCMA_CC_GPIOIRQ 0x0074
#define BCMA_CC_WATCHDOG 0x0080
#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
#define BCMA_CC_CLOCK_N 0x0090
#define BCMA_CC_CLOCK_SB 0x0094
#define BCMA_CC_CLOCK_PCI 0x0098
#define BCMA_CC_CLOCK_M2 0x009C
#define BCMA_CC_CLOCK_MIPS 0x00A0
#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
#define BCMA_CC_CLKDIV_OTP 0x000F0000
#define BCMA_CC_CLKDIV_OTP_SHIFT 16
#define BCMA_CC_CLKDIV_JTAG 0x00000F00
#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
#define BCMA_CC_CLKDIV_UART 0x000000FF
#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
#define BCMA_CC_EROM 0x00FC
#define BCMA_CC_PCMCIA_CFG 0x0100
#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
#define BCMA_CC_PCMCIA_IOWAIT 0x010C
#define BCMA_CC_IDE_CFG 0x0110
#define BCMA_CC_IDE_MEMWAIT 0x0114
#define BCMA_CC_IDE_ATTRWAIT 0x0118
#define BCMA_CC_IDE_IOWAIT 0x011C
#define BCMA_CC_PROG_CFG 0x0120
#define BCMA_CC_PROG_WAITCNT 0x0124
#define BCMA_CC_FLASH_CFG 0x0128
#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
#define BCMA_CC_FLASH_WAITCNT 0x012C
#define BCMA_CC_SROM_CONTROL 0x0190
#define BCMA_CC_SROM_CONTROL_START 0x80000000
#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
/* Block 0x140 - 0x190 registers are chipset specific */
#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
/* NAND flash registers for BCM4706 (corerev = 31) */
#define BCMA_CC_NFLASH_CTL 0x01A0
#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
#define BCMA_CC_NFLASH_CONF 0x01A4
#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
#define BCMA_CC_NFLASH_DATA 0x01B0
#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
#define BCMA_CC_UART0_IMR 0x0304
#define BCMA_CC_UART0_FCR 0x0308
#define BCMA_CC_UART0_LCR 0x030C
#define BCMA_CC_UART0_MCR 0x0310
#define BCMA_CC_UART0_LSR 0x0314
#define BCMA_CC_UART0_MSR 0x0318
#define BCMA_CC_UART0_SCRATCH 0x031C
#define BCMA_CC_UART1_DATA 0x0400
#define BCMA_CC_UART1_IMR 0x0404
#define BCMA_CC_UART1_FCR 0x0408
#define BCMA_CC_UART1_LCR 0x040C
#define BCMA_CC_UART1_MCR 0x0410
#define BCMA_CC_UART1_LSR 0x0414
#define BCMA_CC_UART1_MSR 0x0418
#define BCMA_CC_UART1_SCRATCH 0x041C
/* PMU registers (rev >= 20) */
#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
#define BCMA_CC_PMU_CTL_RES_SHIFT 13
#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
#define BCMA_CC_CHIPCTL_ADDR 0x0650
#define BCMA_CC_CHIPCTL_DATA 0x0654
#define BCMA_CC_REGCTL_ADDR 0x0658
#define BCMA_CC_REGCTL_DATA 0x065C
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
/* NAND flash MLC controller registers (corerev >= 38) */
#define BCMA_CC_NAND_REVISION 0x0C00
#define BCMA_CC_NAND_CMD_START 0x0C04
#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
#define BCMA_CC_NAND_SPARE_RD0 0x0C20
#define BCMA_CC_NAND_SPARE_RD4 0x0C24
#define BCMA_CC_NAND_SPARE_RD8 0x0C28
#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
#define BCMA_CC_NAND_SPARE_WR0 0x0C30
#define BCMA_CC_NAND_SPARE_WR4 0x0C34
#define BCMA_CC_NAND_SPARE_WR8 0x0C38
#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
#define BCMA_CC_NAND_CONFIG 0x0C48
#define BCMA_CC_NAND_TIMING_1 0x0C50
#define BCMA_CC_NAND_TIMING_2 0x0C54
#define BCMA_CC_NAND_SEMAPHORE 0x0C58
#define BCMA_CC_NAND_DEVID 0x0C60
#define BCMA_CC_NAND_DEVID_X 0x0C64
#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
#define BCMA_CC_NAND_READ_ADDR 0x0C94
#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
#define BCMA_CC_NAND_SPARE_RD16 0x0D30
#define BCMA_CC_NAND_SPARE_RD20 0x0D34
#define BCMA_CC_NAND_SPARE_RD24 0x0D38
#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
#define BCMA_CC_NAND_CACHE_DATA 0x0D44
#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
#define BCMA_CC_PMU5_MAINPLL_MEM 2
#define BCMA_CC_PMU5_MAINPLL_SSB 3
/* PLL usage in 4716/47162 */
#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
/* PLL usage in 5356/5357 */
#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
/* 4706 PMU */
#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
/* PMU rev 15 */
#define BCMA_CC_PMU15_PLL_PLLCTL0 0
#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
/* ALP clock on pre-PMU chips */
#define BCMA_CC_PMU_ALP_CLOCK 20000000
/* HT clock for systems with PMU-enabled chipcommon */
#define BCMA_CC_PMU_HT_CLOCK 80000000
/* PMU rev 5 (& 6) */
#define BCMA_CC_PPL_P1P2_OFF 0
#define BCMA_CC_PPL_P1_MASK 0x0f000000
#define BCMA_CC_PPL_P1_SHIFT 24
#define BCMA_CC_PPL_P2_MASK 0x00f00000
#define BCMA_CC_PPL_P2_SHIFT 20
#define BCMA_CC_PPL_M14_OFF 1
#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
#define BCMA_CC_PPL_MDIV_WIDTH 8
#define BCMA_CC_PPL_NM5_OFF 2
#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
#define BCMA_CC_PPL_NDIV_SHIFT 20
#define BCMA_CC_PPL_FMAB_OFF 3
#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
#define BCMA_CC_PPL_MRAT_SHIFT 28
#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
#define BCMA_CC_PPL_ABRAT_SHIFT 27
#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
#define BCMA_CC_PPL_PLLCTL_OFF 4
#define BCMA_CC_PPL_PCHI_OFF 5
#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
#define BCMA_CC_PMU_PLL_CTL0 0
#define BCMA_CC_PMU_PLL_CTL1 1
#define BCMA_CC_PMU_PLL_CTL2 2
#define BCMA_CC_PMU_PLL_CTL3 3
#define BCMA_CC_PMU_PLL_CTL4 4
#define BCMA_CC_PMU_PLL_CTL5 5
#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
/* BCM4331 ChipControl numbers. */
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
/* 43224 chip-specific ChipControl register bits */
#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
/* 4313 Chip specific ChipControl register bits */
#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
/* BCM5357 ChipControl register bits */
#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
#define BCMA_RES_4314_LPLDO_PU BIT(0)
#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
#define BCMA_RES_4314_PMU_BG_PU BIT(2)
#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
#define BCMA_RES_4314_CLDO_PU BIT(5)
#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
#define BCMA_RES_4314_WL_PMU_PU BIT(7)
#define BCMA_RES_4314_LNLDO_PU BIT(8)
#define BCMA_RES_4314_LDO3P3_PU BIT(9)
#define BCMA_RES_4314_OTP_PU BIT(10)
#define BCMA_RES_4314_XTAL_PU BIT(11)
#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
#define BCMA_RES_4314_LQ_AVAIL BIT(13)
#define BCMA_RES_4314_LOGIC_RET BIT(14)
#define BCMA_RES_4314_MEM_SLEEP BIT(15)
#define BCMA_RES_4314_MACPHY_RET BIT(16)
#define BCMA_RES_4314_WL_CORE_READY BIT(17)
#define BCMA_RES_4314_ILP_REQ BIT(18)
#define BCMA_RES_4314_ALP_AVAIL BIT(19)
#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
#define BCMA_RES_4314_RADIO_PU BIT(23)
#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
#define BCMA_RES_4314_RX_LDO_PU BIT(26)
#define BCMA_RES_4314_TX_LDO_PU BIT(27)
#define BCMA_RES_4314_HT_AVAIL BIT(28)
#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
struct bcma_chipcommon_pmu {
u8 rev; /* PMU revision */
u32 crystalfreq; /* The active crystal frequency (in kHz) */
};
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
bool present;
u8 buswidth;
u32 window;
u32 window_size;
};
#ifdef CONFIG_BCMA_SFLASH
struct bcma_sflash {
bool present;
u32 window;
u32 blocksize;
u16 numblocks;
u32 size;
struct mtd_info *mtd;
void *priv;
};
#endif
#ifdef CONFIG_BCMA_NFLASH
struct mtd_info;
struct bcma_nflash {
bool present;
bool boot; /* This is the flash the SoC boots from */
struct mtd_info *mtd;
};
#endif
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
unsigned int irq;
unsigned int baud_base;
unsigned int reg_shift;
};
#endif /* CONFIG_BCMA_DRIVER_MIPS */
struct bcma_drv_cc {
struct bcma_device *core;
u32 status;
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
u8 early_setup_done:1;
/* Fast Powerup Delay constant */
u16 fast_pwrup_delay;
struct bcma_chipcommon_pmu pmu;
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash pflash;
#ifdef CONFIG_BCMA_SFLASH
struct bcma_sflash sflash;
#endif
#ifdef CONFIG_BCMA_NFLASH
struct bcma_nflash nflash;
#endif
int nr_serial_ports;
struct bcma_serial_port serial_ports[4];
#endif /* CONFIG_BCMA_DRIVER_MIPS */
u32 ticks_per_ms;
struct platform_device *watchdog;
/* Lock for GPIO register access. */
spinlock_t gpio_lock;
#ifdef CONFIG_BCMA_DRIVER_GPIO
struct gpio_chip gpio;
struct irq_domain *irq_domain;
#endif
};
struct bcma_drv_cc_b {
struct bcma_device *core;
u8 setup_done:1;
void __iomem *mii;
};
/* Register access */
#define bcma_cc_read32(cc, offset) \
bcma_read32((cc)->core, offset)
#define bcma_cc_write32(cc, offset, val) \
bcma_write32((cc)->core, offset, val)
#define bcma_cc_mask32(cc, offset, mask) \
bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
#define bcma_cc_set32(cc, offset, set) \
bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
#define bcma_cc_maskset32(cc, offset, mask, set) \
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
/* Chipcommon GPIO pin access. */
u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
/* PMU support */
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
u32 value);
extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
u32 mask, u32 set);
extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set);
extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set);
extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
#endif /* LINUX_BCMA_DRIVER_CC_H_ */

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include/linux/bcma/bcma_driver_gmac_cmn.h Normal file
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#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
#include <linux/types.h>
#define BCMA_GMAC_CMN_STAG0 0x000
#define BCMA_GMAC_CMN_STAG1 0x004
#define BCMA_GMAC_CMN_STAG2 0x008
#define BCMA_GMAC_CMN_STAG3 0x00C
#define BCMA_GMAC_CMN_PARSER_CTL 0x020
#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
#define BCMA_GMAC_CMN_PA_START 0x40000000
#define BCMA_GMAC_CMN_PHY_CTL 0x104
#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
#define BCMA_GMAC_CMN_PC_MTE 0x00800000
#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
#define BCMA_GMAC_CMN_UDF_0_A8 0x308
#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
#define BCMA_GMAC_CMN_UDF_1_A8 0x318
#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
#define BCMA_GMAC_CMN_UDF_2_A8 0x328
#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
#define BCMA_GMAC_CMN_UDF_0_B8 0x338
#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
#define BCMA_GMAC_CMN_UDF_1_B8 0x348
#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
#define BCMA_GMAC_CMN_UDF_2_B8 0x358
#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
#define BCMA_GMAC_CMN_UDF_0_C8 0x368
#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
#define BCMA_GMAC_CMN_UDF_1_C8 0x378
#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
#define BCMA_GMAC_CMN_UDF_2_C8 0x388
#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
struct bcma_drv_gmac_cmn {
struct bcma_device *core;
/* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
* BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
struct mutex phy_mutex;
};
/* Register access */
#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
extern void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
#else
static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
#endif
#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */

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include/linux/bcma/bcma_driver_mips.h Normal file
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#ifndef LINUX_BCMA_DRIVER_MIPS_H_
#define LINUX_BCMA_DRIVER_MIPS_H_
#define BCMA_MIPS_IPSFLAG 0x0F08
/* which sbflags get routed to mips interrupt 1 */
#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
/* which sbflags get routed to mips interrupt 2 */
#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8
/* which sbflags get routed to mips interrupt 3 */
#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16
/* which sbflags get routed to mips interrupt 4 */
#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24
/* MIPS 74K core registers */
#define BCMA_MIPS_MIPS74K_CORECTL 0x0000
#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
#define BCMA_MIPS_MIPS74K_BIST 0x000C
#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
#define BCMA_MIPS_MIPS74K_INTMASK(int) \
((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C
#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040
#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044
#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
#define BCMA_MIPS_OOBSELINA74 0x004
#define BCMA_MIPS_OOBSELOUTA30 0x100
struct bcma_device;
struct bcma_drv_mips {
struct bcma_device *core;
u8 setup_done:1;
u8 early_setup_done:1;
};
#ifdef CONFIG_BCMA_DRIVER_MIPS
extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
extern unsigned int bcma_core_irq(struct bcma_device *core);
#else
static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
static inline unsigned int bcma_core_irq(struct bcma_device *core)
{
return 0;
}
#endif
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */

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